Abstract: A system controller is presented that controls an output format of data according to a data congestion status of the data and then outputs the data over an output bus. Specifically, if there is data congestion, the system controller changes the format of the data to a format that matches a bus width of the output bus before outputting the data over the output bus. To give a specific example, the system controller changes the format of the data input over an input bus in an input format of 4 B to an output format of 5 B before outputting the data over the output bus. If there is no data congestion, the system controller outputs the data over the output bus without changing the input format.

Abstract: A system having a memory device accessible by a plurality of processors is provided. The system includes a memory device, a first processor, and a second processor. The memory device has a first memory array part and a second memory array part. The first processor predominantly accesses the first memory array part of the memory device and selectively accesses the second memory array part of the memory device. The second processor predominantly accesses the second memory array part of the memory device and selectively accesses the first memory array part of the memory device.

Abstract: A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories.

Abstract: A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories.

Abstract: A display device communicating with a microcontrol unit by data, including: a panel with a plurality of pixels; and a display driver operating to drive the panel, in which the display driver includes: a data bus with a plurality of widths; a register storing an index and parameter input from the microcontrol unit through the data bus; and a bus width control circuit selecting one of the plurality of widths with reference to the index and parameter stored in the register and conducting data communication with the microcontrol unit by means of the selected bus width. An index or parameter is introduced for transferring information to configure a data bus width, so that it is possible to reduce the number of mode set pins for determining the data bus width.

Abstract: Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes.

Abstract: A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.

Abstract: A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories.

Abstract: A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories.

Abstract: A method may be provided to communicate a plurality of groups of output data bits representing a respective plurality of groups of input data bits over a data bus with each group of output data bits and each group of input data bits have an equal data width. Each of the plurality of groups of input data bits at may be received at a data register. For each group of input data bits received at the data register, if a number of data bits of the group of input data bits having a first logic level is greater than half of the data width, the group of input data bits are inverted, the inverted group of input data bits are transmitted as a respective group of output data bits in parallel over the data bus, and an inversion flag associated with the respective group of output data bits is transmitted.

Abstract: A data logger is disclosed wherein a common housing includes different function blocks which are connected to one another. These function blocks include at least one analog/digital converter for conversion of measurement signals into digital input data, a memory unit for recording of digital data and of digitized event data, a timer, a processor unit for processing of data, a power supply source and input and output interfaces for measurement signals or digital data and event data. The processor unit is configured for conversion of digital input data and time data into a format which is compatible with standardized software (e.g., freely available) and which makes it possible to display the processed data using standardized software in tabular and/or graphic form on an output device.

Abstract: A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device having a third parallel port; and a path selector being selectively configurable to provide either (i) a first signal path between the first and second parallel ports, or (ii) a second signal path between the first and third parallel ports.

Abstract: A data generator provides faster data than before. A parallel data generator 18 provides first data having four or five effective data width according to a divided clock DCLK. A bit width adjuster 20 having a FIFO memory receives the first parallel data to provide second parallel data of constant four bit width despite of the bit width of the first parallel data. A parallel to serial converter 12 converts the second parallel data into serial data according to a reference clock RCLK that is faster than divided clock DCLK. The frequency of the divided clock DCLK can be constant, which makes it possible to use DLL to fasten the operation of the logic circuits.

Abstract: A bus arbitration system, medium, and method. The bus arbitration system can arbitrate access to a bus for a plurality of masters, requesting the use of a bus to which at least one slave is connected, and may include a bus use granting unit that outputs a plurality of bus grant signals for granting the use of the bus to the plurality of masters that request the use of the bus at the same time, a simultaneous processing available signal selecting unit that selects a predetermined number of operation instruction signals having a predetermined similarity, from among a plurality of operation instruction signals that are input from the masters, in response to the bus grant signals, and an operation instructing unit that simultaneously transmits the selected operation instruction signals to the slave through the bus.

Abstract: There is provided a method and apparatus for bus negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad indicating whether a host is configured to communicate with a fixed data storage device or a removable data storage device. If the first bond pad indicates the host is configured to communicate with a fixed data storage device, then the method additionally includes determining the configuration of a second bond pad. The second bond pad indicates the supported bus width of the fixed data storage device.

Abstract: Disclosed herein is an image processing apparatus including an input section, a bus, a memory interface, an output section, and a control section.

Abstract: The storage control device of the present invention is able to perform input and output of data between blocks whose size is different with good efficiency. The size of extended logical blocks, which are units of data input and output within a storage control device, and the size of physical blocks, which are provided within the storage device, are different from one another. A write object range generation unit reads out both of the extended logical blocks which are adjacent to the write data, and creates a write object range by linking them to the write data. An assurance code checking unit checks a corresponding assurance code for each of these extended logical blocks. And a block size adjustment unit deletes superfluous data from the adjacent blocks, and adjusts the size of the write object range, so that it becomes an integral multiple of the size of the physical blocks.

Abstract: A memory cell array includes a plurality of memory cells, in which n (n is a natural number equal to 3 or larger) cells are simultaneously written. A control circuit controls the memory cell array. A conversion circuit converts data constituted of k (k is equal to n or smaller, and is a natural number equal to 3 or larger) bits stored in the memory cells into data of h (h is equal to k or larger, and is a natural number equal to 2 or larger) bits on the basis of a conversion rule.

Abstract: A method for interfacing single transfer and burst transfer components, comprising: processing transfer completion of a byte in burst transfer as an interrupt; maintaining the current state of signal lines to prevent occurrence of next interrupt; copying the transferred byte from buffer to memory; and allowing next interrupt; and enabling sending of next byte in burst transfer. This invention interfaces incompatible signaling of the components, and solves the handshake, communication and buffering problems involved.

Abstract: A communication data processing device according to an aspect of the invention includes a memory storing data, a data bus transmitting data read from the memory, a plurality of buffer memories temporarily storing data from the memory via the data bus and being capable of receiving and providing data independently of each other, a bus arbiter arbitrating use of the data bus to control data read from the memory to the plurality of buffer memories, an aligner aligning input data in a sequence corresponding to a packet communication, and a selector selecting a buffer memory from the plurality of buffer memories to output data from the selected buffer memory toward the aligner.

Abstract: A method of having multiple devices share a circuit's input/output (I/O) terminals includes applying first and second input signals to first and second I/O terminals to generate first and second output signals at the second and first I/O terminals, respectively. The first and second I/O terminals are coupled to first, second, and third devices via a plurality of signal paths. The method determines which, if any, of the first, second, and third devices is activated based on the first and second output signals. In some embodiments, the three devices correspond to three key switches of a keyboard through which a user can enter operation instructions. In some other embodiments, the three devices correspond to three signal receivers, which are controlled by a local or remote signal source that transmits activation signals in a wired or wireless manner.

Abstract: A production tool for low-level format of a storage device is disclosed. The production tool includes an input connector connectable and an output connector, both of which conform to an interface standard. At least a redundant pin of the input connector is unconnected with a corresponding redundant pin of the output connector, and the redundant pin of the output connector is electrically connected to receive a provided predetermined signal, the presence of which indicating a low-level format mode.

Abstract: A method and apparatus for transmitting a signal to a remote location. The method splits the signal into a multitude of signals that are transmitted down cables. The split signals are collected into a single signal at the receiving end at the remote location. An apparatus for splitting the signals and collecting the split signals is illustrated.

Abstract: This invention discloses an interface card built in each single unit of a CTI system and connected to the Voice Processing Unit (VPU) of the single unit via local CT-BUS. On the transmitting side of an interface card, low-speed signals from the VPU in the single unit are multiplexed into a single high-speed signal and converted into LVDS signals. On the receiving side of the interface card, external high-speed LVDS signals are converted into low voltage TTL signals, demultiplexed into local CT-BUS compatible low-speed signals and sent to the VPU in the single unit. The invention also discloses a CTI system applying the interface card. The interface card and the CTI system applying the interface card feature low cost, simple and reliable connection, easy installation and operation, high reliability, large channel capacity and good expandability.

Abstract: A semiconductor integrated circuit provided with an (m×n)-bit output mode and an n-bit output mode and including a set of (m×n) I/O portions 103 for outputting signals to the outside, wherein data with a bus width of (m×n) bits are selected by a set of selectors 101 in the (m×n)-bit output mode so that the data with the bus width of (m×n) bits are outputted from the set of (m×n) I/O portions 103 whereas data with a bus width of n bits are multiply selected by the set of selectors 101 in the n-bit output mode so that the data with the bus width of n bits are outputted from the set of (m×n) I/O portions 103 while multiplexed in at least two I/O portions per bit. Every I/O portions which output one and the same bit are short-circuited externally to improve current drive capacity.

Abstract: The present invention provides a system bus control apparatus that effectively utilizes a system bus to the full and realizes efficient data transfer. A system bus control apparatus includes a system bus that is a path of data transferred from a bus master, a bus condition monitoring section that monitors a used condition or unused condition of the system bus, a bus allocating section that allocates a bus width permitted to be transferred by the bus master based on the used condition or unused condition of the system bus monitored by the bus condition monitoring section, when the bus master issues a transfer request, and a bus width variable section that changes the bus width of the data transferred from the bus master in accordance with the allocated bus width. Accordingly, the bus width of the data to be transferred is changed in accordance with the bus width permitted to be used, whereby the transfer request is not brought into a stand-by condition.

Abstract: A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device having a third parallel port; and a path selector being selectively configurable to provide either (i) a first signal path between the first and second parallel ports, or (ii) a second signal path between the first and third parallel ports.

Abstract: Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes.

Abstract: An enhanced switch/network adapter port incorporating shared memory resources (“SNAPM™”) selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module (“FB-DIMM”) format for clustered computing systems employing direct execution logic such as multi-adaptive processor elements (“MAP®”, all trademarks of SRC Computers, Inc.). Functionally, the SNAPM modules incorporate and properly allocate memory resources so that the memory appears to the associated dense logic device(s) (e.g. a microprocessor) to be functionally like any other system memory such that no time penalties are incurred when accessing it.

Abstract: There is provided a method and apparatus for bus negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad indicating whether a host is configured to communicate with a fixed data storage device or a removable data storage device. If the first bond pad indicates the host is configured to communicate with a fixed data storage device, then the method additionally includes determining the configuration of a second bond pad. The second bond pad indicates the supported bus width of the fixed data storage device.

Abstract: An improved hibernation method and system, including the use of a modified DMA (Direct Memory Access) mode of transferring data to and from the disk. The use of DMA increases data transfer speed, while freeing the system processor to perform other tasks, including compressing/decompressing the data transferred to and from the disk. An improved decoder is also provided that reduces the number of bounds checks needed on average for typical compressed data by first guaranteeing that there is sufficient room to decode literals and small substrings, whereby bounds checking is not needed. A combination hibernation mode and a suspend mode is also provided that essentially maintains power to the RAM while transparently backing the RAM with the hibernation file, such that if power to the RAM is interrupted, the RAM contents are automatically restored from the hibernation file when power is restored.

Abstract: There is provided a method and apparatus for bus width negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad indicating whether a host is configured to communicate with a fixed data storage device or a removable data storage device. If the first bond pad indicates the host is configured to communicate with a fixed data storage device, then the method additionally includes determining the configuration of a second bond pad. The second bond pad indicates the supported bus width of the fixed data storage device.

Abstract: A method and apparatus for transferring wide data (e.g., n bits) from a narrow bus (m bits, where m<n) for updating a wide data storage array. The apparatus includes: a staging latch accommodating m bits, e.g., 32 bits; control circuitry for depositing the m bits of data from a data bus port into the staging latch addressed using a specific register address; and control circuitry adapted to merging the m bit data contained in the staging latch with m bit data from a data bus port, to generate the n bit wide data, for example, 64 bits, that is written atomically to a storage array specified by an address corresponding to a storage array location.

Abstract: When data is transferred to an access destination in a different endian format, a transfer start address is aligned based on a transfer bus width, and a transfer size is adjusted according to the transfer bus width and a transfer address. Thus, it becomes possible to perform burst transfer in the access destination. Accordingly, in the case where burst transfer to an access destination in a different endian format is performed with a smaller data width than a transfer bus width, an inconvenience where burst transfer can not be performed because an address is converted and data access is no longer an ascending order access can be prevented.

Abstract: A universal cable interface and associated system and method are provided for coupling a transmission medium to a processing device. The universal cable interface can selectively operate in a first (input) mode and a second (output) mode. The universal cable interface can also handle different types of data, such as standard definition video data and high definition video data. When operating in the first mode, the universal cable interface may receive serial data over the transmission medium and convert the serial data into a parallel format for transmission to the processing device. When operating in the second mode, the universal cable interface may receive parallel data from the processing device and convert the parallel data into a serial format for transmission over the transmission medium.

Abstract: A flow-based FIFO sub-system for a disk formatter in a data processing system that performs data width conversion. The sub-system has a first FIFO unit having a first width interfacing to a first bursting channel, and a second FIFO unit having a second width interfacing to a second bursting channel, the second width not being a multiple of the first width and the first width not being a multiple of the second width. Data width conversion is performed between the first FIFO unit and the second FIFO unit to convert data moving from the first FIFO unit to the second FIFO unit from the first width to the second width, and to convert data moving from the second FIFO unit to the first FIFO unit from the second width to the first width. The sub-system also includes an Error Correcting Code interface between the first FIFO unit and the second FIFO unit for performing in-line correction.

Abstract: A peripheral connectable to a processing device includes a housing and network interface circuitry at least partially enclosed within the housing, the network interface circuitry being utilizable by the processing device to establish a connection between the processing device and a network. The peripheral further includes peripheral circuitry disposed within the housing and adapted to perform at least a portion of at least one of an input function and an output function for the processing device in a manner unrelated to utilization of the network interface circuitry by the processing device. In an illustrative embodiment, the network interface circuitry comprises a wireless local area network (LAN) interface card, module or access point, the processing device comprises a computer, and the peripheral comprises a keyboard, monitor, speaker, docking station or other peripheral connectable to the computer.

Abstract: A method and apparatus for maintaining data throughput in a data element includes receiving a clock and a first plurality of instances of data having a first width on an input, sampling consecutive ones of instances of the data having the first width at consecutive ones of a first rising edge and a first falling edge of the clock, respectively, to generate two plurality of instances of sampled data having a first width. The plurality of instances of sampled data is then sampled at a second rising edge of the clock and parallelized to generate a second plurality of instances of parallel data having a second width greater than the first width. The parallel data may then be processed to for example generate statistics to monitor link integrity, prior to being transmitted. A 10 Gbps data transmission speed may be maintained using the IEEE 802.3ae-specified media independent interface clock.

Abstract: Methods and apparatuses are described for a communication system. The communication system comprises an initiator core supporting a first burst capability as well as a target core supporting a second burst capability. The supported burst features of the second burst capability differ from the supported burst features of the first burst capability. The communication system also comprises an agent coupled to the initiator core, which comprises logic to compute target-dependent burst support information across multiple groups of potential targets at the same time. The logic then selects the correct target-dependent information based upon a resulting address decode for the target selection.

Abstract: A system and method for receiving, by a memory device, data in a first format, transforming, by the memory device, the data from the first format to a second format and outputting the data in the second format. An integrated circuit having at least one data segment and a logic circuit receiving and transforming data from a first format to a second format.

Abstract: A method for optimizing performance of an apparatus includes interrogating at least one part of the apparatus to obtain information about the at least one part. Once the at least one part is interrogated, instructions for optimizing at least one operation of the apparatus is determined based on the obtained information about the at least one part. Next, the instructions are applied to the at least one operation of the apparatus to optimize the performance.

Abstract: A serial communication system includes a first and second communication devices for transmitting first signals in a first standard with each other; a convertor for receiving and converting the first signals into second signals in a second standard; a controller for generating third signals in the second standard according to the second signals; and a processing unit for receiving the third signals and generating data corresponding to the first signals in responding the received third signals. A related monitor device is also provided.

Abstract: A DVD reproducing device is capable of being connected to a certain external electronic device. The DVD reproducing device includes an external input receiving unit connected with the external electronic device to receive an external input signal from the external electronic device. A key input receiving unit receives a user selection signal for selecting whether or not the external input signal is transformed. An external signal processing unit transforms the external input signal into a certain form according to a user selection signal.

Abstract: An electronic data processing circuit contains a plurality of data handling units (10a-d, 16a-b) with data outputs, at least part of the data handling units having address outputs. The data handling units supply words of preferably selectable size to a bus. A bus controller (20) is arranged to control access to the bus in successive access cycles. The bus controller (20) causes data bits from a plurality of data words from respective ones of the data handling units (10a-d, 16a-b), to be placed in combination on the data lines in a same bus cycle. The bus controller causes write addresses that the respective ones of the data handling units (10a-d, 16a-b) supply for respective ones of the plurality of data words to be placed on the address lines in a plurality of respective bus cycles. Preferably, the temporal or spatial arrangement of the data words on the bus lines adapted so as to minimize the number of logic level changes on the bus.

Abstract: A system controller is presented that controls an output format of data according to a data congestion status of the data and then outputs the data over an output bus. Specifically, if there is data congestion, the system controller changes the format of the data to a format that matches a bus width of the output bus before outputting the data over the output bus. To give a specific example, the system controller changes the format of the data input over an input bus in an input format of 4 B to an output format of 5 B before outputting the data over the output bus. If there is no data congestion, the system controller outputs the data over the output bus without changing the input format.

Abstract: The storage control device of the present invention is able to perform input and output of data between blocks whose size is different with good efficiency. The size of extended logical blocks, which are units of data input and output within a storage control device, and the size of physical blocks, which are provided within the storage device, are different from one another. A write object range generation unit reads out both of the extended logical blocks which are adjacent to the write data, and creates a write object range by linking them to the write data. An assurance code checking unit checks a corresponding assurance code for each of these extended logical blocks. And a block size adjustment unit deletes superfluous data from the adjacent blocks, and adjusts the size of the write object range, so that it becomes an integral multiple of the size of the physical blocks.

Abstract: In at least some embodiments, a method comprises receiving an external card detection signal that indicates that a hot-pluggable card is coupled to a computer system and activating at least one reference clock signal of a scalable reference clock platform based on the external card detection signal. The method further comprises synchronizing clock signals embedded in data packets transmitted between the hot-pluggable card and the computer system with another clock signal bases on the at least one reference clock signal.

Abstract: A semiconductor device includes a first circuit block, a second circuit block, and a data bus. The data bus is coupled between the first and second circuit blocks. A first data inverter on the data bus inverts a selected segment of data that is transferred onto the data bus. A second data inverter at an end of the data bus re-inverts the selected segment of data before the data is transferred off the data bus. The data that is transferred onto the data is not analyzed in order to determine the selected segment of data that is inverted.

Abstract: Disclosed herewith is a semiconductor data processing device that realizes low power consumption at the standby time and at the operation time, as well as speeds up the interfacing operation. The semiconductor data processing device can connect a non-volatile storage device to a general-purpose bus of a host system. The data processing device enters the active or standby state in response to the state of the general-purpose bus. In the standby state, the data processing device stops the internal clock signal and applies a substrate bias voltage to each object so as to suppress the potential sub-threshold leak current therefrom. This bias voltage is also applied to the central processing unit and the rewritable non-volatile memory for storing a control program to be executed by the central processing unit. The central processing unit processes data in units of n bits or below when the interface controller and the data transfer controller input/output parallel data in units of 2n bits.

Abstract: A network system connects with processes P1 to P5 that can mutually send and receive a broadcast message specified with no destination and a message specified with a specific process portion and change their states to parent or child processes. For example, process P1 is a parent process and processes P2 to P4 are child processes. When processes P1 to P4 constitute a group, each of child processes P2 to P4 stores parent process P1. Parent process P1 stores each of child processes P2 to P4 that store itself (P1). When process P5 in another group is connected, parent process P1 exchanges a message with process P5 for negotiation to determine either to be a parent process and change the other to a child process.