Abstract: A tunnel device for an input/output node of a computer system. A tunnel device includes a first interface, a second interface and a control unit. The first interface may receive a plurality of data bytes associated with a command packet on a first external input/output bus. The second interface may be coupled to the first interface by an internal data path configured to convey up to a maximum number of data bytes in a given cycle. The control unit may be coupled to control the conveyance of the data bytes from the first interface to the second interface upon the internal data path. The first interface may further align the smaller number of data bytes on a corresponding number of designated bits of the internal data path with no intervening invalid data bytes when conveying a smaller number of data bytes than the maximum number of data bytes.

Abstract: A DMA control circuit controls DMA transfer between a flash memory and a main memory. An S/P bus conversion circuit converts serial data output from the flash memory into parallel data and outputs the parallel data to the main memory. This eliminates the need for the CPU downloading file data from the flash memory to the main memory, allowing connection of a non-volatile memory with a large capacity, without reduction in the processing speed of the system.

Abstract: A system and corresponding method for improving set-top box boots up efficiency while, at the same time, reducing the memory allocation required for set-top box boot-up is disclosed. The boot-up method includes performing a vertical direct memory access transfer of relevant program instructions from a system non-volatile memory to system main memory. The transferred program instructions are then re-arranged into consecutive locations within the main memory.

Abstract: A process control system uses an asset optimization reporter to collect status information pertaining to the assets of a process plant from various data sources of the plant including, for example, data tools, data collectors, and data generators. This status information is used to generate reports that may be displayed to various users, including maintenance persons, process control persons and business persons. The status information may be used as the basis for further types of status information and/or be categorized in ways that are useful to the user. The reports are generally displayed via a user interface routine that enables users to view the status information and manipulate the display of the report to correspond to the user's preferences, as contained in a user profile. The user interface routine further enables the user to view reports of various types of status information for various devices, loops, units, areas, etc.

Abstract: A system includes an application processor and a baseband processor that may be configurable to communicate by the transfer of data in a hexadecimal format, an octal format or a decimal format in accordance with programmed bits in a register's data field.

Abstract: The invention provides a data output control apparatus which is suitable for allowing detailed information on a network to be readily obtained. A data output control terminal selects one of printing apparatuses corresponding to a data-format-conversion terminal which allows conversion of data associated with a data print request; outputs the data associated with the data print request to the data-format-conversion terminal allowing conversion of the data and corresponding to the printing apparatus; by the data-format-conversion terminal, converts the data associated with the data print request into data which can be printed by the printing apparatus; and outputs the converted data to the printing apparatus. One or more of data-format-conversion terminals is selected in accordance with the transmission load of the Internet, and data-format-conversion processes are executed by the data-format-conversion terminal.

Abstract: In a computer system, a first processor, a second processor for use as a coprocessor to the first processor, a memory, a data buffer for buffering data to be written to or read from the memory in data bursts in accordance with burst instructions, a burst controller for executing the burst instructions, a burst instructions element for providing burst instructions in a sequence for execution by the burst controller, and a synchronization mechanism for synchronizing execution of coprocessor instructions and burst instructions with availability of data on which said coprocessor instructions and burst instructions are to execute. Burst instructions are provided by the first processor to the burst instructions element and data is read from the memory as input data to the second processor and written to the memory as output data from the second processor through the data buffer in accordance with burst instructions executed by the burst controller.

Abstract: A circuit that merges and aligns data that resides in a buffer entry is described. The data residing in the buffer entry is divided into a prepend portion and a payload portion. The prepend and the payload portions of the data are each defined, in part, by a length and an offset. Given the lengths and offsets, the circuit fetches the data from the buffer entry, merges the data, and aligns the data.

Abstract: A method and computer program for data conversion in a heterogeneous communications network. This method and computer program converts data for computer systems having different data storage architectures so that these computer systems may simply and easily communicate over a network. This is most useful when converting data stored in little endian and big endian format. This method relies on creating the data structure used to convert the data using embedded macros that are not executed at run time. These embedded macros are expanded by the compiler to generate the data structure and thereby saves substantial time during execution.

Abstract: In a data processing system, the effective speed of transferring data packets between a data processing unit and various other devices with different performance characteristics is improved by a data transfer method and a packing and buffering device, thus offloading the data processing unit or the various devices. FIFO buffers provide intermediate storage of transfer data, and packing and unpacking modules ensure efficient use of bus widths that are different on the data processing side and the device side. Data packet transfer control is effected using a control and status module with a common byte counter, and a direct transfer is facilitated via a supplementary direct data path between the data processing unit and other devices.

Abstract: A circuit that merges and aligns data that resides in a buffer entry is described. The data residing in the buffer entry is divided into a prepend portion and a payload portion. The prepend and the payload portions of the data are each defined, in part, by a length and an offset. Given the lengths and offsets, the circuit fetches the data from the buffer entry, merges the data, and aligns the data.

Abstract: A system and method to perform partial byte writes in a processor circuit is disclosed. The system comprises a bit assembly circuit having a bit assembly register with a corresponding shadow register. Also included is a bit routing circuit configured to transfer at least one data bit from a data bus to a predetermined register position in the bit assembly register and a shadow bit from the data bus to a corresponding register position in the shadow register. The shadow bit indicates that the data bit written comprises valid data. The bit assembly and shadow registers may receive data directly from the data bus as well. Using this circuitry, a partial parallel data block is assembled in the bit assembly register. Thereafter, the partial parallel data block is transferred to a destination register via the data bus with corresponding shadow bits being transmitted to the destination shadow register. The valid data is processed accordingly.

Abstract: This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile, so-called flash memory into an ICs. Such a flash memory may be integrated by providing a dedicated flash bus which operationally links the flash memory with one or more microprocessors on the IC. Unfortunately, flash memories have relatively long access times compared to usual modern microprocessors. To achieve that the flash memory keeps pace with the microprocessor(s), a dedicated flash bus (2) links the flash memory (1) to the microprocessor (3), said flash bus (2) having a width m which is greater than the width n of the microprocessor's data bus (8). Preferably, width m is a multiple of width n. A plurality of intermediate storage registers (4) connects the flash bus (2) with the data bus (8) of the microprocessor (3) for performing the width conversion.

Abstract: In one embodiment, a bus multiplexer is between a memory and a functional unit of the integrated circuit. An input of the bus multiplexer couples to a global bus having a bit width. A local bus having a lesser bit width couples to an output of the bus multiplexer. The bus multiplexer selectively multiplexes bits of data on the global bus onto bits of the local bus. In another embodiment, an integrated circuit comprises a memory, a global bus, and a functional unit coupled together. The functional unit includes a bus multiplexer with an input coupled to the global bus, and a local bus coupled to an output of the bus multiplexer. The bus width of the local bus is less than that of the global bus. The bus multiplexer selects data from a subset of bits of the global bus to couple onto the bits of the local bus.

Abstract: A tape drive method and apparatus is disclosed wherein payload data is sent from a host computer device to a tape drive data storage device in data block sizes which are specified by the host computer, for example in the case of a tape drive presenting a CD-ROM image, in 2 kbyte blocks, whereas the tape drive writes to tape media in an optimal block size required to keep the tape media streaming across the tape heads, for example 8 kbyte blocks. Conversion between block size is achieved by buffering incoming payload data in a buffer, and by reading or writing to the tape media in the optimum block size.

Abstract: An apparatus is contemplated, including a router and a memory controller. The router is configured to route a write request and write data to the memory controller. The memory controller is coupled to receive the write request and the write data. If the write data is a number of bytes less than a minimum number of bytes writeable to a memory to which the memory controller is capable of being coupled, the memory controller is configured to read first data from the memory. The first data comprises the minimum number of bytes and includes bytes to be updated with the write data. The memory controller is configured to return the first data to the router as a read response. The router is configured to return the first data to the memory controller.

Abstract: A switching router memory map is organized as 64-bit wide double words. The bi-directional data bus is only 32-bits wide, so the Least Significant Words (LSW) are mapped to the even addresses and the Most Significant Words (MSW) are mapped to the odd address. When the host writes to the even address the 32-bit data is stored in the bidirectional data bus buffer. When the host writes to the odd address the entire 64-bit double word access is posted to the appropriate global access bus. When a read operation is performed from an even address the entire 64-bit double word access is performed by the appropriate global access bus. The LSW is available on the bi-directional data bus address data pins and the 32-bit MSW is buffered within the bi-directional data bus. The host can access the MSW by performing a read from the odd address.

Abstract: A coding device and method in which m-bit information words are converted into n-bit code words such that the coding rate m/n is greater than ½. The coding device and method are also employed to record information on a recording medium and to transmit information. In the decoding method and apparatus, n-bit code words are decoded into m-bit information words. The decoding involves determining the state of a next n-bit code word, and based on the state determination, the current n-bit code word is converted into an m-bit information word. The decoding device and method are employed to reproduce information from a recording medium, and to receive information transmitted over a medium.

Abstract: A memory that supports non-aligned memory accesses includes a field address generator circuit, multiple field memories, and a data rotation circuit. The field address generator circuit generates multiple field addresses in response to an address associated with a memory access. Each field memory receives one of the field addresses from the field address generator circuit. The data rotation circuit rotates data associated with the memory access based upon the memory access address to support a non-aligned access. The memory can support either non-aligned read accesses or non-aligned write accesses. A method for performing non-aligned read or write memory accesses is also described.

Abstract: An input device may operate with a variety of different host processor-based systems running a variety of different applications by providing a translation module which translates input commands in one format to a format compatible with one or more applications that may run on a given processor-based system. A table may be provided, for example, in software, which enables a variety of different input device formats to be converted into a variety of formats utilized by an application. In this way, contention between an application and an input device may be resolved.

Abstract: When the data bus is cut off from the CPU (1) and the transmission ready signal (TXRDY) is activated, the DMA control circuit (10) reads 32 bits of data at once according to the lead address of the destined area for storage in the DRAM (2) and the address width that are set by the CPU (1), and stores the data in the transmission buffer (16). The selector (17) selects 8 bits of data at a time from the transmission buffer (16), the data is written to the communication circuit (14) and thus output, the bus release request is cancelled, 8 bits of data is read at a time from transmission buffer (16), and the data is written into the communication circuit (14). When the transmission ready signal is provided once again, the above-described processing is repeated.

Abstract: A system includes an application processor and a baseband processor that may be configurable to communicate by the transfer of data in a hexadecimal format, an octal format or a decimal format in accordance with programmed bits in a register's data field.

Abstract: A system and corresponding method for improving set-top box boots up efficiency while, at the same time, reducing the memory allocation required for set-top box boot-up is disclosed. The boot-up method includes performing a vertical direct memory access transfer of relevant program instructions from a system non-volatile memory to system main memory. The transferred program instructions are then rearranged into consecutive locations within the main memory.

Abstract: A selection circuit causes either a memory 6H or 6L to enter an enabled state according to address data A16 of address data A0-A16 when a mode signal M is 1. The selection circuit comprises OR gates (10, 12) which output different outputs. When the address data A16 is 0, a nonvolatile memory 6L enters an enabled state. Then, the memory 6L is addressed according to the address data A0-A15 so that, for example, 8-bit lower data is written therein. On the other hand, when the address data A16 is 1, a nonvolatile memory 6H becomes in an enabled state. Then, the memory 6H is addressed according to the address data A0-A15 so that, for example, 8-bit upper data is written therein. Also, when an external terminal (17) is grounded, and a mode signal become 0, the OR gates (10, 12) outputs signals 0, so that the memories 6H, 6L simultaneously become in an enabled state. When data is read from corresponding addresses of each memory, data of, for example, 16-bits is obtained.

Abstract: A direct memory access (DMA) controller provides seven DMA channels configurable for a PC/AT compatible mode or an enhanced mode. In an enhanced mode of the DMA controller, three DMA master channels on a master DMA controller and a DMA channel on a slave DMA controller are individually configurable to be either 8-bit or 16-bit DMA channels. In addition, in the enhanced mode, a memory address can increment or decrement across a memory page boundary. The DMA controller includes a transfer count register selectively configured for 16-bit operation or 24-bit operation. The DMA controller also includes address generation logic selectively configured for 24-bit operation or 28-bit operation. In the PC/AT compatible mode, the DMA controller supports three 16-bit channels and four 8-bit channels. The DMA controller thus provides DMA channel width configurability.

Abstract: A method of operating a processor (30). The method comprises a first step of fetching an instruction (20). The instruction includes an instruction opcode, a first data operand bit group corresponding to a first data operand (D1′), and a second data operand bit group corresponding to a second data operand (D2′). At least one of the first data operand and the second data operand consists of an integer number N bits (e.g., N=32). The instruction also comprises at least one immediate bit manipulation operand consisting of an integer number M bits, wherein 2M is less than the integer number N. The method further includes a second step of executing the instruction, comprising the step of manipulating a number of bits of one of the first data operand and the second data operand. Finally, the number of manipulated bits is in response to the at least one immediate bit manipulation operand, and the manipulating step is further in response to the instruction opcode.

Abstract: A data width conversion apparatus has a buffer for storing output-incomplete partial data of input data received in the past and a block shifter for combining the output-incomplete partial data stored in said buffer with new input data. In the combined data by the block shifter, a portion of a fixed data width is outputted in form of an output data, and data less than the fixed data width or data exceeding the fixed data width is stored in the buffer so as to be combined with the successive input data.

Abstract: A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions requiring multiple cycles by sharing single-cycle operations, thereby reducing both costs and size of the microprocessor. One embodiment handles 288-bit data widths using 36-bit data path slices. Another embodiment executes integer multiply and multiply-and-accumulate and floating point add/subtract and multiply operations using single-cycle arithmetic logic units. Other embodiments support 8-bit, 9-bit, 16-bit, and 32-bit integer data types and 32-bit floating data types.

Abstract: A PCI interface is provided to support a 16- or 32-bit PCI host employing little-endian or big-endian byte ordering. The PCI interface may be arranged on a multiport switch to enable a PCI host to access internal registers and an external memory via a PCI bus. When a 16-bit PCI host is provided with access to a 32-bit internal register, two consecutive 16-bit data transfers are performed. The first 16 bits of data are temporarily stored in a holding register until the following 16 bits are transferred. The PCI host accesses the external memory via posting write buffers and prefetch read buffers arranged between an external memory interface and the PCI interface. When the multiport switch is configured to support a big-endian PCI host, bytes of a word transferred between the external memory and a write or read buffer are swapped to rearrange byte ordering of the word.

Abstract: A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width.

Abstract: A method and apparatus for maintaining data throughput in a data element includes receiving a clock and a first plurality of instances of data having a first width on an input, sampling consecutive ones of instances of the data having the first width at consecutive ones of a first rising edge and a first falling edge of the clock, respectively, to generate two plurality of instances of sampled data having a first width. The plurality of instances of sampled data is then sampled at a second rising edge of the clock and parallelized to generate a second plurality of instances of parallel data having a second width greater than the first width. The parallel data may then be processed to for example generate statistics to monitor link integrity, prior to being transmitted. A 10 Gbps data transmission speed may be maintained using the IEEE 802.3ae-specified media independent interface clock.

Abstract: A computer system comprises: a processing system for processing data; a memory for storing data processed by, or to be processed by, the processing system; a memory access controller for controlling access to the memory; and at least one data buffer for buffering data to be written to or read from the memory. A burst controller is provided for issuing burst instructions to the memory access controller, and the memory access controller is responsive to such a burst instruction to transfer a plurality of data words between the memory and the data buffer in a single memory transaction. A burst instruction queue is provided so that such a burst instruction can be made available for execution by the memory access controller immediately after a preceding burst instruction has been executed.

Abstract: A method for optimizing the performance of a 64-bit PCI initiator when transferring a 64-bit data via a 64-bit PCI bus. The 64-bit PCI initiator receives a single 64-bit data for transfer via the 64-bit PCI bus. The 64-bit PCI initiator breaks the 64-bit data into a first 32-bit data and a second 32-bit data. The 64-bit initiator then initiates a data transaction with the target device arbitrating for ownership of the 64-bit PCI bus. Upon receiving ownership of the 64-bit PCI bus, the 64-bit PCI initiator transfers the first 32-bit data and then transfers the second 32-bit data to the target device via the 64-bit PCI bus. The first 32-bit data and the second 32-bit data are transferred by the 64-bit PCI initiator to the target device without the assertion of a REQ64# signal, such that a REQ64# ACK64# protocol is avoided, enabling a more efficient completion of the data transaction.

Abstract: An architecture, circuitry and method for transmitting n-bit wide data over m-bit wide media that may comprise a first circuit configured to present a first series of data packets having a first bit-width in response to a second series of data packets having a second bit-width and a second circuit configured to present a third series of data packets having said first bit-width in response to said second series of data packets. The first circuit may comprise a buffer circuit configured to hold one or more of the first series of data packets and a packer circuit configured to present the second series of data packets in response to the data packets held in the buffer circuit. The second circuit may comprise an unpacker circuit configured to present the third series of data packets and a buffer circuit configured to hold one or more of the third series of data packets.

Abstract: A system and method that prevents address aliasing and eliminates the unnecessary clock cycle consumed by the use of a dual address cycle when using a single address cycle to transmit a target address in a computer system including target devices having addresses of different sizes, such as 32-bit and 64-bit target devices, with 32-bit and 64-bit addresses, respectively. In addition, a combination of single address cycles and dual address cycles may be used to prevent address aliasing while permitting access to the entire address spaces of the target devices. The computer system includes a bus, an initiator device coupled to the bus, a first target device coupled to the bus, and a second target device coupled to the bus. The first target device has a first address range containing a plurality of bits, and the second target device has a second address range containing a fewer number of bits than the first address range.

Abstract: When writing of data into nonvolatile memories 8H and 8L is started, data D7 and D15 corresponding to the 128th word of a data input section 8B are inverted and outputted. When accurate writing is subsequently performed, the data D7 and D15 are outputted as they are. By monitoring a change of the data D7 and D15 from the nonvolatile memories 8H and 8L, it is possible to detect whether writing is still continuing or has already completed. Thus, by using nonvolatile memories of 8 bit data width or the like, a 16-bit microcomputer can be easily realized.

Abstract: For use in a processor having a result bus of insufficient width to convey all results of a given multiple-result instruction concurrently, a system for, and method of, writing back the results of the multiple-result instruction. In one embodiment, the system includes: (1) multi-result node creation circuitry that creates a multi-result node having at least first and second results for the multiple-result instruction and (2) node transmission circuitry, coupled to the multi-result node creation circuitry, that transmits the first and second results of said multi-result node sequentially over the result bus.

Abstract: A reference value is set for recording quantity of information, and a plurality of compression factors is provided for compressing information to be recorded. The compression factors are arranged in order. The information is sequentially recorded on a first memory at a first compression factor of the arrangement of the compression factors. It is determined whether the recording quantity of a first information group reaches the reference value. The first information group is compressed at a larger second compression factor when the recording quantities reaches the reference value, and the compressed first information group is recorded on the first memory at a first area. A second information group following the first information group is compressed at the second compression factor, and the compressed second information group is recorded on the first memory at a second area next to the first area. It is determined whether the sum of the recorded first and second information groups reaches the reference value.

Abstract: A system for efficiently controlling the exchange of data between a host bus (190) and an input/output (I/O) register (125) of an elliptic curve (EC) processor (120) having a much wider datapath than that of the host device (100) . A spreading/despreading pattern is determined which spans multiple bit positions of the input/output register (125). In one embodiment, a full combinational circuit (300) is provided to connect a bit position of the host bus (190) to a bit position of the input/output register (125). In another embodiment, a combinational circuit (300) and an intermediate register (410) are provided. In still another embodiment, a spreading-by shifting system (500) is provided which comprises a plurality of subfield modules (520) into which data from the host bus (190) is shifted. The spreading/despreading pattern is achieved through multiplexers (540) connected between the subfield modules (520).

Abstract: Permission based flow control is implemented in a computer network having at least a downstream, intermediate and upstream network device by receiving credits at the intermediate network device from the downstream network device and granting credits from the intermediate network device to the upstream network device based at least in part upon the credits received at the intermediate network device from the downstream network device. Credit chaining as described above is employed to permit the granting of the right to transmit downstream to be predicated upon buffer availability downstream of the next downstream network device. Via the use of credit chaining, high utilization of network resources is achieved with minimal loss of data traffic.

Abstract: An apparatus and method for transferring a block of data between a first storage area in a first, unpacked format and a second, narrower storage area in a second, packed format. The present invention includes a set of working registers to temporarily store and manipulate portions of the block of data as it is transferred between the first and second storage areas. By employing this set of working registers, the present invention transfers blocks of data between the first and second storage areas with a low latency and the highest possible throughput.

Abstract: A system and method for eliminating unnecessary data transfers (e.g., null data phase transfers) in a computer system. The computer system comprises a bus, a target device coupled to the bus, and an initiator device coupled to the bus. The initiator device is adapted to transfer a data byte and a signal corresponding to the data byte over the bus to the target device, wherein the signal is equal to a first value to indicate that the target device is to accept the data byte and the signal is equal to a second value to indicate that the target device is to disregard the data byte. The initiator device is further adapted to decode the signal for each of a plurality of data bytes. The initiator device withholds transferring a subset of the data bytes to the target device when the signal corresponding to each of the data bytes in the subset is equal to the second value, thereby eliminating unnecessary data transfers.

Abstract: A system and method for using single address cycles and eliminating dual address cycles to transmit a target address in a computer system. The computer system comprises a bus, a central processing unit coupled to the bus, an initiator device coupled to the bus, and a target device coupled to the bus. The target device comprises a first configuration register which is adapted to use a configuration bit to indicate an address range of the target device. The central processing unit interrogates the first configuration register and communicates the address range indicated by the configuration bit to the initiator device. The initiator device comprises a second configuration register which is adapted to use a configuration bit to register the address range of the target device.

Abstract: A microprocessor circuit arrangement is capable of retrieving and executing program instructions from a program memory having one of multiple possible bit-widths using address signals. A microprocessor uses a set of program instructions to select a memory configuration for retrieving the program instructions. The program memory stores the set of program instructions such that the microprocessor can retrieve the set of program instructions regardless of which bit-width is used to store the set of program instructions. Additional circuitry maps the address signals for retrieving the program instructions from the program memory.

Abstract: A target configuration prediction system that provides an initiator coupled to a bus system with a prediction of the configuration type of a target. The present invention stores information regarding the address and configuration of targets and utilizes this information to predict the address of a target an initiator is currently attempting to access. The prediction is based upon the proximity of stored target addresses to a target address an initiator is currently trying to access and the probability that targets with addresses within certain ranges are the same target configuration type. The configuration type is determined by initiator component logic during an initial attempt at accessing a target and a status bit indicating the configuration type is stored in a status bit component.

Abstract: Configurable I/O circuitry having a plurality of configurable input/output elements, each of which connects one of a plurality of bits of a data bus to a corresponding one of the input/output terminals. Multiple clock selects and programmable enable signals can be connected to different interface elements to control activation of the interface element to which it is connected. The activated interface elements make up a virtual port that can be of any arbitrary bit width that is less than or equal to the fixed width of a physical port. This allows virtual ports on the data bus to be constructed that are narrower than the physical ports so that narrower data can be utilized in the port without causing the potential use of any of the data pins to be lost.

Abstract: A data processing system and a method for inputting data from storage devices provided in the data processing system, in which the ROM address areas in a memory map include an area for reading in a 32-bit bus mode and an area for reading in a 16-bit mode, which areas are set so that a portion of the addresses are equal. When a 32-bit data read is performed for the area used to read in 32-bit bus mode and the high-order 16 bits are invalid, it is determined that only one ROM device is mounted in the system. Therefore, accesses are performed with the area used to read in 16-bit bus mode. After determining the number of ROM devices in this way, the result is written to a mode register. The selector reads this result stored in the mode register and, when only one ROM device is mounted in the system, supplies Address A1 to the highest-order address terminal RA17 of the ROM device.

Abstract: A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.

Abstract: A method of transmitting a printer control file from a host computer to a printer includes the steps of: checking if a printer control file that is in the same format as stored in a non-volatile memory, has been amended; and if the printer control file is amended, storing the amended printer control file. When this process of storing the printer control file is complete, or if the printer control file has not been amended, then the printer control file is read. The read printer control file is transmitted to the printer.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.