Abstract: A method and apparatus for emulating an instruction on a processor. The instruction operates on an operand in a first data format and the processor operates in a second data format. The operand is converted from the first data format to the second data format. The processor then executes the instruction in the second data format to generate a result in the second data format. The result is converted from the second data format to the first data format.

Abstract: A protocol controller connected between a SCSI device and a DMA controller. The SCSI device is connected to the protocol controller with a first bus and the DMA controller is connected to the protocol controller with a second bus having a width less than a width of the first bus. The protocol controller communicates with the SCSI device so that it transfers data having a width equivalent to the width of the second bus. Other data concurrently transferred by the SCSI device over the first data bus is ignored and not transferred to the DMA controller.

Abstract: One aspect of the invention is a shared signal processor comprising input circuitry to receive a plurality of input signals and output circuitry operable to transmit a plurality of output signals. Storage circuitry is operable to store state information and signal data for each of the plurality of input signals and output signals. A state machine is coupled to the input circuitry, output circuitry, and storage circuitry and is operable to poll each input signal and output signal to identify a first signal requiring processing. The state machine is further operable to load the state information and signal data associated with the first signal and process the first signal.

Abstract: A CPU-Peripheral bus interface for 64-bit local bus to 32-bit peripheral bus uses byte enable signaling to provide byte lane steering. Qbuffer logic provides a hardware interface that interfaces directly to the processor local-bus--a Qbuffer protocol using conventional byte enable signals provides lane steering to eliminate the need for separate multiplexing logic. The Qbuffer protocol signals include a BE control signal asserted by the system logic to cause the CPU to relinquish control of the byte enable control lines, such that the system control logic is able to drive the BE control lines with byte enable codes to implement lane steering for CPU-Peripheral transfers.

Abstract: A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width.

Abstract: A method and circuit, for use with a parallel data bus of defined width, which provide a parallel data transmission and reception rate which is greater than the defined width of the parallel data bus. With respect to improving transmission, provided is a width-reduction circuit element, having at least two inputs through which are received a first set of parallel digital data signals and having one or more outputs through which are transmitted a second set of parallel digital data signals where the second set is both smaller than the first set and representative of the information contained within the first set. The one or more outputs interface with a parallel connector which is sufficient to form an operable connection with the parallel data bus of defined width.

Abstract: A system and method is provided by which byte stream data files in industry-standard format can be retrieved from a compact disk and then re-created to provide an original set of native format files suitable for use by a first computer system. Additionally, an integrated network of a first computer platform which utilizes native file formats working in conjunction with a second computer platform which uses byte stream file formats can be utilized so that the second computer platform may transfer the byte stream data files to a commonly shared storage means, such as a disk, after which the first computer platform can then utilize a first interface program and a second interface program in order to convert the byte stream files into copies of the original native file suitable for the first computer platform.

Abstract: A descriptor controlled transmit and receive scatter/gather Direct Memory Access Controller efficiently moves data frames comprised of scattered blocks of data from within memory to a destination interface via a multibyte-wide buffer. The transfer of frames into a transmit buffer and out of a receive buffer is optimized regardless of the total length of the component data blocks and regardless of whether the data blocks include an odd or even number of bytes, whether the data blocks begin at an odd or even address, or whether the data blocks are misaligned with regard to memory width boundaries. A DMAC in accordance with an embodiment of the present invention stores information provided by a descriptor before frame processing takes place. This information in conjunction with steering logic and accumulator registers is used to control the steering and storing of the frame data as it passes through the DMAC to the transmit buffer or from the receive buffer.

Abstract: A bi-directional buffer circuit for transferring data between clock boundaries in a computer system is described. The circuit is divided into halves, with one half being controlled by a first clock and the second half being controlled by a second clock. The incoming data that is synchronized to the first clock is compiled into data blocks and stored into registers before being synchronized and transferred to the other half of the circuit. The data blocks that are stored in the register sent across a the clock boundary the then synchronized into matched registers within the second half of the circuit. In addition, the signals that control the synchronization of data blocks between the halves of the circuit are synchronized by two stages of registers to avoid the problem the metastability.

Abstract: Potable multimedia terminal which is small and consumes low power, can process a large quantity of multimedia data such as video and audio data. Portable multimedia data input/output processor can be made smaller by using a pen as an input device and can also process a large quantity of multimedia data at a high speed by adopting a PCI bus as a local bus of a system. To retrieve, compress, and decompress multimedia data, main components of this portable multimedia data input/output processor are comprised of audio codec for compressing and decompressing audio data, video codec controller for compressing and decompressing video data, and multimedia processor for transmitting audio data to wireless communication controller and video data to video codec controller and to graphic processor. The method for retrieving multimedia data includes steps of receiving data, de-interleaving received data into audio, video, and graphic data, decompressing the data, and outputting the data to output device.

Abstract: A microcomputer that is easy to use and connected direct to such memories as dynamic and static RAM's and to other peripheral circuits. The microcomputer has strobe signal output terminals CASH*, CASL* and RAS* for direct connection to a dynamic RAM, and chip select signal output terminals CS0* through CS6* for outputting a chip select signal in parallel with the output from the strobe signal output terminals. The microcomputer further includes address output terminals for outputting a non-multiplexed or multiplexed address signal as needed, and data I/O terminals for selectively outputting the address signal to comply with a multiple-bus interface scheme.

Abstract: A microcomputer comprises a processor, a memory and a buffer including a selector for changing a bus width, wherein a processor bus has a smaller width than that of a memory bus. The microcomputer further comprises a bus interface unit which has a selector for changing the bus width, and is used for inputting/outputting signals from/to the outside, and an external bus for connecting the bus interface unit and the outside, wherein the bus interface unit is connected to the memory via the memory bus, and the external bus has a smaller width than that of the memory bus. Still further the memory includes a plurality of memory regions, and the processor is disposed in a space of the memory regions.

Abstract: An input/output (I/O) data compression system operates two data compression modules in tandem. A "master" module has an uncompressed data I/O, a data compressor/decompressor, a data flow manager, and a compressed data I/O. An identical "dual" data compression module is also provided. Either module is capable of operating singly to provide compression/decompression between the data I/Os. A "tandem" control causes the master data flow manager to control the compressed data I/O, and causes the dual data flow manager to relinquish control. A dual port "active/slave" control responds to receipt of an input at one of the uncompressed data I/O's, idling the uncompressed data I/O of the module (slave) not receiving the input, and causing the module (active) receiving the input to conduct the input and output of uncompressed data.

Abstract: A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.

Abstract: A multi-function peripheral device, connected to an information processing device, has a plurality of functional units for exerting mutually different functions by exchanging data with the information processing device. The multi-function peripheral device includes a specific command judgment unit for judging whether data from the information processing device contains a specific command corresponding to any one of the plurality of the functional units and a data supplier for acting when the specific command detector determines that the specific command exists. The data supplier thereupon supplies the data from the information processing device, including the specific command, to the one of the functional units to which the specific command corresponds.

Abstract: A method and apparatus for transferring data between bus agents in a computer system including a bus operating at a bus clock rate. The method includes the step of receiving a transaction request from a requesting agent including an indication of a plurality of data widths the requesting agent processes. In response to the transaction request, a data transmission is configured in accordance with a data width that both the requesting agent and a responding agent process. The data transmission is performed asynchronously with respect to the bus clock if the data width is one of a first plurality of data widths, otherwise, the data transmission is performed synchronously with respect to the bus clock.