Dynamic Random Access Memory Patents (Class 711/105)
  • Patent number: 10380024
    Abstract: The present disclosure provides a dynamic random access memory (DRAM), and a method of operating the same. The DRAM includes a memory row and a buffer. The memory row is configured to store a data, wherein the memory row does not provide the data to the buffer in response to a request to read the data. The buffer is configured to store the data as a temporarily-stored data, wherein the buffer provides the temporarily-stored data in response to the request.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: August 13, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10372339
    Abstract: The present disclosure relates to an extensible memory hub. An apparatus may include a first extensible non-volatile memory (NVM) hub (EN hub). The first EN hub includes an upstream interface port configured to couple the first EN hub to an NVM controller or to a second EN hub; a downstream interface port configured to couple the first EN hub to a third EN hub or to a NVM device; at least one NVM device port, each NVM device port configured to couple the first EN hub to a respective NVM device via a NVM channel; and an EN hub controller. The EN hub controller includes command logic configured to initialize the first EN hub in response to an initialize chain command from the NVM controller, the initializing including enumerating each NVM device coupled to the first EN hub and each of one or more associated NVM dies.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Randall K. Webb, Jawad B. Khan, Richard L. Coulson, Knut S. Grimsrud, Brian M. Yablon
  • Patent number: 10365857
    Abstract: A memory system capable of being connected to a host, includes a non-volatile memory that includes a plurality of non-volatile memory dies, and a controller that is electrically connected to the non-volatile memory. The controller is configured to manage the plurality of non-volatile memory dies as a plurality of die sets, each die set including two or more of the non-volatile memory dies to which priorities are assigned respectively, select one die set from the plurality of die sets based on an identifier received from the host, and select, based on the assigned priorities, a non-volatile memory die from the selected die set as a writing destination die of write data received from the host.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: July 30, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Masahiro Ishiyama
  • Patent number: 10360970
    Abstract: An apparatus includes a plurality of termination points and a clock mesh network. The termination points may be configured to send/receive timing signals. Each of the termination points may comprise an inductor. The clock mesh network may be configured to provide a path to transmit the timing signals from a clock source to a plurality of components and implement a condition using the inductors. The inductors for each of the termination points may be implemented to meet the condition. Values for the inductors may be determined based on characteristics of the clock mesh network. The condition may prevent power loss.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: July 23, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: David Chang
  • Patent number: 10353455
    Abstract: A three-dimensional stacked (3DS) memory module includes multiple memory chips physically integrated with a data I/O chip. The data I/O chip includes multiple data interfaces and multiple respectively corresponding data buffers. A memory controller routes data traffic through all available data interfaces for maximum bandwidth. In some circumstances, the memory controller directs the data I/O chip to de-activate one or more of the data interfaces (for example, to reduce power consumption). All subsequent data traffic to and from the memory module is routed through the remaining active interfaces. All physical addresses in the 3DS memory module are addressable through the remaining active interfaces. In some circumstances, the memory controller directs the data I/O chip to re-activate some or all of the de-activated data interfaces. Once re-activated, subsequent data traffic to and from the memory module can again be routed through all active interfaces.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kevin M. Mcilvain, Saravanan Sethuraman, Warren E. Maule, Kyu-hyoun Kim
  • Patent number: 10340784
    Abstract: The present disclosure relates to power systems. The teachings thereof may be embodied in power electronic systems. For example, a power electronic system for operating a load may comprise: a number of power modules connected to the load, each comprising at least one switching element and a local actuator; a superordinate controller for actuating the power modules; a device bus connected to the superordinate controller via which the control signals for actuating the power modules are transmitted; the superordinate controller transmitting the control signals in respective messages at predefined intervals of time; wherein all power modules scan a first communication edge of a received message and process it as a common time base of the system.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: July 2, 2019
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Marek Galek
  • Patent number: 10331352
    Abstract: A device and method dynamically optimize processing of a storage command within a storage system. The device and method execute a rule based on predetermined criteria and internal operation parameters of the storage system. An extended application program interface within the storage system provides internal operation parameters for use in execution of the rule. Based on execution of the rule, the storage system optimizes processing of the storage command.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: June 25, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Yaron Klein
  • Patent number: 10331355
    Abstract: A control device, including: a first processor; a second processor which has a higher performance than the first processor; and a storage in which data is stored so as to be readable and writable by the second processor, wherein a part of the storage is usable as a common storage area which is readable and writable by the first processor and the second processor, in reading operation, the second processor reads first data from out of the common storage area in the storage and writes the first data to the common storage area, and the first processor reads the first data from the common storage area, and in writing operation, the first processor writes second data to the common storage area, and the second processor stores the second data out of the common storage area in the storage.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 25, 2019
    Assignee: CASIO COMPUTER CO., LTD.
    Inventors: Naoto Toda, Tatsuya Sekitsuka
  • Patent number: 10324648
    Abstract: Systems and methods are disclosed for wear-based access optimization. An apparatus may comprise a circuit configured to perform a data access operation at a target location of a memory, and determine a wear value of the target location. The circuit may compare the wear value to global wear value of other locations of the drive, and adjust data access parameters for the target location based on the comparison.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: June 18, 2019
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, Antoine Khoueir, Ara Patapoutian
  • Patent number: 10311936
    Abstract: A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: June 4, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Uksong Kang, Hoiju Chung
  • Patent number: 10313470
    Abstract: A system includes at least one end-node, at least one edge node, and an edge cloud video headend. The at least one end node generally implements a first stage of a multi-stage hierarchical analytics and caching technique. The at least one edge node generally implements a second stage of the multi-stage hierarchical analytics and caching technique. The edge cloud video headend generally implements a third stage of the multi-stage hierarchical analytics and caching technique.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: June 4, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Mohammad S. Akhter
  • Patent number: 10290361
    Abstract: A semiconductor system may be configured to classify failure groups of data including erroneous bits and may replace a memory area in which the failure groups are stored with a redundancy area. The replacement of the memory area in which the failure groups are stored, with the redundancy area, may be performed according to priorities of the failure groups.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: May 14, 2019
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Sangkwon Lee
  • Patent number: 10275372
    Abstract: In one embodiment, a cached memory device can include: (i) a memory array coupled to a system address bus and an internal data bus; (ii) a plurality of data buffers coupled to a system data bus, and to the memory array via the internal data bus; (iii) a plurality of valid bits, where each valid bit corresponds to one of the data buffers; (iv) a plurality of buffer address registers coupled to the system address bus, where each buffer address register corresponds to one of the data buffers; and (v) a plurality of compare circuits coupled to the system address bus, where each compare circuit corresponds to one of the data buffers.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: April 30, 2019
    Assignee: Adesto Technologies Corporation
    Inventors: Gideon Intrater, Bard Pedersen, Paul Hill
  • Patent number: 10268382
    Abstract: A processing device includes a first memory interface for accessing a first memory device of a main memory. Each first memory interface is compatible with Low-Power Double-Data-Rate (LPDDR) signaling. The processing device further includes a second memory interface, which has different signaling characteristics from the first memory interface, for accessing a second memory device of the main memory. The second memory device has an access latency higher than the first memory device and lower than a secondary storage device. The first memory device and the second memory device may be used as a dual memory or a two-tiered memory.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: April 23, 2019
    Assignee: MediaTek Inc.
    Inventors: Chuen-Shen Bernard Shung, Jonathan Fuchuen Lee, Zhaoqian Chen, Tom Hsiou-Cheng Kao
  • Patent number: 10262718
    Abstract: In one embodiment, a memory device includes a clock receiver to receive a clock signal and a plurality of mode registers to store parameter information associated with a plurality of operating clock frequencies of the clock signal. The plurality of clock frequencies include a first clock frequency and a second clock frequency. The memory device also includes a command interface to receive commands synchronously with respect to the clock signal. The command interface receives a command that instructs the DRAM device to change operation from the first clock frequency to the second clock frequency.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 16, 2019
    Assignee: Rambus Inc.
    Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
  • Patent number: 10235312
    Abstract: A memory system includes a storage device and a host device. The storage device includes a memory device and a device controller. The device controller is configured to store device information. The device information includes a level of a power supply voltage required for the memory device. The host device includes a host controller and a power management integrated circuit (PMIC). The host device is configured to send a query command to receive the device information from the device controller during a power setting period. The PMIC is configured to supply a first level of power supply voltage to the memory device during the power setting period and, after the power setting period, selectively supply one of the first level of power supply voltage and a second level of power supply voltage to the memory device. The first level of power supply voltage is lower than the second level of power supply voltage.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: March 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Chang Cho, Jae-Phil Kong
  • Patent number: 10216659
    Abstract: An example system includes a memory controller; a memory bus coupled to the memory controller; and a dual inline memory module (DIMM) coupled to the memory controller through the memory bus. The DIMM includes a dynamic random access memory (DRAM) portion; a storage portion; and a gate array portion coupled to the memory bus to detect memory access signals and to store information related to the memory access signals on the storage portion.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: February 26, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Jim W Brainard, Hubert E Brinkmann, Jr., Kevin T Lim, Mitchel E Wright, Raghavan V Venugopal, Reza M Bacchus
  • Patent number: 10216967
    Abstract: A USB-style data-transfer device employs volatile memory that is connected to an onboard power-storage device for data storage. Through this design, any data stored on the memory can be physically cleared by interrupting the supply of electrical power from the onboard power-storage device to the memory. Enhanced security relative to conventional USB flash devices is provided by the volatile memory-based USB-style data-transfer device as the memory can be physically cleared without being plugged into a computer system either automatically when the onboard power storage device runs out of electrical power to supply to the volatile memory, or by user initiation through either a programmed instruction to interrupt the supply of electric power after a set time period or the operation of a manual switch which interrupts the supply of electric power.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: February 26, 2019
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Jeffrey M. Lloyd, Michael Tall, Alex G. Phipps
  • Patent number: 10210948
    Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters and perform a test on at least one memory core. The method includes setting a sweep range including a sweep start point of a first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-ho Ok, Pyung-moon Zhang, Sang-hoon Shin, Ki-hyun Park, Yong-sik Park
  • Patent number: 10191689
    Abstract: Systems for page management using local page information are disclosed. The system may include a processor, including a memory controller, and a memory, including a row buffer. The memory controller may include circuitry to determine that a page stored in the row buffer has been idle for a time exceeding a predetermined threshold determine whether the page is exempt from idle page closures, and, based on a determination that the page is exempt, refrain from closing the page. Associated methods are also disclosed.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney
  • Patent number: 10185667
    Abstract: There is described a storage controller, the storage controller having an array of entries, each entry associated with a partition of one or more partitions, wherein the controller comprises logic configured to identify a partition identifier of an entry and apply a policy to the entry based on or in response to the partition identifier.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: January 22, 2019
    Assignee: Arm Limited
    Inventor: Andrew David Tune
  • Patent number: 10185510
    Abstract: A bank interleaving controller may include a power calculator and a write driver. The power calculator may calculate a total power consumption by adding a power consumption of one or more memory banks that are performing write operations and an amount of power that is expected to be additionally consumed to write input data. The write driver may write the input data to a memory cell corresponding to an input address when the total power consumption is equal to or less than a reference power consumption.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: January 22, 2019
    Assignee: SK hynix Inc.
    Inventors: Seon Kwang Jeon, Bo Ra Choi
  • Patent number: 10180795
    Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: January 15, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihisa Kojima, Tatsuhiro Suzumura, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito
  • Patent number: 10176124
    Abstract: A technology is described for determining an idle page close timeout for a row buffer. An example memory controller may comprise a scoreboard buffer and a predictive timeout engine. The scoreboard buffer may be configured to store a number of page hits and a number of page misses for a plurality of candidate timeout values for an idle page close timeout. The predictive timeout engine may be configured to increment the page hits and the page misses in the scoreboard buffer according to estimated page hit results and page miss results for the candidate timeout values, and identify a candidate timeout value from the scoreboard buffer estimated to maximize the number of page hits to the number of page misses.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney
  • Patent number: 10162750
    Abstract: System address reconstruction logic in accordance with one embodiment of the present description, reconstructs a system address from a channel address translated from the system address. The system address reconstruction logic includes logic configured to reconstruct one or more systems address fields as a function of the channel address, the number of memory controller target ways of the memory being equal to three, the number of bits of the granularity of interleaving of data among the memory controller target ways, the number of channels per memory controller target way, and the number of bits of the granularity of interleaving of data among the channels of a memory controller target way. Other aspects are described herein.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: December 25, 2018
    Assignee: INTEL CORPORATION
    Inventor: Massimo Sutera
  • Patent number: 10163485
    Abstract: A memory module includes a memory interface circuit and a training signal generator. The memory interface circuit includes a plurality of terminals for communicating with a memory controller, and the terminals comprise at least a plurality of data terminals. The training signal generator is coupled to the memory interface circuit, and is arranged for generating a training signal to the memory controller through only a portion of the data terminals or a specific terminal instead of the data terminals when the memory module receives a training request from the memory controller.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: December 25, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shang-Pin Chen, Bo-Wei Hsieh
  • Patent number: 10156994
    Abstract: Techniques for reducing Solid State Device Input/Output latency are disclosed. In some embodiments, the techniques may be realized as a method for reducing Solid State Device Input/Output latency comprising receiving a write request at a Solid State Device, monitoring a plurality flash memory channels of the Solid State Device to identify Input/Output requests, evaluating, using load balancing circuitry, identified Input/Output requests to determine a load of one or more of the plurality of flash memory channels, and assigning a destination flash memory channel out of the plurality of flash memory channels to the write request based on the determined load.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: December 18, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Vetrivel Ayyavu
  • Patent number: 10157123
    Abstract: An apparatus includes a scheduler module operatively coupled to each memory block from a set of memory blocks via a shared address bus. The scheduler module is configured to receive a group of memory commands from a set of memory controllers. Each memory controller from the set of memory controllers is uniquely associated with a different memory block from the set of memory blocks. The scheduler module is configured to classify each memory command from the group of memory commands into a category based at least in part on memory commands previously sent to the set of memory blocks via the shared address bus. The scheduler module is configured to select an order in which to send each memory command from the group of memory commands to the set of memory blocks via the shared address bus based at least in part on the category of each memory command.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 18, 2018
    Assignee: Juniper Networks, Inc.
    Inventors: Srinivas Vaduvatha, Deepak Goel, Shahriar Ilislamloo
  • Patent number: 10153028
    Abstract: A semiconductor device may be provided. The semiconductor device may include an error scrub control circuit and or an active period signal generation circuit. The error scrub control circuit may be configured to generate an error scrub pre-charge signal and an error scrub bank signal for performing an error scrub operation of memory cells included in banks, based on a bank active signal and a row address signal which are generated based on a refresh signal. The active period signal generation circuit may be configured to generate an active period signal from the bank active signal and the error scrub pre-charge signal based on the error scrub bank signal.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: December 11, 2018
    Assignee: SK hynix Inc.
    Inventor: Chang Hyun Kim
  • Patent number: 10109340
    Abstract: Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, John B. Halbert, Nadav Bonen, Tomer Levy
  • Patent number: 10101934
    Abstract: Described herein are embodiments of a process that can be used to balance the allocation of primary memory between different types of information. In some embodiments, the memory allocation is balanced dynamically based on observed I/O patterns. Related system embodiments are also described.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: October 16, 2018
    Assignee: EMC Corporation
    Inventors: Tal Ben-Moshe, Eli Dorfman, Kirill Shoikhet, David Krakov, Roman Vainbrand, Noa Cohen
  • Patent number: 10089040
    Abstract: A memory apparatus may include a plurality of ranks commonly coupled to an input/output (I/O) terminal. Non-target ranks other than a target rank among the plurality of ranks may be configured to perform an on die termination operation based on a read operation of the target rank.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: October 2, 2018
    Assignee: SK hynix Inc.
    Inventors: Seung Wook Oh, Hyun Seung Kim, Jin Youp Cha
  • Patent number: 10061532
    Abstract: A system includes multiple memories. Access of at least one of the multiple memories uses an interface subsystem that includes a memory controller and a distinct media controller, the memory controller to issue a transaction-level access request. The media controller is associated with at least one memory and produces, in response to the transaction-level access request, at least one command according to a specification of the at least one memory. Data is migrated from a first of the multiple memories to a second of the multiple memories, without the data traversing through a cache memory in the processor during the migrating.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: August 28, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Michael R. Krause
  • Patent number: 10055346
    Abstract: Apparatus, systems, and methods to implement polarity based data transfer function for volatile memory power reduction are described. The transfer function take into account certain data values, all zeroes in particular, that are common and transforms them to predetermined values that consume less power and are less common. Similarly, these predetermined values are transformed to the common values.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: August 21, 2018
    Assignee: Intel Corporation
    Inventor: Nadav Bonen
  • Patent number: 10049006
    Abstract: A method for updating a DRAM memory array is disclosed. The method comprises: a) transitioning the DRAM memory array from an idle state to a refresh state in accordance with a command from a memory controller; b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry by activating a row of data into an associated sense amplifier buffer; and c) during the refresh, performing an ERR Correction Code (ECC) scrub operation of selected bits in the activated row of the DRAM memory array.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: August 14, 2018
    Assignee: Nvidia Corporation
    Inventors: David Reed, Alok Gupta
  • Patent number: 10002659
    Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: June 19, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jeffery W. Janzen, Brent Keeth, Jeffrey P. Wright, James S. Cullum
  • Patent number: 10003323
    Abstract: An impedance calibration circuit is disclosed, which relates to a technology for improving precision of pad resistance. The impedance calibration circuit includes: a first On Die Termination (ODT) circuit selected by a first selection signal, configured to tune its own resistance using a first code signal, and output a first resistance value to an output terminal; and a second ODT circuit selected by a second selection signal, configured to tune its own resistance using a second code signal, and output a second resistance value to the output terminal.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: June 19, 2018
    Assignee: SK hynix Inc.
    Inventors: Seung Geun Baek, Jae Il Kim
  • Patent number: 9984013
    Abstract: A method, a controller, and a system for service flow control in an object-based storage system are disclosed. The method is: receiving, by a controller, a first object IO request; acquiring a processing quantity threshold and a to-be-processed quantity; if the to-be-processed quantity is less than the processing quantity threshold, sending the first object IO request to a storage device client, and updating the to-be-processed quantity; receiving a first response message replied by the storage device client for the first object IO request, where the first response message carries a processing result of the first object IO request; and adjusting the processing quantity threshold according to a received processing result of an object IO request when a preset condition is met. The storage device is not overloaded with object IO requests and can use all resources to effectively, thereby improving performance and a success rate of the object-based storage system.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: May 29, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Yanqun Tong
  • Patent number: 9965384
    Abstract: A method for managing a multi-channel memory device includes at least following steps: when the multi-channel memory device is controlled to operate in an M-channel mode, reserving a partial memory space across N memory channels of the multi-channel memory device, where the reserved partial memory space is not used under the M-channel mode, M and N are positive integers, and M is smaller than N; and when the multi-channel memory device is controlled to switch from the M-channel mode to an N-channel mode, accessing data in the reserved partial memory space across the N memory channels used under the N-channel mode. The method for managing a multi-channel memory device can improve switch response time.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: May 8, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chuan Liu, Wen-Hsuen Kuo
  • Patent number: 9952644
    Abstract: Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Mahesh Wagh, Lily Pao Looi
  • Patent number: 9952643
    Abstract: Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Mahesh Wagh, Lily Pao Looi
  • Patent number: 9946470
    Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: April 17, 2018
    Assignee: Rambus Inc.
    Inventors: Aws Shallal, Michael Miller, Stephen Horn
  • Patent number: 9946652
    Abstract: A memory management system for managing a memory and includes a multi-stage memory management unit including control circuitry and cache memory. The cache memory may have a respective translation look-aside buffer for each stage of the multi-stage memory management unit. The control circuitry may be configured to generate a blank data request including a virtual address and information that specifies that data is not to be read from the memory, perform address translations based on the generated blank data request in multiple stages until a physical address is obtained, and discard the blank data request.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: April 17, 2018
    Assignee: STMicroelectronics International N.V.
    Inventors: Gilles Ries, Ennio Salemi, Sana Ben Alaya
  • Patent number: 9940985
    Abstract: The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 10, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Sanjay Tiwari
  • Patent number: 9916105
    Abstract: Providing for a memory apparatus configured for improved data management for a two-terminal memory array is described herein. By way of example, disclosed embodiments relate to page management and transfer of data between page-sized subsets of a page buffer, and respective pages within one or more memory banks of the two-terminal memory array. The memory apparatus can emulate a larger page size than a physical page buffer utilized by the memory apparatus, to provide compatibility with different page size defaults while lowering current consumption by the page buffer. This can facilitate large or small array operations, taking advantage of higher efficiencies of two-terminal memory devices. In addition, page buffer data management can facilitate interleaved data transfers among multiple banks of memory, facilitating large memory capacities for a disclosed memory apparatus.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: March 13, 2018
    Assignee: CROSSBAR, INC.
    Inventor: Mehdi Asnaashari
  • Patent number: 9916247
    Abstract: A method is provided for cache coherence being based on a hybrid approach relying on hardware-and software-implemented functionalities. In case a processor core is requested to perform a write operation on a memory line missed in the local cache of said core, a hardware-implemented coherence directory ensures that said processor core becomes assigned exclusive write permissions to indicate that the memory line in said local cache is up-to-date after said write. In case the processor core is requested to perform a read operation on a memory line missed in the local cache of said processor core, the coherence directory updates the coherence directory to indicate that none of the processor cores of the system has exclusive write permission on the memory line and relies on software executed on said processor core to ensure that the cached memory line is up-to-date before performing the read operation.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventor: Burkhard Steinmacher-Burow
  • Patent number: 9916176
    Abstract: A methods and device for accessing virtual machine (VM) data are described. A computing device for accessing virtual machine comprises an access request process module, a data transfer proxy module and a virtual disk. The access request process module receives a data access request sent by a VM and adds the data access request to a request array. The data transfer proxy module obtains the data access request from the request array, maps the obtained data access request to a corresponding virtual storage unit, and maps the virtual storage unit to a corresponding physical storage unit of a distributed storage system. A corresponding data access operation may be performed based on a type of the data access request.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: March 13, 2018
    Assignee: Alibaba Group Holding Limited
    Inventor: Xiao Fei Quan
  • Patent number: 9898228
    Abstract: A write method and a write apparatus for a storage device, where the write method includes: acquiring n numerical values that need to be written; determining n bits corresponding to the n numerical values, and information about a stuck-at fault included in the n bits; grouping the n bits into B groups of bits, so that the B groups of bits meet a grouping condition; and correspondingly writing the n numerical values according to information about a stuck-at fault included in each group of bits in the B groups of bits and a numerical value that needs to be written and that is corresponding to the information about the stuck-at fault included in each group of bits in the B groups of bits.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: February 20, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jiwu Shu, Jie Fan, Guanyu Zhu
  • Patent number: 9874898
    Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: January 23, 2018
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Patent number: 9865328
    Abstract: An apparatus includes a detector circuit and a data buffer. The detector circuit may be configured to (i) identify a start of a command sequence associated with a directed access to a memory system and (ii) generate a control signal indicating a non-consecutive clock associated with the start of said command sequence. The data buffer circuit may be configured to initialize a condition of a receiver circuit in response to the control signal prior to reception of a first data bit associated with the command sequence.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: January 9, 2018
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Craig DeSimone, Praveen Singh