Solid-state Random Access Memory (ram) Patents (Class 711/104)
  • Patent number: 10353636
    Abstract: A write filter can be configured to employ a dynamically expandable overlay. The size of the overlay could initially be small and could then grow and shrink during the current session based on demand. The overlay can span both RAM and disk to thereby allow the size of the overlay to be relatively large. When sufficient RAM is available, the overlay can be allowed to grow in RAM. In contrast, if RAM is low, the overlay can grow on disk. Also, artifacts in the overlay can be moved from the RAM portion to the disk portion to reduce the amount of RAM consumed by the overlay. Because the overlay is dynamically expandable, it will typically not become full and will therefore not force a reboot.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: July 16, 2019
    Assignee: WYSE TECHNOLOGY L.L.C.
    Inventors: Puneet Kaushik, Salil S Joshi, Sumit Popli
  • Patent number: 10339992
    Abstract: A semiconductor system may include a controller configured to provide a command clock and a control signal to a semiconductor memory device, and the semiconductor memory device configured to transmit/receive external data and a plurality of data clocks to/from the controller, wherein the plurality of data clocks comprise a first read data strobe signal and a second read data strobe signal, and the semiconductor memory device transmits both of the first read data strobe signal and the second read data strobe signal to the controller or transmits one of the first read data strobe signal and the second read data strobe signal to the controller, based on an operation select signal.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: July 2, 2019
    Assignee: SK hynix Inc.
    Inventors: Keun Soo Song, Woo Yeol Shin
  • Patent number: 10303363
    Abstract: A system and method is provided for data storage using log-structured merge (LSM) trees. An example method includes storing data blocks for a number of files backup data files in a data archive, storing data values and corresponding segment identifiers for each data block in a first LSM tree, and storing the segment identifiers and associated physical addresses for each data block in a second LSM tree. The method further includes determining that one or more data blocks is no longer referenced by the backup data file and storing, in a third LSM tree, the physical address of the unused space in the data archive. Finally, the method includes copying data blocks from the end of the data archive to unused memory space at the physical address in the data archive and then deleting these data block at the end position of the archive to truncate the archive.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: May 28, 2019
    Assignee: Acronis International GmbH
    Inventors: Vitaly Pogosyan, Kirill Korotaev, Mark Shmulevich, Stanislav Protasov, Serguei Beloussov
  • Patent number: 10275159
    Abstract: An embedded device, a RAM disk of an embedded device and a method of accessing a RAM disk of an embedded device are provided. The embedded device includes: a processing unit, configured to execute an operating system; a first memory, for the processing unit to access required system data when the processing unit executes the operating system; a function module, configured to perform a predetermined function; a second memory, for the function module to access required functional data through direct memory access when the function module performs the predetermined function; and a RAM disk driving module, configured to incorporate a first part of the first memory with the second memory to one RAM disk, and to control access of the RAM disk.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: April 30, 2019
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Chien-Hsing Huang, Hsin-Hsiung Tseng
  • Patent number: 10255145
    Abstract: In one embodiment, two or more programmable multimedia controllers are provided a multimedia system that includes a plurality of audio/video (A/V) devices that source or output digital media streams. Each of the programmable multimedia controllers has at least a processing subsystem and a switch capable of switching the digital media streams. Arbitration is conducted among the programmable multimedia controllers to select one of the programmable multimedia controllers as winning the arbitration. Master status is assigned to the one of the programmable multimedia controllers that won the arbitration. Subordinate status is assigned to at least one other programmable multimedia controller that did not win the arbitration. It is periodically verified whether the programmable multimedia controller assigned master status is operating.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: April 9, 2019
    Assignee: Savant Systems, LLC
    Inventors: Siegmar K. Eschholz, Michael C. Silva
  • Patent number: 10223261
    Abstract: A lightweight architecture for an aliased memory operation includes loading data by performing an aliased memory operation, and storing data by performing an aliased memory operation, the loading of data by performed by an aliased memory operation that includes: requesting an aliased address through an HAT without a specific operation for converting an address by means of a CPU processor, converting an address input through the HAT into an aliased address in response to the request for an aliased address, stopping the aliased memory operation through the HAT and calling up a miss handler when the conversion of an address into an aliased address in response to the request for an aliased address fails, and loading data by accessing an SAT using the aliased address when conversion of an address into an aliased address succeeds.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: March 5, 2019
    Assignee: UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
    Inventors: Woongki Baek, Seung Hoe Kim
  • Patent number: 10210080
    Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: February 19, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern
  • Patent number: 10210097
    Abstract: A request is received to load a particular overlay segment from a secondary storage memory to a main memory for execution by a processor, wherein the particular overlay segment is absent from the main memory. A determination is made whether the main memory can receive the particular overlay segment. In response to determining that the main memory cannot receive the particular overlay segment, eviction strategy information about one or more existing overlay segments that are present in the main memory is obtained. Based on the eviction strategy information, at least one of the one or more existing overlay segments is selected for eviction from the main memory. The particular overlay segment is retrieved from the secondary storage memory. The at least one of the one or more existing overlay segments in the main memory that is selected for eviction is replaced with the particular overlay segment.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: February 19, 2019
    Assignee: Macronix International Co., Ltd.
    Inventors: Tzu-Yi Yang, Ting-Yu Liu, Yi-Chun Liu
  • Patent number: 10204669
    Abstract: A semiconductor system may include a controller configured to provide a first external clock and a control signal to a semiconductor device, and the semiconductor device configured to transmit/receive external data and a plurality of second external clocks to/from the controller, wherein the plurality of second external clocks comprise a third primary external clock and a third secondary external clock, and the semiconductor device transmits both of the third primary external clock and the third secondary external clock to the controller or transmits one of the third primary external clock and the third secondary external clock to the controller, based on an operation select signal.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: February 12, 2019
    Assignee: SK hynix Inc.
    Inventors: Keun Soo Song, Woo Yeol Shin
  • Patent number: 10184272
    Abstract: An installation-free rechargeable access control system is disclosed which automates the action of locking and unlocking a single-cylinder deadbolt on a door. In various embodiments, the present teachings provide a portable electronic module that can enhance the usage of deadbolts in place, instead of replacing the deadbolt mechanism itself. In various embodiments, the access control system can authenticate users and rotate a deadbolt using one or more peripheral sensing sources and wireless protocols.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: January 22, 2019
    Inventor: Dominick S. Lee
  • Patent number: 10162758
    Abstract: A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of cache entries in a cache, wherein the processor core is to: detect an amount of the memory installed in a computing system and, responsive to detecting less than a maximum allowable amount of the memory for the computing system, direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventor: Ruchira Sasanka
  • Patent number: 10141935
    Abstract: On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: November 27, 2018
    Assignee: Intel Corporation
    Inventors: Kuljit S Bains, Alexey Kostinsky, Nadav Bonen
  • Patent number: 10115442
    Abstract: A computing device may comprise a processor, a volatile memory and a non-volatile storage device. An operating system or firmware of the device may cause one or more pages of the volatile memory to be treated, by applications executing on the computing device, as non-volatile memory pages. A number of pages that may be treated as non-volatile may be determined based on demand for non-volatile storage by at least one application executing on the computing device.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 30, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bryan D. Kelly, Mallik Bulusu, Ravi Mysore Shantamurthy, Tom L. Nguyen
  • Patent number: 10108658
    Abstract: A data store manager of a multi-data-store journal-based database performs a sequential analysis of committed transaction entries of a journal. A particular entry includes a directive to determine a value of an attribute of a data object based on a result obtained from a value generator, and does not specify the value of the attribute. The data store manager determines the value using a local version of the value generator, and stores the value in a materialized version of the data object. In response to a programmatic read request, the data store manager provides the materialized version of the data object.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: October 23, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Timothy Daniel Cole, Michael Benjamin Deardeuff, Artem Danilov, John Michael Morkel, Tate Andrew Certain, Christopher Richard Jacques De Kadt, Aaron Gifford Freshwater, Allan Henry Vermeulen, Andrew Wayne Ross
  • Patent number: 10043561
    Abstract: A semiconductor system may include a controller and a semiconductor memory device. The controller may provide an external command, an external address and a first external clock. The controller may be configured to transmit a second external clock and receive a third external clock for receiving/transmitting external data. The semiconductor memory device may be configured to synchronize and receive the external address and the external command with the first external clock. The semiconductor memory device may be configured to synchronize and receive the external data with the second external clock. The semiconductor memory device may be configured to transmit the external data and the third external clock to the controller.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: August 7, 2018
    Assignee: SK hynix Inc.
    Inventors: Keun Soo Song, Woo Yeol Shin
  • Patent number: 10013170
    Abstract: Determining whether to compress data of a virtual storage unit based at least in part on: an I/O activity value of a virtual storage unit; a compressibility value of the virtual storage unit; and/or a capacity utilization of the storage system or a component thereof. For example, decision logic may be configured based on one or more of such parameters such that virtual storage units with relatively high I/O activities are rarely or never compressed, e.g., to avoid the disproportionately high increases in CPU and bandwidth resource consumption and I/O latency this could create. Decision logic may be configured such that, in general, the likelihood that a virtual storage unit will be compressed increases as: the I/O activity of the virtual storage unit decreases; the system capacity utilization increases; and/or as the compressibility value of the virtual storage unit increases.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 3, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Adnan Sahin, Owen Martin, Jeremy J. O'Hare
  • Patent number: 9984746
    Abstract: According to an embodiment, a memory device includes a nonvolatile memory, a controller, and power storage. The controller is configured to receive, from a host device, a write request for writing data into the nonvolatile memory, and then, write the data based on the write request. The power storage is configured to store power supplied from a power supply. The controller writes, when abnormality in power supplied from the power supply to the memory device is detected, the data based on the write request that has already been received, using the power supplied from the power storage.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: May 29, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsunori Kanai, Tetsuro Kimura, Masaya Tarui, Yusuke Shirota, Shiyo Yoshimura
  • Patent number: 9959086
    Abstract: There are provided an electronic device and a control method thereof. First contents related to an image and second contents generated by converting the recorded audio into text are displayed on a touchscreen, instead of a playback screen of the image when the electronic device plays the image and enters a mode for recording audio. Thus, a user can use a image, when viewing and listening to it, in various manners.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 1, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Sungchae Na, Jungeun Shin
  • Patent number: 9946513
    Abstract: A spin unit provided with a memory cell that stores a value of one spin of an Ising model, a memory cell that stores an interaction coefficient from an adjacent spin which interacts with the corresponding spin, a memory cell that stores an external magnetic field coefficient of the one spin and circuits that determine the next state of the one spin on the basis of a product of a value of each adjacent spin and the corresponding interaction coefficient and the external magnetic field coefficient is configured, the semiconductor device is provided with a spin array where the plural spin units are arranged and connected on a two-dimensional plane on a semiconductor substrate, a random number generator and a bit regulator, the bit regulator operates output of the random number generator and supplies a random bit to all spin units in the spin array via one wire.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: April 17, 2018
    Assignee: HITACHI, LTD.
    Inventors: Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura
  • Patent number: 9947386
    Abstract: A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.
    Type: Grant
    Filed: September 21, 2014
    Date of Patent: April 17, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Manish Arora, Indrani Paul, Yasuko Eckert, Nuwan Jayasena, Dong Ping Zhang
  • Patent number: 9916881
    Abstract: A semiconductor system may include a controller and a semiconductor memory device. The controller may provide an external command, an external address and a first external clock. The controller may be configured to transmit a second external clock and receive a third external clock for receiving/transmitting external data. The semiconductor memory device may be configured to synchronize and receive the external address and the external command with the first external clock. The semiconductor memory device may be configured to synchronize and receive the external data with the second external clock. The semiconductor memory device may be configured to transmit the external data and the third external clock to the controller.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: March 13, 2018
    Assignee: SK hynix Inc.
    Inventors: Keun Soo Song, Woo Yeol Shin
  • Patent number: 9852064
    Abstract: A system on chip includes a memory information read unit and a memory feature setting unit. The memory information read unit is configured to read standard integrated information using a first instruction or read standard information using a second instruction from at least one of the memory and an application image. The memory feature setting unit is configured to set a feature of the memory using the standard integrated information or the standard information. The memory feature setting unit selects all or some of a plurality of bus access modes defined in the standard integrated information or in the standard information and sets a bus access mode of the memory as one or more of the bus access modes.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: December 26, 2017
    Assignee: FCI, Inc.
    Inventor: Hyungil Goh
  • Patent number: 9836359
    Abstract: There is provided a storage having plural clusters. Each of the clusters includes a cache memory and a save memory. The processor of each of the clusters controls to write plural data pieces into the cache memory, controls to store all the data stored in the cache memory into the save memory upon an occurrence of a failure, and controls to restore some of the data stored in the save memory into the cache memory upon recovery from the failure.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: December 5, 2017
    Assignee: HITACHI, LTD.
    Inventor: Fumiaki Hosaka
  • Patent number: 9824010
    Abstract: According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: November 21, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Tony M. Brewer, J. Michael Andrewartha, William D. O'Leary, Michael K. Dugan
  • Patent number: 9760300
    Abstract: Memory objects may be allocated and re-allocated within a computer system to consolidate infrequently used memory objects to memory regions that may be operated at lower power. During initial allocation of memory objects, the objects may be placed into high power regions. During subsequent periodic analysis, memory objects in high power regions that are infrequently used may be relocated to lower power regions while memory objects in low power regions that are frequently used may be moved to the high power regions. Various heuristics or logic may be used to handle unmovable objects, shared objects, and other types of objects.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: September 12, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bruce L. Worthington, Vishal Sharda, Qi Zhang, Swaroop Kavalanekar
  • Patent number: 9747040
    Abstract: Example embodiments of the present invention relate to methods, systems, and computer program products for reducing I/O latency in a storage system. The method include polling a storage system for values related to caching of I/Os in global memory for subsequent destaging to disk. The host then may determine respective write delay values for I/Os to be sent from a host communicatively coupled with the storage system according to the values related to caching of I/Os. The write delay values then may be applied to the I/Os at the host to delay sending of the I/Os by respective delay times from the host to the storage system.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: August 29, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Ajith Balakrishnan, Bradley A. Bowlin, Rong Yu, Arieh Don, Peng Wu
  • Patent number: 9720970
    Abstract: A system and method for efficient storage and retrieval of fragmented data using a pseudo linear dynamic byte array is provided. In accordance with an embodiment, the system comprises a database driver which provides access by a software application to a database. The database driver uses a dynamic byte array to enable access by the application to data in the database, including determining a size of a required data to be stored in memory, and successively allocating and copying the required data into the dynamic byte array as a succession of blocks. The data stored within the succession of blocks can then be accessed and provided to the application.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: August 1, 2017
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Douglas Surber, Jean De Lavarene, Ashok Shivarudraiah, Edward Shirk, Mark Jungerman
  • Patent number: 9721625
    Abstract: Time-constrained data copying between storage media is disclosed. When an electronic device is engaged in real-time operations, multiple data blocks may need to be copied from one storage medium to another storage medium within certain time constraints. In this regard, a data port is operatively controlled by a plurality of registers of a first register bank. The plurality of registers is copied from the first register bank to a second register bank within a temporal limit and while the data port remains under control of the plurality of registers being copied. By copying the plurality of registers within the temporal limit, it is possible to prevent operational interruption in the data port and reduce bandwidth overhead associated with the register copying operation.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: August 1, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Lior Amarilio, Alexander Khazin
  • Patent number: 9720600
    Abstract: An apparatus is connected to a first storage and a second storage which is accessed at an access speed lower than an access speed of the first storage. The apparatus accesses each of blocks stored in the second storage, and counts, for each of the blocks, the number of accesses made for the each block. The apparatus determines, based on the number of accesses that has been counted for each of the blocks, a transfer target block that is a target which is to be transferred from the second storage to the first storage, and determines a transfer time at which transfer of the transfer target block is to be performed. The apparatus transfers the determined transfer target block to the first storage at the determined transfer time.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: August 1, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Motoyuki Kawaba, Kazuichi Oe, Kazutaka Ogihara
  • Patent number: 9715444
    Abstract: Disclosed is a method of writing data in a storage device including a nonvolatile memory device. The method includes receiving write data with a write request, detecting a number of free blocks, if the detected number of free blocks is less than a threshold value, allocating a log block only in accordance with a sub-block unit, but if the detected number of free blocks is not less than the threshold value, allocating the log block in accordance with one of the sub-block unit and a physical block unit, wherein the sub-block unit is smaller than the physical block unit.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: July 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joonho Lee, Jong-Nam Baek, Dong-Hoon Ham, Sang-Wook Yoo, Intae Hwang
  • Patent number: 9710403
    Abstract: In various embodiments, apparatuses and methods are disclosed to keep a memory clock gated when the data for a current memory address is the same as the data in the immediate previous memory address. For a write function, new data will only be written into the current memory address if it is different from the data in the immediate previous memory address. Similarly, for a read function, the data will only be read out of the current memory address if it is different from the data in the immediate previous memory address. Each row in the memory may have one associated status bit outside the memory. Data may only be written to or read from the current memory address when the status bit is set. Clock gating the memory ports may reduce the overall power consumption of the memory.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: July 18, 2017
    Assignee: INTEL CORPORATION
    Inventor: Sutirtha Deb
  • Patent number: 9697111
    Abstract: A method of managing dynamic memory reallocation includes receiving an input address including a block bit part, a tag part, and an index part and communicating the index part to a tag memory array, receiving a tag group communicated by the tag memory array based on the index part, analyzing the tag group based on the block bit part and the tag part and changing the block bit part and the tag part based on a result of the analysis, and outputting an output address including a changed block bit part, a changed tag part, and the index part.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: July 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Hee Yoo, Sung Hyun Lee, Dong Soo Kang
  • Patent number: 9658956
    Abstract: Disclosed is a method of writing data in a storage device including a nonvolatile memory device. The method includes receiving write data with a write request, detecting a number of free blocks, if the detected number of free blocks is less than a threshold value, allocating a log block only in accordance with a sub-block unit, but if the detected number of free blocks is not less than the threshold value, allocating the log block in accordance with one of the sub-block unit and a physical block unit, wherein the sub-block unit is smaller than the physical block unit.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: May 23, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joonho Lee, Jong-Nam Baek, Dong-Hoon Ham, Sang-Wook Yoo, Intae Hwang
  • Patent number: 9652330
    Abstract: A method for data management and a memory storage device and a memory control circuit unit thereof. The method includes: configuring a NVRAM and a VRAM; storing first data which includes writing data from a host system in the NVRAM; storing second data read from a rewritable non-volatile memory module in the VRAM; when the memory storage device is re-powered on after power failure, reading the first data from the NVRAM, so as to write the writing data into the rewritable non-volatile memory module.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: May 16, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 9639287
    Abstract: In operating a Data Storage Device (DSD) in communication with a host, a reported write command log is maintained that includes entries identifying pending write commands reported as completed to the host but whose data is not yet stored in at least one Non-Volatile Memory (NVM) of the DSD. The reported write command log is maintained to persist over power cycles. A write command is received from the host to store data in the at least one NVM and the data for the write command is buffered in a volatile memory of the DSD for storage in the at least one NVM. The reported write command log is updated to account for the write command as a pending write command reported as completed, and an indication is sent to the host reporting completion of the write command before completing storage of the data in the at least one NVM.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: May 2, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventors: James N. Malina, Albert H. Chen
  • Patent number: 9641459
    Abstract: Various embodiments relate to a method, network node, and non-transitory machine-readable storage medium including the following: receiving a packet; evaluating a flow processing table comprising a plurality of rules to determine whether a rule of the plurality of rules is applicable to the received packet, wherein: a rule of the plurality of rules includes a matching rule that identifies one or more flows to which the rule applies and at least one action that identifies at least one action to be taken when the rule applies; generating a new rule to be added to the flow processing table when the after failing to identify a rule of the plurality of rules as applicable to a received packet, including: evaluating at least one flow rule generation table to identify a first set of packet header fields and a set of processing actions; installing the new rule in the flow processing table.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: May 2, 2017
    Assignee: Alcatel Lucent
    Inventors: Yang Guo, Fang Hao, Tirunellai V. Lakshman, An Wang
  • Patent number: 9606965
    Abstract: A semiconductor device includes a plurality of spin units individually including a memory cell configured to store values of spins in an Ising model, a memory cell configured to store an interaction coefficient from an adjacent spin that exerts an interaction on the spin, a memory cell configured to store an external magnetic field coefficient of the spin, and an interaction circuit configured to determine a subsequent state of the spin. The spin units individually include a random number generator configured to supply the random number to the plurality of the spin units and generate two-valued simulated coefficients of two values or simulated coefficients of three values in performing an interaction to determine a subsequent state of a spin of the spin units from a value of a spin from an adjacent spin unit, an interaction coefficient, and an external magnetic field coefficient.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: March 28, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Chihiro Yoshimura, Masato Hayashi, Masanao Yamaoka
  • Patent number: 9590012
    Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: March 7, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Jong Won Lee, Gianpaolo Spadini, Derchang Kau
  • Patent number: 9563587
    Abstract: A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals from the memory controller and to output module command signals and module control signals. The module command signals are provided to memory devices organized in groups, each group including at least one memory device, while the module control signals are provided to a plurality of buffer circuits to control data paths in the buffer circuits. The plurality of buffer circuits are associated with respective groups of memory devices and are distributed across a surface of the memory module such that each module control signal arrives at the plurality of buffer circuits at different points in time.
    Type: Grant
    Filed: September 7, 2015
    Date of Patent: February 7, 2017
    Assignee: Netlist, Inc.
    Inventors: Hyun Lee, Jayesh R. Bhakta
  • Patent number: 9565251
    Abstract: Data frames, such as Controller Access Network frames, that are to be programmed into a FLASH memory device, are sent from a programming station to a target device via a relatively high-speed bus and stored temporarily at the target device in numbered frame buffers. Each frame carries a payload. Before a frame is sent, an identifier is assigned to it, or an identifier is appended to the frame. The identifier identifies a particular buffer in the target device where the frame is to be stored in the target device until the target device is able to process the frame and write its payload into a FLASH memory device.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: February 7, 2017
    Assignee: Continental Automotive Systems, Inc.
    Inventor: Graeme Davidson Whyte
  • Patent number: 9558247
    Abstract: A storage device may include a main storage part including one or more memories; and a controller configured to control an overall operation of the main storage part. The controller includes a filter manager configured to store data format information and a filtering condition provided from a host; one or more stream filters configured to search and project data stored in the one or more memories in parallel in response to a control of the filter manager to produce searched and projected data; and a merge filter configured to merge the searched and projected data of the one or more stream filters in response to the control of the filter manager.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: January 31, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chanik Park, Jeonguk Kang, Kangho Roh, Yang Seok Ki
  • Patent number: 9542224
    Abstract: The approaches described herein implement execution of a user space operation from a kernel context. A thread, executing on a computing device, initializes a second kernel stack based on a first kernel stack. The computing device executes an operating system having a user space and a kernel space. The thread, executing in kernel space, performs a non-blocking call (e.g., an upcall) to execute an upcall function in user space, such as filtering input/output (I/O) requests. The upcall function may further call other user space functions or system calls. The system calls are performed using the second kernel stack. Upon termination of the upcall function, the thread continues execution on the first kernel stack in kernel space. For example, the thread handles the filtered I/O commands.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: January 10, 2017
    Assignee: VMware, Inc.
    Inventors: Christoph Klee, Mukund Gunti, Adrian Drzewiecki
  • Patent number: 9520162
    Abstract: The various implementations described herein include systems, methods and/or devices used to enable performing supervisory functions for a dual in-line memory module (DIMM), at a controller in the DIMM. The method includes upon power-up, determining a power supply voltage provided to the DIMM. In accordance with a determination that power supply criteria are satisfied, the method includes: (1) performing one or more power-up operations, including initiating a usage counter, (2) monitoring a temperature of the DIMM, (3) monitoring the DIMM for occurrence of one or more of a set of predetermined trigger events, and (4) in response to detecting one of the set of predetermined trigger events, logging information corresponding to the detected predetermined event.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: December 13, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Gregg S. Lucas, Kenneth B. Delpapa, Robert W. Ellis
  • Patent number: 9501424
    Abstract: Provided is a memory mapping method, and particularly provided is a nonvolatile main memory mapping method for managing a nonvolatile main memory. The nonvolatile memory mapping method includes: performing a system call in order to access a file page that is required to operate a process stored in a kernel area of a nonvolatile main memory, wherein both the file page and process are stored in the kernel area of the nonvolatile main memory; and mapping a physical address of the file page to a virtual address of a user area of the nonvolatile main memory.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: November 22, 2016
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SUNGKYUNKWAN UNIVERSITY RESEARCH & BUSINESS F
    Inventors: Oh-seong Kwon, Hwan-soo Han, Jung-sik Choi, Sun-young Lim
  • Patent number: 9495309
    Abstract: A system and method for serial interface topologies is disclosed. A serial interface topology includes a replication device configured to receive control information from a controller interface. The replication device is configured to transmit two or more copies of substantially replicated control information to a device control interface. A data interface is configured to provide differential, point-to-point communication of data with the device controller interface.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: November 15, 2016
    Assignee: Dell Products L.P.
    Inventor: William F. Sauber
  • Patent number: 9489406
    Abstract: A method includes traversing pointers reachable from a root node, identifying an object, determining whether the identified object has a weak property, determining, when the identified object has a weak property, whether the key object referenced by the identified weak property is traversed by the garbage collector, if the key object associated with the identified weak property is traversed by the garbage collector, queuing the value object for later traversal, otherwise, marking the key object as being watched and appending an entry in a table mapping the key objects to a list with value object pointer locations as an entry and determining whether the identified object is visited for the first time by the garbage collector.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: November 8, 2016
    Assignee: Google Inc.
    Inventor: Carl Shapiro
  • Patent number: 9465738
    Abstract: An information processing system that determines whether static data is already loaded into shared memory when a request is made to load static data into shared memory from a process out of a plurality of processes. When the information processing system determines that static data is not loaded into shared memory, after loading the data into shared memory, it notifies the requesting process with information identifying the static data. When the information processing system determines that the static data is already loaded into shared memory, it notifies the requesting process with information identifying the static data.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: October 11, 2016
    Assignee: SQUARE ENIX HOLDINGS CO., LTD.
    Inventor: Tetsuji Iwasaki
  • Patent number: 9449659
    Abstract: The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: September 20, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Tony M. Brewer, J. Michael Andrewartha, William D. O'Leary, Michael K. Dugan
  • Patent number: 9430402
    Abstract: The described implementations relate to computer memory. One implementation provides a technique that can include providing stealth memory to an application. The stealth memory can have an associated physical address on a memory device. The technique can also include identifying a cache line of a cache that is mapped to the physical address associated with the stealth page, and locking one or more other physical addresses on the memory device that also map to the cache line.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: August 30, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Marcus Peinado, Taesoo Kim
  • Patent number: 9405697
    Abstract: A method for managing memory using a virtual memory manager includes receiving a memory allocation request, allocating memory of a physical address space in response to the memory allocation request, mapping an address value of the memory allocated in the physical address space to consecutive primary virtual address space, and mapping the address value of the primary virtual address space to one of a first and second secondary virtual address spaces to process a new memory allocation request in a situation where memory a fragmentation occurs. Other embodiments are also disclosed. The methods and apparatuses of the present disclosure are capable of moving active memory blocks of the fragmented virtual memory space to another virtual memory space to resolve the memory fragmentation even when a memory fragmentation occurs.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: August 2, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Kyu Koo, Sang-Bok Han, Myung Sun Kim, In Choon Yeo