Solid-state Random Access Memory (ram) Patents (Class 711/104)
  • Patent number: 10810123
    Abstract: A method, computer program product, and computer system for receiving, by a computing device, an I/O request. The I/O request may be processed as a write miss I/O. One or more dirty pages associated with the write miss I/O may be placed into a tree according to a key. It may be determined whether one of a first event and a second event occurs. A data flush may be triggered for the tree when the first event occurs, and the data flush may be triggered for the data flush for the tree when the second event occurs.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: October 20, 2020
    Assignee: EMC IP Holding Company, LLC
    Inventors: Xinlei Xu, Jian Gao, Lifeng Yang, Michael P. Wahl
  • Patent number: 10795605
    Abstract: An information handling system may include a resistive memory buffer to supplement a system main memory unit of the information handling system. A processor of the information handling system may map the resistive memory buffer as system memory, along with the system main memory unit. The processor may use the system memory, including the resistive memory buffer and the system main memory unit in executing one or more applications. The resistive memory buffer may improve performance of the information handling system, such as during hibernation and wake-up processes and memory flush processes.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: October 6, 2020
    Assignee: Dell Products L.P.
    Inventors: Mitchell A. Markow, Lee Zaretsky
  • Patent number: 10789143
    Abstract: A controller may include: a ROM code register configured to generate and store a ROM code including a plurality of firmware images; and a ROM controller configured to change an operation setting of a ROM based on an operation firmware image of the plurality of firmware images, wherein each of the plurality of firmware images includes an image header including attribute information on a corresponding firmware image and image data, and wherein the operation firmware image includes, as its image header, an operation image header, which includes an operation mode field indicating whether the operation setting of the ROM is changed, and, as its image data, operation image data including information on the operation setting of the ROM.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 29, 2020
    Assignee: SK hynix Inc.
    Inventor: Jung-Ae Kim
  • Patent number: 10733113
    Abstract: A memory system may include a volatile memory, a nonvolatile memory, and a controller. The controller may copy data from a memory to the other memory. The controller may include a page hit detection circuit and a page requester. The page hit detection circuit may generate information regarding page hit and page miss according to whether page information requested from a host and page information of the nonvolatile memory loaded in the volatile memory correspond to each other. The page requester may perform page swapping and transmit a ready response signal to the host.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventor: Jae Young Lee
  • Patent number: 10725680
    Abstract: The present disclosure includes apparatuses and methods to change data category values. An example is a memory device that includes an array having a plurality of sequences of memory cells, where each of the respective sequences of memory cells includes a plurality of designated subsets of memory cells, and the array includes a counter corresponding to one of the plurality of designated subsets of memory cells. The memory device is configured to receive input corresponding to a data batch, where the input includes a designation that corresponds to the one of the plurality of designated subsets of memory cells to be conditionally updated, and to change a numerical value stored by the counter corresponding to the one of the plurality of designated subsets of memory cells.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Jeremiah J. Willcock
  • Patent number: 10706105
    Abstract: Systems and techniques for collecting and using merge tree garbage metrics are described herein. A kvset is created for a node in a KVS tree. Here, a set of kvset metrics for the kvset are computed as part of the node creation. The kvset is added to the node. The node is selected for a compaction operation based on a metric in the set of kvset metrics. The compaction operation is performed on the node.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: David Boles, John M. Groves, Steven Moyer, Alexander Tomlinson
  • Patent number: 10698687
    Abstract: An example system includes a plurality of execution units, a shared resource, and an allocation control circuit. Each execution unit may generate a resource allocation request that includes a resource allocation size. The allocation control circuit may select a particular resource allocation request from the plurality of resource allocation requests, and determine an availability, based on an allocation register, of contiguous resource blocks within the shared resource. In response to determining that a number of the contiguous resource blocks satisfies a requested allocation size, the allocation control circuit may select an address corresponding to a particular resource block of the one or more contiguous resource blocks, and allocate the resource blocks to a corresponding execution unit. In response to a beginning of a second system clock cycle, the allocation control circuit may also update the allocation register based on the selected address and the requested allocation size.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: June 30, 2020
    Assignee: Apple Inc.
    Inventors: Dimitri Tan, Jeffrey T. Brady, Terence M. Potter, Jeffrey M. Broton, Frank W. Liljeros
  • Patent number: 10686906
    Abstract: A method, non-transitory computer readable medium and storage controller computing device that receives a read request from a client device. Data corresponding to the read request is retrieved from a flash cache comprising local flash memory. The data is returned to the client device in response to the read request. A determination is made when the data is stored in a flash pool. The flash pool comprises a plurality of solid state drives (SSDs). The data is inserted into the flash pool, when the determining indicates that the data is not stored in the flash pool. With this technology, a flash pool is populated based on hits in a flash cache. Accordingly, flash cache is utilized to provide low latency reads while the most important data is preserved in the flash pool to be used by another storage controller computing device in the event of a failover.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: June 16, 2020
    Assignee: NetApp, Inc.
    Inventors: Mark Smith, Brian Naylor, Naresh Patel
  • Patent number: 10673743
    Abstract: A first receiver device receives, from a sender device in a unicast communication, a data flow including a multicast identifier, the multicast identifier indicating that the data flow is to reach multiple receiver devices. The first receiver device determines that the data flow is to reach multiple receiver devices in response to detecting the multicast identifier. The first receiver device sends, to a second receiver device in a unicast communication, the data flow including the multicast identifier.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: June 2, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Michael R. Krause
  • Patent number: 10642488
    Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: store a namespace map mapping blocks of logical block addresses in a namespace to blocks from a logical address capacity of the non-volatile storage media; adjust the namespace map to change the size of the namespace; and translate logical addresses in the namespace to physical addresses for the non-volatile storage media using the namespace map.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Alex Frolikov
  • Patent number: 10613976
    Abstract: The present disclosure directs to solutions for performing deduplication by a storage device. In the solutions, according to a duplicate data locality principle, non-duplicate data blocks whose logical addresses are contiguous are stored in contiguous physical addresses in a sequence of the logical addresses, and fingerprints of the non-duplicate data blocks whose logical addresses are contiguous are also stored in contiguous physical addresses in the sequence of the logical addresses, and in addition, a mapping from a logical address, which is of one data block in the non-duplicate data blocks whose logical addresses are contiguous, to an aggregation address is established.
    Type: Grant
    Filed: April 22, 2018
    Date of Patent: April 7, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zongquan Zhang, Chengwei Zhang
  • Patent number: 10606513
    Abstract: A Memory Device (MD) includes a configurable Non-Volatile Memory (NVM) including a first memory array and a second memory array. The configurable NVM stores temporary data designated for volatile storage by a Central Processing Unit (CPU) and persistent data designated for non-volatile storage by the CPU. An address is associated with a first location in the first memory array and with a second location in the second memory array. In performing a command to write data for the address, it is determined whether to write the data in the second location based on a volatility mode set for the MD. According to another aspect, a CPU designates a memory page in a virtual memory space as volatile or non-volatile based on data allocated to the memory page, and defines the volatility mode for the MD based on whether the memory page is designated as volatile or non-volatile.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: March 31, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Viacheslav Dubeyko, Luis Cargnini
  • Patent number: 10607715
    Abstract: A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alper Buyuktosunoglu, Swagath Venkataramani, Rajiv Joshi, Karthik V. Swaminathan, Schuyler Eldridge, Pradip Bose
  • Patent number: 10592429
    Abstract: Cache memory for resistive switching memory modules is provided herein. The cache memory can reside on a separate DIMM from the resistive switching memory, in some embodiments, or can share a common DIMM with the resistive switching memory. Cache management protocols are provided to service read and write policies for managing interaction of data between the cache memory and the resistive switching memory. In various embodiments, memory controllers are optimized for physical characteristics of resistive switching memory, and cache management protocols can be implemented to take advantage of these characteristics.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: March 17, 2020
    Assignee: CROSSBAR, INC.
    Inventors: Mehdi Asnaashari, Robin Sarno, Ruchirkumar D. Shah
  • Patent number: 10579548
    Abstract: An example of a system includes a host interface, a set of non-volatile memory cells, and one or more control circuits coupled to the host interface and coupled to the set of non-volatile memory cells. The one or more control circuits are configured to access a host memory through the host interface by sending host memory access requests for two or more blocks of host data according to an interleaving scheme.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: March 3, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Elkana Richter, Shay Benisty
  • Patent number: 10545901
    Abstract: An apparatus includes a memory card that includes at least one memory module and an expansion connector to connect with at least one expansion memory card. A lane distributor on the memory card interfaces with a set of bidirectional lanes and provides a base lane set and an expanded lane set of bidirectional lanes to support communications with the memory module and the expansion memory card via the expansion connector.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: January 28, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Peter Seiler, Shane Ward, Byron A. Alcorn, Raphael Gay
  • Patent number: 10529421
    Abstract: A memory system includes a memory cell array including a plurality of resistive memory cells; a peripheral circuit suitable for providing a set pulse or a reset pulse with write data into a selected memory cell among the resistive memory cells, based on a write command; and a memory controller suitable for providing the write command with the write data to the peripheral circuit and scheduling the write command based on an amount of power consumption calculated depending on the number of either low bits or high bits in the write data.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: January 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung-Gyu Jeong, Jung-Hyun Kwon, Do-Sun Hong, Won-Gyu Shin
  • Patent number: 10521134
    Abstract: A memory system has a first memory which comprises a nonvolatile memory data region, and a second memory which stores data before storing in a third memory, the data not being written back on the third memory in a lower-level with access priority lower than access priority of the first memory, among data inside the nonvolatile memory data region, wherein the second memory has a bit error rate lower than a bit error rate of the first memory.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: December 31, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroki Noguchi, Shinobu Fujita
  • Patent number: 10521294
    Abstract: In one implementation, a memory module with on-die error correction code (ECC) with scrub operation capabilities and a programmable patrol scrub period is coupled to a memory controller that causes error correction operations to perform based on a power status of an energy storage device.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: December 31, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Reza M Bacchus
  • Patent number: 10509594
    Abstract: A memory module includes memory devices; data buffers suitable for receiving write data transferred from a memory controller and transmitting read data to the memory controller; a buffer control signal generation circuit suitable for generating buffer control signals for controlling the data buffers, by using a command transferred from the memory controller; a command delay circuit suitable for generating an effective command by delaying the command by a delay amount of the buffer control signal generation circuit in a read operation and a write operation; a data processing circuit suitable for processing write data transferred from the data buffers and transferring processed write data to the memory devices, and processing read data transferred from the memory devices and transferring processed read data to the data buffers, in response to the effective command; and a command buffer circuit suitable for transferring the effective command to the memory devices.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: December 17, 2019
    Assignee: SK hynix Inc.
    Inventor: Kwan-Dong Kim
  • Patent number: 10496286
    Abstract: The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: December 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jason T. Zawodny, Glen E. Hush, Troy A. Manning, Timothy P. Finkbeiner
  • Patent number: 10481802
    Abstract: A method, computer program product, and computer system for receiving, by a computing device, an I/O request for data. A number of storage devices of a plurality of storage devices in a Mapped RAID group that will be used to process the I/O request may be determined. It may be determined that an amount of I/O credits available for the number of storage devices is insufficient. The amount of I/O credits available for the number of storage devices to process the I/O request may be tuned dynamically based upon, at least in part, determining that the amount of I/O credits available for the number of storage devices is insufficient.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: November 19, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Jian Gao, Geng Han, Jibing Dong, Shaoqin Gong, Ree Sun, Naizhong Chiu, Xinlei Xu, Jamin Kang
  • Patent number: 10474378
    Abstract: A memory system includes a memory controller; a first memory module, the first memory module including first volatile memory devices; a second memory module, the second memory module including nonvolatile memory devices; a data bus for transmitting data between the memory controller and the first memory module and between the memory controller and the second memory module; a first control bus for transmitting first control signals between the memory controller and the first memory module and between the memory controller and the second memory module; a second control bus for transmitting second control signals between the memory controller and the first memory module; and a third control bus for transmitting third control signals between the memory controller and the second memory module, wherein, in a backup operation, the second control bus and the third control bus are electrically coupled.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: November 12, 2019
    Assignee: SK hynix Inc.
    Inventor: Chan-Jong Woo
  • Patent number: 10452392
    Abstract: A programmable integrated circuit device includes a plurality of clusters of programmable logic resources. Programmable device interconnect resources allow user-defined interconnection between the clusters of programmable logic resources. A plurality of specialized processing blocks have dedicated arithmetic operators and programmable internal interconnect resources, and having inputs and outputs programmably connectable to the programmable device interconnect resources. A plurality of embedded memory modules have inputs and outputs programmably connectable to the programmable device interconnect resources. Instruction sequencing circuitry is provided, and the instruction sequencing circuitry, at least one of the specialized processing blocks and at least one of the embedded memory modules, are programmably connectable to form a processor, where the memory module serves as instruction memory.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: October 22, 2019
    Assignee: Altera Corporation
    Inventors: David Lewis, Valavan Manohararajah
  • Patent number: 10452531
    Abstract: A memory system including a memory subsystem and a memory controller is provided. The memory subsystem includes a plurality of first memory modules implemented by a phase-change memory and a second memory module implemented by a memory whose write speed is faster than that of the phase-change memory. The memory controller generates a non-blocking code from a plurality of sub-data into which original data are divided, writes the non-blocking code to the second memory module, writes the plurality of sub-data to the plurality of first memory modules, respectively, and reconstructs the original data from some sub-data of the plurality of sub-data which are read from some of the plurality of first memory modules and the non-blocking code read from the second memory under a predetermined condition at a read request.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: October 22, 2019
    Assignees: MEMRAY CORPORATION, YONSEI UNIVERSITY, UNIVERSITY—INDUSTRY FOUNDATION (UIF)
    Inventors: Myoungsoo Jung, Gyuyoung Park
  • Patent number: 10445177
    Abstract: A method for updating a DRAM memory array is disclosed. The method comprises: a) transitioning the DRAM memory array from an idle state to a refresh state in accordance with a command from a memory controller; b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry by activating a row of data into an associated sense amplifier buffer; and c) during the refresh, performing an ERR Correction Code (ECC) scrub operation of selected bits in the activated row of the DRAM memory array.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: October 15, 2019
    Assignee: Nvidia Corporation
    Inventors: David Reed, Alok Gupta
  • Patent number: 10437892
    Abstract: Methods and computer storage media are provided for generating entries for documents in a forward index. A document and its document identification are received, in addition to static features that are query-independent. The document is parsed into tokens to form a token stream corresponding to the document. Relevant data used to calculate rankings of document is identified and a position of the data is determined. The entry is then generated from the document identification, the token stream of the document, the static features, and the positional information of the relevant data. The entry is stored in the forward index.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: October 8, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Knut Magne Risvik, Michael Hopcroft, John G. Bennett, Karthik Kalyanaraman, Trishul Chilimbi, Chad P. Walters, Vishesh Parikh, Jan Otto Pedersen
  • Patent number: 10417146
    Abstract: An embodiment of an apparatus includes a retry queue circuit, a transaction arbiter circuit, and a plurality of transaction buffers. The retry queue circuit may store one or more entries corresponding to one or more memory transactions. A position in the retry queue circuit of an entry of the one or more entries may correspond to a priority for processing a memory transaction corresponding to the entry. The transaction arbiter circuit may receive a real-time memory transaction from a particular transaction buffer. In response to a determination that the real-time memory transaction is unable to be processed, the transaction arbiter circuit may create an entry for the real-time memory transaction in the retry queue circuit. In response to a determination that a bulk memory transaction is scheduled for processing prior to the real-time memory transaction, the transaction arbiter circuit may upgrade the bulk memory transaction to use real-time memory resources.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: September 17, 2019
    Assignee: Apple Inc.
    Inventors: Sridhar Kotha, Neeraj Parik, Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan, Xiaoming Wang
  • Patent number: 10394456
    Abstract: Systems, devices, and methods related to on demand memory page size are described. A memory system may employ a protocol that supports on demand variable memory page sizes. A memory system may include one or more non-volatile memory devices that may each include a local memory controller configured to support variable memory page size operation. The memory system may include a system memory controller that interfaces between the non-volatile memory devices and a processor. The system memory controller may, for instance, use a protocol that facilitates on demand memory page size where a determination of a particular page size to use in an operation may be based on characteristics of memory commands and data involved in the memory command.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Duane R. Mills, Richard E. Fackenthal
  • Patent number: 10353636
    Abstract: A write filter can be configured to employ a dynamically expandable overlay. The size of the overlay could initially be small and could then grow and shrink during the current session based on demand. The overlay can span both RAM and disk to thereby allow the size of the overlay to be relatively large. When sufficient RAM is available, the overlay can be allowed to grow in RAM. In contrast, if RAM is low, the overlay can grow on disk. Also, artifacts in the overlay can be moved from the RAM portion to the disk portion to reduce the amount of RAM consumed by the overlay. Because the overlay is dynamically expandable, it will typically not become full and will therefore not force a reboot.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: July 16, 2019
    Assignee: WYSE TECHNOLOGY L.L.C.
    Inventors: Puneet Kaushik, Salil S Joshi, Sumit Popli
  • Patent number: 10339992
    Abstract: A semiconductor system may include a controller configured to provide a command clock and a control signal to a semiconductor memory device, and the semiconductor memory device configured to transmit/receive external data and a plurality of data clocks to/from the controller, wherein the plurality of data clocks comprise a first read data strobe signal and a second read data strobe signal, and the semiconductor memory device transmits both of the first read data strobe signal and the second read data strobe signal to the controller or transmits one of the first read data strobe signal and the second read data strobe signal to the controller, based on an operation select signal.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: July 2, 2019
    Assignee: SK hynix Inc.
    Inventors: Keun Soo Song, Woo Yeol Shin
  • Patent number: 10303363
    Abstract: A system and method is provided for data storage using log-structured merge (LSM) trees. An example method includes storing data blocks for a number of files backup data files in a data archive, storing data values and corresponding segment identifiers for each data block in a first LSM tree, and storing the segment identifiers and associated physical addresses for each data block in a second LSM tree. The method further includes determining that one or more data blocks is no longer referenced by the backup data file and storing, in a third LSM tree, the physical address of the unused space in the data archive. Finally, the method includes copying data blocks from the end of the data archive to unused memory space at the physical address in the data archive and then deleting these data block at the end position of the archive to truncate the archive.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: May 28, 2019
    Assignee: Acronis International GmbH
    Inventors: Vitaly Pogosyan, Kirill Korotaev, Mark Shmulevich, Stanislav Protasov, Serguei Beloussov
  • Patent number: 10275159
    Abstract: An embedded device, a RAM disk of an embedded device and a method of accessing a RAM disk of an embedded device are provided. The embedded device includes: a processing unit, configured to execute an operating system; a first memory, for the processing unit to access required system data when the processing unit executes the operating system; a function module, configured to perform a predetermined function; a second memory, for the function module to access required functional data through direct memory access when the function module performs the predetermined function; and a RAM disk driving module, configured to incorporate a first part of the first memory with the second memory to one RAM disk, and to control access of the RAM disk.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: April 30, 2019
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Chien-Hsing Huang, Hsin-Hsiung Tseng
  • Patent number: 10255145
    Abstract: In one embodiment, two or more programmable multimedia controllers are provided a multimedia system that includes a plurality of audio/video (A/V) devices that source or output digital media streams. Each of the programmable multimedia controllers has at least a processing subsystem and a switch capable of switching the digital media streams. Arbitration is conducted among the programmable multimedia controllers to select one of the programmable multimedia controllers as winning the arbitration. Master status is assigned to the one of the programmable multimedia controllers that won the arbitration. Subordinate status is assigned to at least one other programmable multimedia controller that did not win the arbitration. It is periodically verified whether the programmable multimedia controller assigned master status is operating.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: April 9, 2019
    Assignee: Savant Systems, LLC
    Inventors: Siegmar K. Eschholz, Michael C. Silva
  • Patent number: 10223261
    Abstract: A lightweight architecture for an aliased memory operation includes loading data by performing an aliased memory operation, and storing data by performing an aliased memory operation, the loading of data by performed by an aliased memory operation that includes: requesting an aliased address through an HAT without a specific operation for converting an address by means of a CPU processor, converting an address input through the HAT into an aliased address in response to the request for an aliased address, stopping the aliased memory operation through the HAT and calling up a miss handler when the conversion of an address into an aliased address in response to the request for an aliased address fails, and loading data by accessing an SAT using the aliased address when conversion of an address into an aliased address succeeds.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: March 5, 2019
    Assignee: UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
    Inventors: Woongki Baek, Seung Hoe Kim
  • Patent number: 10210080
    Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: February 19, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern
  • Patent number: 10210097
    Abstract: A request is received to load a particular overlay segment from a secondary storage memory to a main memory for execution by a processor, wherein the particular overlay segment is absent from the main memory. A determination is made whether the main memory can receive the particular overlay segment. In response to determining that the main memory cannot receive the particular overlay segment, eviction strategy information about one or more existing overlay segments that are present in the main memory is obtained. Based on the eviction strategy information, at least one of the one or more existing overlay segments is selected for eviction from the main memory. The particular overlay segment is retrieved from the secondary storage memory. The at least one of the one or more existing overlay segments in the main memory that is selected for eviction is replaced with the particular overlay segment.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: February 19, 2019
    Assignee: Macronix International Co., Ltd.
    Inventors: Tzu-Yi Yang, Ting-Yu Liu, Yi-Chun Liu
  • Patent number: 10204669
    Abstract: A semiconductor system may include a controller configured to provide a first external clock and a control signal to a semiconductor device, and the semiconductor device configured to transmit/receive external data and a plurality of second external clocks to/from the controller, wherein the plurality of second external clocks comprise a third primary external clock and a third secondary external clock, and the semiconductor device transmits both of the third primary external clock and the third secondary external clock to the controller or transmits one of the third primary external clock and the third secondary external clock to the controller, based on an operation select signal.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: February 12, 2019
    Assignee: SK hynix Inc.
    Inventors: Keun Soo Song, Woo Yeol Shin
  • Patent number: 10184272
    Abstract: An installation-free rechargeable access control system is disclosed which automates the action of locking and unlocking a single-cylinder deadbolt on a door. In various embodiments, the present teachings provide a portable electronic module that can enhance the usage of deadbolts in place, instead of replacing the deadbolt mechanism itself. In various embodiments, the access control system can authenticate users and rotate a deadbolt using one or more peripheral sensing sources and wireless protocols.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: January 22, 2019
    Inventor: Dominick S. Lee
  • Patent number: 10162758
    Abstract: A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of cache entries in a cache, wherein the processor core is to: detect an amount of the memory installed in a computing system and, responsive to detecting less than a maximum allowable amount of the memory for the computing system, direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventor: Ruchira Sasanka
  • Patent number: 10141935
    Abstract: On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: November 27, 2018
    Assignee: Intel Corporation
    Inventors: Kuljit S Bains, Alexey Kostinsky, Nadav Bonen
  • Patent number: 10115442
    Abstract: A computing device may comprise a processor, a volatile memory and a non-volatile storage device. An operating system or firmware of the device may cause one or more pages of the volatile memory to be treated, by applications executing on the computing device, as non-volatile memory pages. A number of pages that may be treated as non-volatile may be determined based on demand for non-volatile storage by at least one application executing on the computing device.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 30, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bryan D. Kelly, Mallik Bulusu, Ravi Mysore Shantamurthy, Tom L. Nguyen
  • Patent number: 10108658
    Abstract: A data store manager of a multi-data-store journal-based database performs a sequential analysis of committed transaction entries of a journal. A particular entry includes a directive to determine a value of an attribute of a data object based on a result obtained from a value generator, and does not specify the value of the attribute. The data store manager determines the value using a local version of the value generator, and stores the value in a materialized version of the data object. In response to a programmatic read request, the data store manager provides the materialized version of the data object.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: October 23, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Timothy Daniel Cole, Michael Benjamin Deardeuff, Artem Danilov, John Michael Morkel, Tate Andrew Certain, Christopher Richard Jacques De Kadt, Aaron Gifford Freshwater, Allan Henry Vermeulen, Andrew Wayne Ross
  • Patent number: 10043561
    Abstract: A semiconductor system may include a controller and a semiconductor memory device. The controller may provide an external command, an external address and a first external clock. The controller may be configured to transmit a second external clock and receive a third external clock for receiving/transmitting external data. The semiconductor memory device may be configured to synchronize and receive the external address and the external command with the first external clock. The semiconductor memory device may be configured to synchronize and receive the external data with the second external clock. The semiconductor memory device may be configured to transmit the external data and the third external clock to the controller.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: August 7, 2018
    Assignee: SK hynix Inc.
    Inventors: Keun Soo Song, Woo Yeol Shin
  • Patent number: 10013170
    Abstract: Determining whether to compress data of a virtual storage unit based at least in part on: an I/O activity value of a virtual storage unit; a compressibility value of the virtual storage unit; and/or a capacity utilization of the storage system or a component thereof. For example, decision logic may be configured based on one or more of such parameters such that virtual storage units with relatively high I/O activities are rarely or never compressed, e.g., to avoid the disproportionately high increases in CPU and bandwidth resource consumption and I/O latency this could create. Decision logic may be configured such that, in general, the likelihood that a virtual storage unit will be compressed increases as: the I/O activity of the virtual storage unit decreases; the system capacity utilization increases; and/or as the compressibility value of the virtual storage unit increases.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 3, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Adnan Sahin, Owen Martin, Jeremy J. O'Hare
  • Patent number: 9984746
    Abstract: According to an embodiment, a memory device includes a nonvolatile memory, a controller, and power storage. The controller is configured to receive, from a host device, a write request for writing data into the nonvolatile memory, and then, write the data based on the write request. The power storage is configured to store power supplied from a power supply. The controller writes, when abnormality in power supplied from the power supply to the memory device is detected, the data based on the write request that has already been received, using the power supplied from the power storage.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: May 29, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsunori Kanai, Tetsuro Kimura, Masaya Tarui, Yusuke Shirota, Shiyo Yoshimura
  • Patent number: 9959086
    Abstract: There are provided an electronic device and a control method thereof. First contents related to an image and second contents generated by converting the recorded audio into text are displayed on a touchscreen, instead of a playback screen of the image when the electronic device plays the image and enters a mode for recording audio. Thus, a user can use a image, when viewing and listening to it, in various manners.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 1, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Sungchae Na, Jungeun Shin
  • Patent number: 9946513
    Abstract: A spin unit provided with a memory cell that stores a value of one spin of an Ising model, a memory cell that stores an interaction coefficient from an adjacent spin which interacts with the corresponding spin, a memory cell that stores an external magnetic field coefficient of the one spin and circuits that determine the next state of the one spin on the basis of a product of a value of each adjacent spin and the corresponding interaction coefficient and the external magnetic field coefficient is configured, the semiconductor device is provided with a spin array where the plural spin units are arranged and connected on a two-dimensional plane on a semiconductor substrate, a random number generator and a bit regulator, the bit regulator operates output of the random number generator and supplies a random bit to all spin units in the spin array via one wire.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: April 17, 2018
    Assignee: HITACHI, LTD.
    Inventors: Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura
  • Patent number: 9947386
    Abstract: A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.
    Type: Grant
    Filed: September 21, 2014
    Date of Patent: April 17, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Manish Arora, Indrani Paul, Yasuko Eckert, Nuwan Jayasena, Dong Ping Zhang
  • Patent number: 9916881
    Abstract: A semiconductor system may include a controller and a semiconductor memory device. The controller may provide an external command, an external address and a first external clock. The controller may be configured to transmit a second external clock and receive a third external clock for receiving/transmitting external data. The semiconductor memory device may be configured to synchronize and receive the external address and the external command with the first external clock. The semiconductor memory device may be configured to synchronize and receive the external data with the second external clock. The semiconductor memory device may be configured to transmit the external data and the third external clock to the controller.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: March 13, 2018
    Assignee: SK hynix Inc.
    Inventors: Keun Soo Song, Woo Yeol Shin