Abstract: A data transmission method includes: obtaining a target data packet to be stored, the target data packet including an address of the target data packet; determining, from predetermined N parallel-to-serial units based on the address of the target data packet, a target parallel-to-serial unit corresponding to the target data packet, the N parallel-to-serial units being connected to N storage control units in one-to-one correspondence; and transmitting, by the target parallel-to-serial unit, the target data packet to a target storage control unit, and storing, by the target storage control unit, the target data packet in a corresponding storage unit. The target storage control unit is a storage control unit, connected to the target parallel-to-serial unit, of the N storage control units. The target parallel-to-serial unit is configured to divide the target data packet into a plurality of data sub-packets.

Abstract: A plurality of work items are processed through a processing pipeline comprising a plurality of stages in processing logic. The processing of a work item includes: (i) reading data in accordance with a memory address associated with the work item, (ii) updating the read data, and (iii) writing the updated data in accordance with the memory address associated with the work item. The method includes processing a first work item and a second work item through the processing pipeline, wherein the processing of the first work item through the pipeline is initiated earlier than the processing of the second work item, and where it is determined that the first and second work items are associated with the same memory address, first updated data of the first work item is written to a register in the processing logic, and the processing of the second work item comprises reading the first updated data from the register instead of reading data from the memory.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

Abstract: A computer-implemented method for efficiently performing a database join in a distributed data processing system comprising multiple computational nodes, the method comprising determining a first set of one or more columns of a first database table and a second set of one or more columns of a second database table on which the join is to be performed; estimating a size of the rows of the first table which have a particular combination of values in the first set of columns; computing a salt factor n based on the estimated size of rows and further based on a processing capacity of a computational node of the distributed data processing system; assigning one of n different salt values to each row of the first table having the particular combination of values in the first set of columns; for each row of the second table having the particular combination of values in the second set of columns into n rows, expanding the row into n row, and assigning to each expanded row a different one of the n salt values; and per

Abstract: Predicates for processing in memory is described. In accordance with the described techniques, a predicate instruction to compute a conditional value based on data stored in a memory is provided to a processing-in-memory component. A response that includes the conditional value computed by the processing-in-memory component is received, and the conditional value is stored in a predicate register. One or more conditional instructions are provided to the processing-in-memory component based on the conditional value stored in the predicate register.

Abstract: A data processing method and a storage apparatus are disclosed. The data processing method includes: receiving, by an NVMe storage device, an NVMe write command sent by a host, where the NVMe write command carries a key and a value pointer, the value pointer points to first storage space, and the first storage space is used to store a value; obtaining, by the NVMe storage device, the key from the NVMe write command and a value length, and allocating second storage space to the value according to the value length, where the second storage space is in the NVMe storage device; and obtaining, by the NVMe storage device, the value from the host, and storing the value in the second storage space.

Abstract: A data segment to be stored at one or more storage devices is formed, wherein the data segment is to be stored at the one or more storage devices using a first programming mode having a first page size. A determination that a fragment of data of the data segment is less than the first page size is made. The fragment of data is stored at the one or more storage devices using a second programming mode having a second page size that is less than the first page size and the remaining data of the data segment is stored at the one or more storage device using the first programming mode.

Abstract: Sensor devices, systems, and methods for measuring different components of a flow are provided. A sensing arrangement includes a substrate and first and second sensor arrays on the substrate. The first sensor array sensing elements are distributed to obtain measurement data indicative of a first property of an operating environment, such as a turbulent component of a fluid flow. The second sensor array sensing elements are interspersed amongst the first sensor array and distributed to obtain measurement data indicative of a second property of the operating environment, such as an acoustic component of the fluid flow.

Abstract: Technologies are provided for increasing electronic noise of a memory device during an initialization of the memory device and performing initialization operations, such as memory access centering operations, for the memory device while the electronic noise of the memory device is increased. The electronic noise of the memory device can be increased by increasing a level of ground bounce (or ground noise) during a training phase of the memory device. Increasing the ground noise can comprise increasing an inductance across a memory of the memory device during the training phase. The inductance can be increased by deactivating one or more ground connections of the memory during the memory's training phase. Additionally or alternatively, the inductance can be increased by activating one or more inductors connected to one or more ground connections of the memory during the memory's training phase.

Abstract: The disclosure provides a data bus inversion (DBI) encoding device and a DBI encoding method. The DBI encoding device includes a comparator circuit, a first controllable inverting circuit and a second controllable inverting circuit. The comparator circuit checks the number of the different bits between a first raw data and a second raw data. Based on the number of the different bits, the first controllable inversion circuit determines whether to invert a first DBI bit corresponding to the first raw data as a second DBI bit corresponding to the second raw data. The second controllable inversion circuit determines, based on the second DBI bit, whether to adopt the second raw data as a second encoded data corresponding to the second raw data, or invert the second raw data to generate the second encoded data.

Abstract: An apparatus for storing a key value store file according to an embodiment includes a memory configured to record one or more key values in a predefined unit space based on a data input request from an outside, a controller configured to store data received from the memory in a storage, and the storage configured to include a plurality of zones. The controller is configured to perform a flush operation of storing one or more key values received from the memory as a file in a predefined format in the storage and a compaction operation of merging a plurality of files existing in one level in the storage and recording the merged files as one file in another level.

Abstract: A data storage device includes multiple storage modules. Each storage module includes a storage which having a memory device and a first memory controller and a second memory controller. The first memory controller is coupled to the memory device for accessing the memory device. The second memory controller is coupled to the storage for accessing the storage. The first memory controller includes a first transmission interface. The second memory controller includes a second transmission interface. The first memory controller and the second memory controller communicate with each other through the first transmission interface and the second transmission interface.

Abstract: A three-dimensional (3D) memory device includes a 3D NAND memory array, an on-die static random-access memory (SRAM), and peripheral circuits formed on the same chip with the on-die SRAM. The peripheral circuits include a page buffer coupled to the on-die SRAM and a controller coupled to the on-die SRAM and the page buffer. The controller may be configured to load program data into the page buffer and cache the program data into the on-die SRAM as a backup copy of the program data. In response to a status of programming the program data from the page buffer into the 3D NAND memory array being failed, the controller may be further configured to transmit the backup copy of the program data in the on-die SRAM to the page buffer, and program the backup copy of the program data in the page buffer into the 3D NAND memory array.

Abstract: Embodiments described herein improve availability of a power plane in a network device by using a PoE manager that is separate from an operating system in the network device. For example, when the operating system (or a PoE application executing in the operating system) becomes unavailable, either because of failure or system upgrade, the PoE manager continues managing a power plane in the network device such that connected PDs continue to receive DC power. Stated differently, by using a PoE manager that is separate from the operating system, there is no fate sharing between the PoE manager and the operating system. If the operating system is unavailable, the PoE manager continues to provide the same power allotment to the PDs. As such, updates and failures which previously made the power plane unavailable no longer affect the power supplied to the PDs.

Abstract: A cascading search system includes an associative memory array, a similarity match processor and an exact match processor. The columns of the array store a plurality of multiportion data vectors and have a first section, for a first portion of a vector, a second section for storing a second portion of a vector and a match row. The similarity match processor performs a parallel similarity search of a similarity query in the first sections and stores a match bit indication in the match row of the column. Each match bit indication indicates if its column has a first portion which matches the similarity query. The exact match processor performs an exact search in parallel in the second section of each similarity matched column whose match bit indication indicates a match of its first section and outputs those similarity matched columns whose second portions match the exact query.

Abstract: Systems and methods for performing data protection operations including garbage collection operations and copy forward operations. For deduplicated data stored in a cloud-based storage or in a cloud tier that stores containers containing dead and live segments, the dead segments are deleted by copying live segments into new containers and then deleting the old containers. The copy forward is based on a recipe from a data protection system and is performed using a microservices that can be run as needed in the cloud.

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

Abstract: Techniques are provided for implementing garbage collection and bin synchronization for a distributed storage architecture of worker nodes managing distributed storage composed of bins of blocks. As the distributed storage architecture scales out to accommodate more storage and worker nodes, garbage collection used to free unused blocks becomes unmanageable and slow. Accordingly garbage collection is improved by utilizing heuristics to dynamically speed up or down garbage collection and set sizes for subsets of a bin to process instead of the entire bin. This ensures that garbage collection does not use stale information about what blocks are in-use, and ensures garbage collection does not unduly impact client I/O processing or conversely falls behind on garbage collection. Garbage collection can be incorporated into a bin sync process to improve the efficiency of the bin sync process so that unused blocks are not needlessly copied by the bin sync process.

Abstract: Techniques are provided for implementing garbage collection and bin synchronization for a distributed storage architecture of worker nodes managing distributed storage composed of bins of blocks. As the distributed storage architecture scales out to accommodate more storage and worker nodes, garbage collection used to free unused blocks becomes unmanageable and slow. Accordingly garbage collection is improved by utilizing heuristics to dynamically speed up or down garbage collection and set sizes for subsets of a bin to process instead of the entire bin. This ensures that garbage collection does not use stale information about what blocks are in-use, and ensures garbage collection does not unduly impact client I/O processing or conversely falls behind on garbage collection. Garbage collection can be incorporated into a bin sync process to improve the efficiency of the bin sync process so that unused blocks are not needlessly copied by the bin sync process.

Abstract: One example method includes ingesting data to a data protection system, separating, by the data protection system, the ingested data into groups according to Recovery Point Objective (RPO) such that each group is associated with a different respective RPO, storing the groups in respective storage pools, and each of the storage pools is associated with a respective one of the RPOs, and performing a respective garbage collection (GC) process at each storage pool.

Abstract: A serial data buffer integrated circuit comprises unidirectional host-side input and output ports, and unidirectional memory-side input and output ports. Scheduling logic generates memory device commands for writing to and reading from a memory device based on a set of host-side input packets received from a memory controller. A unidirectional serial host side input port receives host-side input packets from the memory controller. A unidirectional serial memory side output port transmits the memory device commands and the write data to the memory device based on the scheduled timing. A unidirectional serial memory side input port receives read data from the memory device in response to a read command, and a unidirectional serial host side output port transmits the read data to the memory controller within the timing constraints of the memory device.

Abstract: A method includes determining a respective number of and respective locations of valid data portions of a plurality of blocks of NAND memory cells, based on the respective locations of the valid data portions, determining respective dispersions of the valid data portions within the plurality of blocks of NAND memory cells, based at least on the respective dispersions, selecting a block of NAND memory cells from the plurality of blocks of NAND memory cells, and performing a folding operation on the selected block.

Abstract: A method and system for initiating a garbage collection request. Historical data representative of a level of initiated I/O requests is acquired. A first operational state and a second operational state are determined based on the historical data. The first operational state and second operational state are expressed in an indication of the level of initiated I/O requests to be processed. A number of currently initiated I/O requests is acquired. A determination is made as to whether the number of currently initiated I/O requests is indicative of the first operational state or the second operational state. If the computer system is in the first operational state, the garbage collection request is initiated.

Abstract: Methods, systems, apparatus, including computer programs encoded on computer storage media, for reclaiming storage space in a storage environment. In one aspect, the method includes actions of aggregating data that is indicative of access to one or more data objects, determining a future storage cost associated with each of a plurality of data objects, determining an access window for each of the plurality of data objects, identifying a data object based on (i) the future storage cost that satisfies a predetermined threshold and (ii) a data object access window, providing a notification to a user device that requests feedback from a user indicating whether the data object can be deleted, and in response to receiving data that indicates that the data object can be deleted, generating an instruction to cause deletion of the data object upon the expiration of the access window.

Abstract: Methods, systems, and devices for data movement based on address table activity are described. A memory system may support a first type of data movement operation and a second type of data movement operation. The memory system may select between the first type of data movement operation and the second type of data movement operation for a region based on address table activity for the region.

Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

Abstract: A network interface controller (NIC) capable of efficient operation management for host accelerators is provided. The NIC can be equipped with a host interface and triggering logic block. During operation, the host interface can couple the NIC to a host device. The triggering logic block can obtain, via the host interface from the host device, an operation associated with an accelerator of the host device. The triggering logic block can determine whether a triggering condition has been satisfied for the operation based on an indicator received from the accelerator. If the triggering condition has been satisfied, the triggering logic block can obtain a piece of data generated from the accelerator from a memory location and execute the operation using the piece of data.

Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

Abstract: Methods and systems for managing data in a distributed system are disclosed. The distributed system may include devices used by users (e.g., clients) and devices in which data is stored for future accessibility (e.g., storage providers). A data storage system may manage the data for the clients. To manage the data efficiently, the data storage system may perform an integrated process of both verifying that segments of files believed to be stored are actually stored and segments of files that no longer need to be stored are removed. The process may not be performed in real-time as files that no longer need to be stored are identified (e.g., as deletion requests are received). Rather, the integrated process may employ a garbage collection process where deletion conditions for segments are checked intermittently over time, and files are verified.

Abstract: Systems, architectures, devices, and methods for matching experimentally acquired mass spectrometry data with a peptide database are provided. The system architecture can include a host central processing unit (CPU) system, a bridge connecting the CPU system with a core control register (or registers), a plurality of processing elements (PEs), and a bus arbiter. The PEs can execute the computations in a parallel and asynchronous manner. The bus arbiter can be a first-come first-serve (FCFS)-based bus arbiter (i.e., can utilize an FCFS-based arbitration scheme).

Abstract: According to one embodiment, a memory system determines a write destination block and a write destination location in the write destination block to which write data is to be written, and notifies a host of an identifier of the write data, a block address of the write destination block, and an offset indicative of the write destination location. The memory system retrieves the write data from a write buffer of the host, and writes the write data to the write destination location. In a case where a read command to designate a physical address of first data is received before a write operation of the first data is finished, the memory system reads the first data from the write buffer of the host.

Abstract: Systems, architectures, devices, and methods for matching experimentally acquired mass spectrometry data with a peptide database are provided. The system architecture can include a host central processing unit (CPU) system, a bridge connecting the CPU system with a core control register (or registers), a plurality of processing elements (PEs), and a bus arbiter. The PEs can execute the computations in a parallel and asynchronous manner. The bus arbiter can be a first-come first-serve (FCFS)-based bus arbiter (i.e., can utilize an FCFS-based arbitration scheme).

Abstract: A controller of a memory sub-system can, responsive to providing a command completion signal to a host, mark a portion of a plurality of commands that are addressed to a same logical block of the memory devices, reorder the marked portion of the plurality of commands, wherein write commands from the marked portion of the plurality of commands are given priority over read commands from the marked portion of the plurality of commands, execute a newest write command from the marked portion of the plurality of commands prior to executing read commands, addressed to the same logical block, from the marked portion of the plurality of commands, and execute read commands from the marked portion of the plurality of commands in on an order in which the read commands were received and after the execution of the newest write command, wherein the read commands are executed responsive to an execution of the newest write command.

Abstract: Embodiments are directed to a cost-aware object selection for cloud garbage collection that deletes completely dead objects and also selects low-live objects up to a carefully selected liveness threshold value. This threshold is dynamically chosen per cloud garbage collection cycle by balancing costs including egress, input/output operations (IOPs), storage cost of cleaning partial live objects, and the storage cost incurred by leaving behind dead data by not cleaning the object. The threshold value is dynamically calculated to accommodate different cost models for different cloud providers and also caters to different costs for different storage tiers.

Abstract: The described technology is generally directed towards fine-grained data event expiration in a streaming data storage system. An event to append is given an expiration period, and the expiration time for the events in a data stream or segment of a data stream is the largest expiration time among events in the data stream or segment. Different segments can have different expiration times for their events. In a segment comprising a group of events, a subgroup of expired events prior to a stream cut are deleted by an expiration task. For a subgroup of unexpired events prior to a stream cut, the expiration task retains (does not delete) the subgroup of events. If a scaling operation is performed on a segment, the new successor segment or segments inherit the largest expiration time of the predecessor segment or segments.

Abstract: A product, system, and/or method of managing memory media that includes: determining whether the memory system is low on one or more ready-to-use (RTU) Block Stripes needed to form a RTU Block Stripe Set, wherein the memory media has a plurality of Planes in each Die, all the memory media Blocks in each Block Stripe are from the same Die #and the same Plane #, each Block Stripe Set is formed of a plurality of Block Stripes all from the same Die #, and all the Blocks in each RTU Block Stripe Set have been subject to the removal process and the erasure process. The product, system, and/or method includes: establishing a pending request for a removal process and/or an erasure process for one or more determined Die #/Plane #combinations; and prioritizing in the one or more determined Die #/Plane #combinations one or more memory media Blocks for the removal and/or erasure process.

Abstract: A storage device includes: a memory device including a plurality of system blocks for storing system data; and a memory controller configured to control the memory device to store cyclic system data that is cyclically provided from a host, in an open system block among the plurality of system blocks, and control the memory device to perform a garbage collection operation on the plurality of system blocks, when a size of data stored in the open system block reaches a predetermined size. The cyclic system data may include a plurality of data slices provided from the host at predetermined cycles. The predetermined size may be determined based on size of the cyclic system data provided for a period of time corresponding to a common multiple of the predetermined cycles.

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

Abstract: A storage control system maintains a write cache in a non-volatile memory device of primary memory of a storage node. The write cache comprises a cyclic buffer and pointers to manage the write cache and track a tail location and head location of the write cache. The storage control system receives a write request from a host system, which comprises a data item to be written to primary storage. The received data item is written together with an associated metadata item at the head location of the write cache. The items in the write cache are arranged in a cyclic write order from the tail location to the head location. The storage control system sends an acknowledgment to the host system that the data item is successfully written to the primary storage, in response to the received data item and the associated metadata item being stored in the write cache.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The data storage device supports zoned namespace. The controller is configured to maintain a zone timestamp table that includes a corresponding timestamp for each zone and add a timestamp to each garbage collection block of the memory device. The controller is further configured to scan a garbage collection block from a last physical block address (PBA) entry to a first PBA entry, determine a zone timestamp for the scanned PBA entry, and compare the zone timestamp to a timestamp of the garbage collection block. The controller is further configured to create and maintain a zone timestamp table and create and maintain a zone based defragmentation table.

Abstract: Systems, apparatuses, and methods related to a selectively operable memory device are described. An example method corresponding to a selectively operable memory device can include receiving, by a resistance variable memory device, a command to operate the resistance variable memory device in a first mode or a second mode and operating the resistance variable memory device in the first mode or the second mode based, at least in part, on the received command to perform, in the first mode, a read operation or a write operation, or both, or, in the second mode, a compute operation. The method can further include performing, using a processing unit resident on the resistance variable memory device, the compute operation, the testing operation, or both based, at least in part, on a determination that the resistance variable memory device is operating in the second mode.

Abstract: According to one embodiment, a buffer stores first hash values and first complementary data. A first conversion unit converts consecutive characters in a second character string into second hash values and second complementary data. A search unit searches for consecutive first hash values from the buffer, and output a pointer. A selection unit selects consecutive first hash values and pieces of first complementary data from the buffer. A second conversion unit converts the consecutive first hash values into a third character string using the pieces of first complementary data. A comparison unit compares the second character string with the third character string to acquire a matching length. An output unit output the matching length with the pointer.

Abstract: A method includes determining a respective number of and respective locations of valid data portions of a plurality of blocks of NAND memory cells, based on the respective locations of the valid data portions, determining respective dispersions of the valid data portions within the plurality of blocks of NAND memory cells, based at least on the respective dispersions, selecting a block of NAND memory cells from the plurality of blocks of NAND memory cells, and performing a folding operation on the selected block.

Abstract: A technique performs Redundant Array of Independent Disks (RAID) transformation. The technique involves performing a garbage collection operation on a first uber within a storage array, the garbage collection operation freeing a set of disk slices of the first uber. The technique further involves, upon completing the garbage collection operation, reallocating storage of the set of disk slices from the first uber to a second uber within the storage array. The technique further involves, after the storage of the set of disk slices is reallocated from the first uber to the second uber, storing data within the second uber. Such leveraging of garbage collection when performing RAID transformation reduces overhead and wear without not negatively affecting system performance.

Abstract: A semiconductor device includes a plurality of input/output (I/O) pads; a serial input pad; a serial output pad; a plurality of interface circuits respectively corresponding to the I/O pads; and a plurality of option setting circuits respectively corresponding to the interface circuits, suitable for setting options of the respective interface circuits, wherein the serial input pad, the interface circuits, the option setting circuits, and the serial output pad configure a serial chain.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The data storage device supports zoned namespace. The controller is configured to maintain a zone timestamp table that includes a corresponding timestamp for each zone and add a timestamp to each garbage collection block of the memory device. The controller is further configured to scan a garbage collection block from a last physical block address (PBA) entry to a first PBA entry, determine a zone timestamp for the scanned PBA entry, and compare the zone timestamp to a timestamp of the garbage collection block. The controller is further configured to create and maintain a zone timestamp table and create and maintain a zone based defragmentation table.

Abstract: A method and apparatus for sustaining performance of a data storage device by predictively determining resource needs and executing processes to meet those needs before the resources are actually needed. According to certain embodiments, a controller collects commands coming from a host and provides these to a machine learning model such as a recurrent neural network (RNN). The RNN is trained using this data, and output of the trained model is used to predict future commands. As future commands are developed by the RNN, resource allocation processes such as garbage collection may be initiated prior to the actual need, during times when processing cycles in the data storage device are available. By operating the garbage collection when the device has available processing may mitigate transition to an urgent mode.

Abstract: Embodiments of the present subject matter provide a local profile management method, an embedded universal integrated circuit card, and a terminal. The embedded universal integrated circuit card (eUICC) includes a primary platform and at least one installed bundle. The primary platform is a hardware platform. Each bundle includes at least one profile and an operating system (OS). The primary platform includes a processing module, which is configured to: receive a first message sent by a local profile assistant (LPA), where the first message is an operation instruction entered by a user; and separately send a second message to at least one OS corresponding to the at least one bundle, where the second message is used by the at least one OS to perform a corresponding operation. Local management of profiles of different OSs is implemented by using the processing module disposed on the primary platform of the eUICC.

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

Abstract: A memory device includes a plurality of groups of memory blocks, each group including a plurality of blocks, and each block including a plurality of memory units. A memory controller for the memory device performs operations including maintaining a count of valid memory units in the group for each group and maintaining a count of valid memory units in each block of the memory device. The operations further include selecting a first group based on a count of valid memory units and the first group including a target plurality of blocks. The operations further include selecting a first target block from the target plurality of blocks, determining whether the first target block is to be erased, and erasing the first target block in response to determining that the first target block is to be erased.