Refresh Scheduling Patents (Class 711/106)
  • Patent number: 11222685
    Abstract: A memory controller interfaces with a dynamic random access memory (DRAM) over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: January 11, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Kedarnath Balakrishnan, Jing Wang, Guanhao Shen
  • Patent number: 11217296
    Abstract: Methods, systems, and devices for staggered refresh counters for a memory device are described. The memory device may include a set of memory dies each coupled with a common command and address (CA) bus and each including a respective refresh counter. In response to a refresh command received over the CA bus, each memory die may refresh a set of memory cells based on a value output by the respective refresh counter for the memory die. The refresh counters for at least two of the memory dies of the memory device may be offset such that they indicate different values when a refresh command is received over the CA bus, and thus at least two of the memory dies may refresh memory cells in different sections of their respective arrays. Offsets between refresh counters may be based on different fuse settings associated with the different memory dies.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Christopher G. Wieduwilt, James S. Rehmeyer
  • Patent number: 11182161
    Abstract: An information handling system includes a memory subsystem; a processor; and a link connecting the processor and memory subsystem, the processor having a memory controller to manage load instructions; a data cache to hold data for use by the processor; a load store unit to execute load instructions; an instruction fetch unit to fetch load instructions and a cache line utility tracker (CUT) table having a plurality of entries, each entry having a utility field to indicate the portions of a cache line of the load instruction that were used by the processor. The system configured to: determine whether the load instruction is in the CUT Table and in response determine from the CUT Table whether to request a partial cache line; and in response to the data not being in the data cache, transmit a memory request for a partial cache line.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Mohit Karve, Edmund Joseph Gieske, Naga P. Gorti
  • Patent number: 11182106
    Abstract: Various implementations described herein are directed to an integrated circuit having a cache with memory components that store data with multiple addresses. The integrated circuit may include a controller that communicates with the cache to provide directives to the cache. The integrated circuit may include a refresh circuit that interprets the directives received from the controller to generate interpretation information based on determining one or more particular addresses of the multiple addresses that no longer need refreshing. The refresh circuit may further employ the interpretation information to skip the need for refreshing the one or more particular addresses pointing to the memory components in the cache that no longer need refreshing.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: November 23, 2021
    Assignee: Arm Limited
    Inventor: Wei Wang
  • Patent number: 11158364
    Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/?1) at a faster rate than counts for more distant victim rows (e.g., +/?2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Jason M. Brown, Nathaniel J. Meier, Timothy B. Cowles, Jiyun Li
  • Patent number: 11152050
    Abstract: Apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Masaru Morohashi, Ryo Nagoshi, Yuan He, Yutaka Ito
  • Patent number: 11133051
    Abstract: A memory device may include a memory medium and a memory controller. The memory medium may be configured to perform a self-refresh operation and an auto-refresh operation in response to a self-refresh signal and an auto-refresh control signal, respectively. The memory controller may be configured to control the auto-refresh operation by transmitting the auto-refresh control signal to the memory medium. The memory medium includes a self-refresh controller. The self-refresh controller may be configured to control the self-refresh operation based on a self-refresh cycle varying according to an internal temperature of the memory medium and transmit the self-refresh signal to the memory controller. The memory controller may be configured to generate the auto-refresh control signal based on an auto-refresh cycle. The auto-refresh control signal may be determined by the self-refresh signal transmitted from the memory medium.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: September 28, 2021
    Assignee: SK hynix inc.
    Inventors: Youngjae Jin, Jin Wook Kim
  • Patent number: 11126497
    Abstract: Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: September 21, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-chu Oh, Moo-sung Kim, Young-sik Kim, Yong-jun Lee, Jeong-ho Lee
  • Patent number: 11094363
    Abstract: Devices and methods include organizing memory units of a memory device into a number of groups. The devices and methods also include self-refreshing each group of memory units on different corresponding sequential clock pulses of a self-refresh clock. Specifically, at least one of each group of memory units counts pulses of a self-refresh clock and invokes a self-refresh after every nth pulse of a cycle of pulses while not invoking a self-refresh on all other pulses of the cycle of pulses.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Vijayakrishna J. Vankayala
  • Patent number: 11087807
    Abstract: A memory controller may control a memory device. The memory device may be coupled to the memory controller through a channel. The memory controller may include an idle time monitor and a clock signal generator. The idle time monitor may output an idle time interval of the memory device. The idle time interval may be between an end time of a previous operation of the memory device and a start time of a current operation. The clock signal generator may generate a clock signal based on the idle time interval and output the clock signal to the memory device through the channel to perform a current operation.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: August 10, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyun Sub Kim, Ie Ryung Park, Dong Sop Lee
  • Patent number: 11043254
    Abstract: An apparatus may include multiple address registers each storing an address signal and multiple counter circuits each storing a count value corresponding to an associated one of the address registers. The apparatus may include a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Honoka Enomoto, Masaru Morohashi
  • Patent number: 11011219
    Abstract: The present disclosure provides a method for refreshing a memory array. The method includes the following steps: generating a plurality of target row records respectively for a plurality of banks; generating a plurality of row address records based on the plurality of target row records; and performing a row-hammer-refreshing process based on the plurality of row address records.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: May 18, 2021
    Assignee: Nanya Technology Corporation
    Inventors: Nung Yen, Yu-Hsiang Liu
  • Patent number: 10978132
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of skipped refresh operations on a memory. Memory cells of memories may need to periodically perform refresh operations. In some instances, auto-refresh operations may be periodically skipped when charge retention characteristics of the memory cells of the memory exceed the auto-refresh frequency. To reduce peak current draw during refresh operations, the skipped refresh operations may be staggered across different portions of the memory. In one example, the skipped refresh operation may be staggered in time among memory dies of the memory to limit a number of memory dies that are performing an auto-refresh operation to a maximum number. In another example, the skipped refresh operation may be staggered in time among memory banks of a single memory array to limit a number of memory banks that are performing an auto-refresh operation to a maximum number.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: James S. Rehmeyer, Nathaniel J. Meier, Joo-Sang Lee
  • Patent number: 10971206
    Abstract: A semiconductor memory device includes a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal; a second count circuit suitable for counting the second clock signal and generating a second count code signal; and a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: April 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Jae-Seung Lee, No-Geun Joo
  • Patent number: 10971207
    Abstract: A semiconductor memory device includes a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal; a second count circuit suitable for counting the second clock signal and generating a second count code signal; and a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: April 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Jae-Seung Lee, No-Geun Joo
  • Patent number: 10950318
    Abstract: Exemplary methods, apparatuses, and systems include a controller to manage memory proximity disturb. The controller identifies a first memory location in response to an access of a second memory location, the first memory location storing a first value. The controller updates a first disturb value by a first amount, the first disturb value representing a cumulative disturb effect on the first value in the first memory location by accesses to a first plurality of memory locations proximate to the first memory location, the first plurality of memory locations including the second memory location.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: March 16, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Jeffrey L. McVay, Samuel E. Bradshaw, Justin Eno
  • Patent number: 10943635
    Abstract: A common memory device shared by a first processor and a second processor is provided. The common memory device includes a memory cell array including a first memory region allocated for the first processor and a second memory region allocated for the second processor, a refresh masking information storage circuit configured to store refresh masking information indicating whether a refresh is performed on at least one of the first and second memory regions, and a refresh circuit configured to selectively perform the refresh on the first memory region and the second memory region according to the refresh masking information.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: March 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Hyun Kim, Ki Seok Oh
  • Patent number: 10943620
    Abstract: A data storage device is disclosed comprising a head actuated over a disk comprising a plurality of data tracks, including a first data track and a second data track. In connection with writing to at least part of the first data track, a quality metric is measured for at least part of the first data track. In connection with writing to at least part of the second data track, a refresh metric is updated based on the write to at least part of second data track and the quality metric measured for the first data track, and at least the first data track is refreshed based on the refresh metric.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: March 9, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Wayne H. Vinson, David R. Hall, Stephanie L. Aho, Zarko Popov
  • Patent number: 10943638
    Abstract: A semiconductor memory device may include a plurality of banks; a plurality of address storage circuits respectively corresponding to the plurality of banks, and suitable for storing refresh addresses of corresponding banks; an output control circuit suitable for, based on a refresh command signal and a test mode signal, generating an output clock and selectively outputting, as output data, a refresh address outputted from any one of the address storage circuits or bank data provided from the banks; an output buffer suitable for outputting the output data to a plurality of data input/output pads based on the output clock; and a strobe signal generation circuit suitable for generating a data strobe signal based on the output clock and outputting the data strobe signal through a data strobe pad.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: March 9, 2021
    Assignee: SK hynix Inc.
    Inventor: Yun-Gi Hong
  • Patent number: 10942658
    Abstract: A system and method for dynamically sizing system memory for a computing device using firmware and NVDIMMs is discussed. Additionally techniques for allocating between system memory and non-volatile storage on one or more NVDIMMs are discussed.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: March 9, 2021
    Assignee: Insyde Software Corp.
    Inventor: Timothy Andrew Lewis
  • Patent number: 10930335
    Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Debra M. Bell, Jeff A. McClain, Brian P. Callaway
  • Patent number: 10929225
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Ho-Young Song, Hyun-Joong Kim
  • Patent number: 10923177
    Abstract: A delay-locked loop circuit includes a delay line and a control unit. The delay line functions to delay an input signal to generate a first delay signal. The control unit receives the input signal, an access start signal and an access end signal, and functions to generate a control signal according to the input signal, the access start signal and the access end signal, wherein the control signal functions to control the delay line between two read operations.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: February 16, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chuan-Jen Chang
  • Patent number: 10916293
    Abstract: A target row refresh method includes: providing first table having M entries each capable of storing information of target row address; providing second table having K entries respectively capable of storing information of different/identical candidate row addresses; determining whether an input address in an input address register matches address information recorded in the first table; when not match, determining whether to update information of a target row latch by using the input address in the input address register according to a sample policy so as to determine whether to compare the input address with address information recorded in the second table to determine a target row address; and performing a target row refresh operation to refresh a memory device's row(s) adjacent to a target row corresponding to the target row address.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: February 9, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Ya-Chun Lai, Po-Hsun Wu, Jen-Shou Hsu
  • Patent number: 10885991
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for data rewrite operations. A non-volatile memory device comprises a non-volatile memory medium. A non-volatile memory device is configured to determine an error metric for a non-volatile memory medium in response to a read request for the non-volatile memory medium. A non-volatile memory device is configured to receive a refresh command from a controller over a bus. A non-volatile memory device is configured to rewrite data from a non-volatile memory medium during a predefined time period after receiving a refresh command in response to an error metric satisfying an error threshold.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: January 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Ward Parkinson, Martin Hassner, Nathan Franklin, Christopher Petti
  • Patent number: 10867655
    Abstract: Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuitry for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: December 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jonathan D. Harms, David Hulton, Jeremy Chritz
  • Patent number: 10860222
    Abstract: Provided are memory devices configured to perform row hammer handling operations, and memory systems including such memory devices. An example memory device may include a memory cell array including a plurality of memory cell rows; a row hammer handler that is configured to determine whether to perform a row hammer handling operation to refresh adjacent memory cell rows adjacent to a first row that is being intensively accessed from among the memory cell rows, resulting in a determination result; and a refresh manager configured to perform either a normal refresh operation for sequentially refreshing the memory cell rows or the row hammer handling operation, based on the determination result of the row hammer handler.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: December 8, 2020
    Inventors: Hoon Shin, Do-Yeon Kim, Ho-Young Song
  • Patent number: 10846246
    Abstract: A memory controller of a sender node issues an instruction of a trans-fabric instruction set of instructions to a receiver node across a communication fabric that supports memory semantic operations, to cause a given transaction to be performed at the receiver node in response to the issued instruction.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: November 24, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Melvin K. Benedict, Michael R. Krause, Mitchel E. Wright
  • Patent number: 10832755
    Abstract: A memory device includes a memory medium and a memory controller. The memory medium has a memory cell array and may be configured to generate a self-refresh signal, which varies based on an internal temperature of the memory medium, to control a self-refresh operation performed on the memory cell array. The memory controller may be configured to calculate an auto refresh cycle of an auto refresh control signal for controlling an auto-refresh operation of the memory medium based on the self-refresh signal.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: November 10, 2020
    Assignee: SK hynix Inc.
    Inventors: Youngjae Jin, Jin Wook Kim
  • Patent number: 10825502
    Abstract: A memory system includes: a memory device that includes a plurality of ranks; and a memory controller suitable for deciding a plurality of refresh cycles for respective combinations of the plurality of ranks and at least one program executed onto the memory device based on a performance diagnosis result of each of the ranks when the program is executed, and controlling a refresh operation to be performed onto the ranks based on the decided refresh cycles.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: November 3, 2020
    Assignee: SK hynix Inc.
    Inventor: Woong-Rae Kim
  • Patent number: 10824939
    Abstract: The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, an instruction module, a data transferring controller, a data writing scheduling unit, a buffer pool, a data reading scheduling unit and a computation module. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: November 3, 2020
    Assignee: XILINX, INC.
    Inventors: Shaoxia Fang, Lingzhi Sui, Qian Yu, Junbin Wang, Yi Shan
  • Patent number: 10818339
    Abstract: A semiconductor memory apparatus includes a plurality of memory banks and a refresh control circuit. The refresh control circuit, in each plurality of cycles, performs a refresh operation on at least one memory bank of the plurality of memory banks at a first refresh rate, and performs a refresh operation on the other memory banks of the plurality of memory banks at a second refresh rate. The refresh control circuit circulates the at least one memory bank on which the refresh operation is performed at the first refresh rate in each one or more cycles of the plurality of cycles.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: October 27, 2020
    Assignee: SK hynix Inc.
    Inventor: No Geun Joo
  • Patent number: 10818337
    Abstract: A semiconductor memory device is provided with a row control circuit, in order to dissolve a Row Hammer issue. The row control circuit is configured to: (A) latches one of (a) a target address upon issuing of an ACTIVE command to the semiconductor memory device, and (b) a row address of a victim cell in which data of a memory cell is affected by the target address, as a victim address by using a predetermined row address latch method; and then, (B) refreshes the victim cell having the victim address by a predetermined refresh method upon issuing of a REFRESH command.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: October 27, 2020
    Assignee: ZENTEL JAPAN CORPORATION
    Inventors: Bunsho Kuramori, Mineo Noguchi, Akihiro Hirota, Masahiro Ishihara, Mitsuru Yoneyama, Takashi Kubo, Masaru Haraguchi, Jun Setogawa, Hironori Iga
  • Patent number: 10811076
    Abstract: Disclosed herein are mechanisms and methods for reducing power consumed by various DRAM technologies (e.g., high-capacity DRAM and/or 3D DRAM) which may impact battery life of the platform. These mechanisms and methods may opportunistically reduce the power consumed by DRAM by inhibiting periodic refresh commands to memory ranks that are not in-use. Since these mechanisms and methods may be based on enhancements to memory controllers, they may accordingly be operating system (OS) agnostic.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Ramkumar Jayaraman, Krishnaprasad H, Kausik Ghosh
  • Patent number: 10795613
    Abstract: A convergence memory device includes a plurality of memories and a controller configured to control the plurality of memories. When an access request for accessing a storage region included in one or more of the memories is received, the controller determines whether the access request has been received a preset number of times or more within a refresh cycle. When the controller determines that the access request has been received the preset number of times or more, the controller postpones processing of the received access request.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: October 6, 2020
    Assignee: SK Hynix Inc.
    Inventor: Wan-Jun Roh
  • Patent number: 10790009
    Abstract: A memory device comprises a memory cell array, a plurality of sense amplifiers and a memory controller for controlling the plurality of sense amplifiers. The memory cell array includes a plurality of bit lines, where a bit line is coupled to a plurality of memory cells. A sense amplifier is coupled to a bit line and provides a sensing current to access data from one or more memory cells of the plurality of memory cells corresponding to the bit line. The memory controller performs operations comprising: during a pre-charging stage of a memory access cycle, providing, to a particular sense amplifier, a first voltage; and during a sensing stage of the memory access cycle, providing, to the particular sense amplifier, a second voltage, where the second voltage is a non-zero voltage that is lower than the first voltage.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: September 29, 2020
    Assignee: Macronix International Co., Ltd.
    Inventors: Chung-Kuang Chen, Han-Sung Chen
  • Patent number: 10725670
    Abstract: A system including a stack of two or more layers of volatile memory, such as layers of a 3D stacked DRAM memory, places data in the stack based on a temperature or a refresh rate. When a threshold is exceeded, data are moved from a first region to a second region in the stack, the second region having one or both of a second temperature lower than a first temperature of the first region or a second refresh rate lower than a first refresh rate of the first region.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: July 28, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Jagadish B. Kotra, Karthik Rao, Joseph L. Greathouse
  • Patent number: 10725695
    Abstract: A memory system includes: a memory device including a plurality of banks; and a memory controller suitable for: controlling an operation of the memory device, calculating row hammer information for each of the banks for each program having a command set requested from a host, and scheduling the banks based on the row hammer information for each of the banks corresponding to a specific program when the specific program is requested from the host.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventor: Woong-Rae Kim
  • Patent number: 10713156
    Abstract: Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Robert Walker, David A. Roberts
  • Patent number: 10706909
    Abstract: A system for refresh operations including multiple refresh activations, and a method and an apparatus therefore, are described. The system includes, for example, a memory array; a command address input circuit configured to provide a command for a per bank refresh operation or an all-bank refresh operation, a command control circuit configured to receive the command, and provide first and second internal control signals; a refresh control circuit configured to provide a first refresh control signal; and a row control circuit configured to provide a second refresh control signal. The provided first internal control signal is based on the provided command. For the per bank refresh operation, the provided second internal control signal is based on the second refresh control signal, and, for the all-bank refresh operation, the provided second internal control signal is based on the first internal control signal delayed by the command control circuit.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shinji Bessho, Toru Ishikawa, Takuya Nakanishi
  • Patent number: 10656856
    Abstract: In some embodiments, a data access apparatus includes a memory device including a plurality of addresses, an address mapping unit configured to map the addresses of the memory device with respective predetermined addresses such that they correspond to each other, a data division unit, a data mapping unit configured to map respective predetermined specific addresses in regions divided by the data division unit, and a control unit configured to control the data such that the data is stored in the addresses of the memory device mapped with the respective specific addresses in the regions divided by the data division unit.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: May 19, 2020
    Assignee: LSIS CO., LTD.
    Inventor: Tae-Bum Park
  • Patent number: 10650902
    Abstract: A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: May 12, 2020
    Assignee: Pure Storage, Inc.
    Inventors: Hari Kannan, Robert Lee, Yuhong Mao
  • Patent number: 10649690
    Abstract: In an example, there is disclosed a memory controller, including: a data buffer to drive a determinate value to a data bus to communicatively couple to a memory; and a register clock driver to: receive a memory initialization command from a processor; and incrementally step through a plurality of initialization addresses, sequentially driving each initialization address to an address bus to communicatively couple to the memory. There is also disclosed a computing device comprising the memory controller, and a method of initializing memory comprising incrementally stepping through a plurality of initialization addresses and sequentially writing a determinate value to each address.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Mohan J. Kumar, George Vergis, Sarathy Jayakumar
  • Patent number: 10607683
    Abstract: A semiconductor memory device and a memory system having the same are provided. The semiconductor memory device includes a memory cell array including plural memory cell array blocks, and a refresh controller configured to control the memory cell array blocks to perform a normal refresh operation and a hammer refresh operation. The refresh controller controls one or more third memory cell array blocks excluding a first memory cell array block and one or more second memory cell array blocks adjacent to the first memory cell array block to perform the hammer refresh operation while the normal refresh operation is performed on the first memory cell array block among the memory cell array blocks.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: March 31, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoon Shin, Do Yeon Kim, Ho Young Song
  • Patent number: 10572377
    Abstract: A method of operating a memory device may include receiving, during each phase of a row hammer refresh (RHR) interval, at least one row hammer address (RHA) of a content addressable memory (CAM). The method may further include storing, during each phase of the RHR interval, a received RHA of the at least one received RHA in an address register. Moreover, the method may include refreshing each stored RHA of the CAM via a RHR during the RHR interval. Semiconductor devices and an electronic system are also described.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yu Zhang, Jun Wu, Yuan He
  • Patent number: 10553300
    Abstract: A system for detecting an address decoding error of a semiconductor device, includes: decoding an original address, with an address decoder of the semiconductor device, to form a corresponding decoded address; recoding the decoded address, with an encoder of the semiconductor device, to form a recoded address; making a comparison, with a comparator of the semiconductor device, of the recoded address and the original address; and detecting an address decoding error based on the comparison.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Ching-Wei Wu, Chun-Hao Chang
  • Patent number: 10545692
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for memory maintenance operations. A non-volatile memory device comprises a non-volatile memory medium. A non-volatile memory device is configured to receive a refresh command from a controller over a bus. A non-volatile memory device is configured to perform one or more maintenance operations on a non-volatile memory medium during a predefined period of time after receiving a refresh command.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: January 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Nathan Franklin, Ward Parkinson
  • Patent number: 10535393
    Abstract: An electronic device including a memory functional block having multiple ranks of memory and a memory controller functional block coupled to the memory. The memory controller includes refresh logic that detects, based on buffered memory accesses for each rank of memory of the ranks of memory, two or more ranks of memory for which a refresh is to be performed during a refresh interval. Based at least in part on one or more properties of buffered memory accesses for the two or more ranks of memory, the refresh logic determines a refresh order for performing refreshes for the two or more ranks of memory during the refresh interval. The memory controller then performs, in the refresh order, refreshes for the two or more ranks of memory during the refresh interval.
    Type: Grant
    Filed: July 21, 2018
    Date of Patent: January 14, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Kedarnath Balakrishnan
  • Patent number: 10497447
    Abstract: A memory device includes: memory cells of first and second planes; and a control circuit suitable for performing multiple read operations on the memory cells in response to a read command. The multiple read operations may include a first read operation which is performed on the memory cells of the first plane in a first read period and a second read operation which is performed on the memory cells of the second plane in a second read period.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: December 3, 2019
    Assignee: SK hynix Inc.
    Inventor: Kye-Wan Shin
  • Patent number: 10431323
    Abstract: A memory system includes a calibration engine, a memory, and a memory controller coupled to the memory by a channel used to transmit a plurality of commands from the memory controller to the memory. The memory controller estimates a total energy consumed based on the first plurality of commands in a first sampling period and determines a first temperature change of the memory based on the first total energy consumed. The memory controller transmits an impedance calibration command to the calibration engine if the first temperature change of the memory exceeds a first threshold. The calibration engine changes an impedance of an I/O terminal of the memory based on the calibration command.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: October 1, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Jason Griffin