Refresh Scheduling Patents (Class 711/106)
  • Patent number: 10321209
    Abstract: An improved data packet design that can be used in a variety of data communication standards used in smart meter systems is disclosed. In an embodiment a smart meter system that comprises of a local server, a coordinator and a plurality of smart meters in the many-to-one data communication system configuration. The smart meter uses a variety of types of radio frequency data packets. The data packets contain the commands, parameters, and data for system control and data transmission. The data packet designs are disclosed for a route discovery command, a get parameter command, a set parameter command, a get data command, a reset command, a relay command, a start command, and a calibration command that are used in the smart meter system.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: June 11, 2019
    Assignee: International Technological University
    Inventor: Karl L. Wang
  • Patent number: 10304515
    Abstract: The present disclosure includes apparatuses and methods related to refresh circuitry. An example apparatus can include a memory array including a main portion and a redundant portion. The apparatus can include refresh circuitry configured to, responsive to a determination of a hammering event, refresh at least a portion of the redundant portion.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Richard N. Hedden
  • Patent number: 10296650
    Abstract: A method of indexing documents to support frequent field updates without reindexing may include receiving, from an indexing application, first fields from a document to be indexed. The method may also include receiving, from the indexing application, second fields from the document to be indexed. The method may additionally include writing the first fields to an index file associated with the indexing application. The method may further include writing the second fields to a datastore that is external to the indexing application.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: May 21, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Aditya Mani Tripathi, Hasari Tosun, Anthony Arnone, Shane Strasser, Karthikeyan Nagarajan
  • Patent number: 10269445
    Abstract: A memory device includes a memory array, an error correction code (ECC) circuit, and a control circuit. The memory array includes plural memory rows and stores a plurality of data. The control circuit is configured to enter the memory device into a power saving mode with a first refresh rate to refresh the memory array, to control the ECC circuit to generate a first ECC according to first data during refreshing the memory array by the first refresh rate, to reduce the first refresh rate to a second refresh rate, to control the ECC circuit to determine whether an error exists in the first data during refreshing the memory array by the second refresh rate. If the error exists in the first data, the control circuit is further configured to control the ECC circuit to correct the first data.
    Type: Grant
    Filed: October 22, 2017
    Date of Patent: April 23, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10268585
    Abstract: An apparatus having a memory controller is described. The memory controller includes prefetch circuitry to prefetch, from a memory, data having a same row address in response to the memory controller's servicing of its request stream being stalled because of a timing constraint that prevents a change in row address. The memory controller also includes a cache to cache the prefetched data. The memory controller also includes circuitry to compare addresses of read requests in the memory controller's request stream against respective addresses of the prefetched data in the cache and to service those of the requests in the memory controller's request stream having a matching address with corresponding ones of the prefetched data in the cache.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Ashish Ranjan, Vivek Kozhikkottu
  • Patent number: 10248343
    Abstract: Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Jason B. Akers, Knut S. Grimsrud, Robert J. Royer, Jr., Richard P. Mangold, Sanjeev N. Trika
  • Patent number: 10225168
    Abstract: An exemplary interface apparatus includes: a header generator which receives, in a first order, a plurality of request headers extracted from a plurality of request packets, generates response headers associated with the request headers, and then stores the response headers so that the response headers are read in the first order; and a header order controller which controls the header generator so that if the plurality of request data have been transmitted to the memory in a second order, the respective response headers are read in the second order.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: March 5, 2019
    Assignee: Panasonic Intellectual Property Management Co. Ltd
    Inventors: Tomoki Ishii, Takao Yamaguchi, Atsushi Yoshida, Satoru Tokutsu, Yuuki Soga
  • Patent number: 10210925
    Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: February 19, 2019
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, John B. Halbert, Christopher P. Mozak, Theodore Z. Schoenborn, Zvika Greenfield
  • Patent number: 10198221
    Abstract: A method of scrubbing errors from a semiconductor memory device including a memory cell array and an error correction circuit, can be provided by accessing a page of the memory cell array to provide a data that includes sub units that are separately writable to the page of memory and to provide parity data configured to detect and correct a bit error in the data and selectively enabling write-back of a selected sub unit of the data responsive to determining that the selected sub unit of data includes a correctable error upon access as part of an error scrubbing operation.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: February 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Uhn Cha, Hoi-Ju Chung, Uk-Song Kang
  • Patent number: 10198494
    Abstract: There is provided a method of using a central computer system, which has a central relational database, systematically to refresh a distributed database that is distributed over a plurality of distributed computer systems and that includes distributed database fields that are for storing contingent values that are contingent on sporadic interactions between terminal computer systems and the distributed computer systems and that are affiliated with central database fields in the central relational database. The method includes recurrently, at receiving times, receiving contingent values of the distributed database fields from the distributed computer systems. The received contingent values are stored, in the central relational database, in succession with previously received and stored contingent values of the distributed database fields, so that, for each distributed computer system an associated series of successive contingent values is built.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: February 5, 2019
    Assignee: Allotz.com Limited
    Inventors: Martin McConnachie, Helen Johnson, Geoffrey Toogood, Daniel Paul Ruul
  • Patent number: 10199079
    Abstract: A semiconductor memory device may include a memory cell array area, a peripheral area, and an interface area. The memory cell array area may include at least one memory plane. The peripheral area may be formed adjacent to one side of the memory cell array area. The interface area may be formed adjacent to one side of the peripheral area and include a plurality of data input/output pads. The peripheral area may include a data path logic area formed between the memory cell array area and the interface area. The interface area may include at least one SerDes (serializer/deserializer) area configured to transmit, to the memory cell array area, data inputted through the data input/output pads, or output, through the data input/output pads, data received from the memory cell array.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: February 5, 2019
    Assignee: SK hynix Inc.
    Inventor: Myung Jin Kim
  • Patent number: 10141034
    Abstract: Providing for an electronic memory apparatus having high-density, non-volatile memory arrays in conjunction with a high-speed communication interface is disclosed herein. In some embodiments, the electronic memory apparatus can include multiple banks of two-terminal memory, communicatively connected to a modified dynamic random access memory bus and configured to operate according to a modified communication protocol. In one or more embodiments, the high-speed communication interface can comprise more than ten command and address pins to identify individual memory banks (or subsets of memory banks) of the multiple banks of memory, to facilitate bank-specific addressing for memory array operations. In some embodiments, the electronic memory can facilitate status information for subsets of memory banks to facilitate informed array operations, increasing duty cycle of the memory device.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: November 27, 2018
    Assignee: CROSSBAR, INC.
    Inventor: Cliff Zitlaw
  • Patent number: 10133645
    Abstract: Data is programmed in a respective block of non-volatile three dimensional memory. The block contains a plurality of rows of subblocks, each row having S subblocks. Programming data in the respective block includes successively programming data in individual rows of the respective block. Programming data in each row is completed prior to programming data in a next row. Programming data in a row includes successively programming data in individual subblocks of the row, in a predefined order. The programming of data in each subblock is completed prior to programming data in a next subblock. While programming data in each individual subblock, a number of XOR signatures, sufficient in number to enable recovery from a short circuit that disables two or three word lines, are generated in volatile memory, and then copied to non-volatile memory prior to programming data in a next subblock in the respective block.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: November 20, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Ofer Shapira, Idan Alrod, Eran Sharon
  • Patent number: 10114829
    Abstract: A technique for storing data in a data storage system includes receiving, from a host, a request specifying a set of data to be written to a first file system, the first file system realized as a file within a second file system. A first log entry is created for the set of data in a first data log, which logs data to be written to the first file system, and a second log entry is created for the set of data in a second data log, which logs data to be written to the second file system. The first log entry provides a reference to the second log entry. The technique further includes storing the data in the cache page and acknowledging the host.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 30, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Jean-Pierre Bono, Philippe Armangau
  • Patent number: 10108365
    Abstract: A memory area is protected from rowhammer attacks by placing an extra sacrificial row at the top and the bottom of the memory addresses defining the area to be protected. The sacrificial rows of memory are written with a known bit pattern that may be read periodically to detect any rowhammer attacks that may be in progress.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: October 23, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Clive D. Bittlestone
  • Patent number: 10083737
    Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, John B. Halbert
  • Patent number: 10079051
    Abstract: There is provided an information processing apparatus including a region detection unit configured to detect a region that satisfies a predetermined condition among a plurality of regions included in a data storage apparatus, and a refresh processing unit configured to skip refresh with respect to the region that satisfies the predetermined condition when performing refresh processing on the plurality of regions.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: September 18, 2018
    Assignee: SONY CORPORATION
    Inventors: Kenji Fudono, Shusuke Saeki, Atsushi Ochiai, Kazumi Sato
  • Patent number: 10049716
    Abstract: An apparatus and system associated with memory are disclosed herein. In various embodiments, an apparatus may include first circuitry to determine a number of queued pending refresh requests for a memory bank based on a comparison of a count from a refresh-request counter to a count from a refresh-address counter; and second circuitry to set a refresh flag in response to a determination that the number of queued pending refresh requests exceeds a predetermined number. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: August 14, 2018
    Assignee: INTELLECTUAL VENTURES I LLC
    Inventor: Robert J. Proebsting
  • Patent number: 10014046
    Abstract: Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Jim Kardach, Nikos Kaburlasos
  • Patent number: 9989948
    Abstract: Methods and systems for transfer-switch controller backup and transfer-switch controller operation are provided. An example backup apparatus includes a memory configured to store transfer-switch data related to a first transfer-switch controller, wherein the first transfer switch-controller is a controller for a given transfer switch. The apparatus is capable of interfacing with a communication interface of the first transfer-switch controller. The apparatus is further capable of being removed from the communication interface of the first transfer-switch controller and thereafter interfacing with a communication interface of a second transfer-switch controller, wherein the second transfer-switch controller is a replacement controller for the given transfer switch.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: June 5, 2018
    Assignee: ASCO Power Technologies, L.P.
    Inventors: Mario Ibrahim, Robert Siciliano, John Hayes
  • Patent number: 9990163
    Abstract: A method of scrubbing errors from a semiconductor memory device including a memory cell array and an error correction circuit, can be provided by accessing a page of the memory cell array to provide a data that includes sub units that are separately writable to the page of memory and to provide parity data configured to detect and correct a bit error in the data and selectively enabling write-back of a selected sub unit of the data responsive to determining that the selected sub unit of data includes a correctable error upon access as part of an error scrubbing operation.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: June 5, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Uhn Cha, Hoi-Ju Chung, Uk-Song Kang
  • Patent number: 9972377
    Abstract: A refresh controller of a memory device may include a timing controller, a refresh counter and an address generator. The timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal that is activated periodically. The refresh counter generates a counter refresh address signal in response to the counter refresh signal, such that the counter refresh address signal represents a row address, the refresh counter being configured sequentially change the counter refresh address signal. The address generator generates a hammer refresh address signal in response to the hammer refresh signal, the hammer refresh address signal representing an address of a row of the memory device that is physically adjacent to a row of the memory device corresponding to a hammer address that is accessed intensively.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: May 15, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Min Oh, Ho-Young Song
  • Patent number: 9953696
    Abstract: A semiconductor memory device may include: a memory cell region including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines; and a refresh control block suitable for performing a first refresh operation onto the plurality of the word lines in response to a refresh signal, counting the number of active signals that are inputted between at least two neighboring refresh signals and when the counted number of the active signals is equal to or greater than a reference number, performing a second refresh operation onto a word line corresponding to a target address.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: April 24, 2018
    Assignee: SK Hynix Inc.
    Inventor: Jung-Hyun Kim
  • Patent number: 9916887
    Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a command/address signal. The second semiconductor device extracts an active signal, a pre-charge signal, and addresses from the command/address signal, performs an active operation on a memory cell corresponding to the addresses, and performs a refresh operation on the memory cell corresponding to counting signals generated by counting a number of pulses in a refresh signal.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: March 13, 2018
    Assignee: SK hynix Inc.
    Inventor: Min Su Park
  • Patent number: 9911484
    Abstract: Various embodiments comprise methods and apparatuses for selecting a randomly-chosen seed row from among a stream of available data in a memory system. A refresh operation is then performed on at least one selected row of memory in the memory system based on the randomly-chosen seed row. Additional apparatuses and methods are described.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: March 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Donald M. Morgan, John D. Porter
  • Patent number: 9910767
    Abstract: On-chip instruction RAM is leveraged as an extension of on-chip data RAM during normal use of a modified Harvard Architecture processor. Unused space in an instruction RAM is detected in a modified Harvard Architecture processor. During operation of the processor this unused space is used to load and store data normally loaded and stored in an on-chip data RAM. A performance penalty associated with swapping out to external memory is reduced. The type of data stored in the unused portion of the instruction RAM may be selected to optimize performance. In one implementation, the unused space in the instruction RAM is used to load and store only a single type of data, such as heap, stack, initialized or uninitialized data.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: March 6, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Gordon Waidhofer, Christopher Delaney, Leland Thompson
  • Patent number: 9880900
    Abstract: In one embodiment, a method for updating a DRAM memory array is disclosed. The method comprises: a) transitioning the DRAM memory array from an idle state to a self-refresh state after a period of inactivity; b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry; and c) during the refresh, performing an Error Correction Code (ECC) scrub operation of selected bits in an activated row of the DRAM memory array.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: January 30, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: David Reed, Alok Gupta
  • Patent number: 9824754
    Abstract: Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Sreenivas Mandava, Brian S. Morris, Suneeta Sah, Roy M. Stevens, Ted Rossin, Mathew W. Stefaniw, John H. Crawford
  • Patent number: 9825613
    Abstract: A resistor calibration system includes a reference resistor, a first control circuit, a second control circuit, a comparator, a multiplexer and a de-multiplexer. The first control circuit calibrates a first resistor and a duplicated first resistor. The second control circuit calibrates a second resistor. The comparator includes a first input terminal receiving a reference voltage, a second input terminal and an output terminal. The multiplexer includes a first input terminal coupled to the reference resistor and the first resistor, a second input terminal coupled to the duplicated first resistor and the second resistor, and an output terminal coupled to the second input terminal of the comparator. The de-multiplexer includes an input terminal coupled to the output terminal of the comparator, a first output terminal coupled to the first control circuit, and a second output terminal coupled to the second control circuit.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: November 21, 2017
    Assignee: NOVATEK Microelectronics Corp.
    Inventor: Po-Yao Ko
  • Patent number: 9792963
    Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Prashant S. Damle, Frank T. Hady, Paul D. Ruby, Kiran Pangal, Sowmiya Jayachandran
  • Patent number: 9767882
    Abstract: A method of refreshing a memory device includes performing normal refresh operations on memory cell rows in response to a refresh command and performing self-refresh operations on the memory cell rows according to a refresh clock signal in response during a self-refresh mode of the memory device between a self-refresh enter command and a self-refresh exit command. The refresh clock signal has a first self-refresh cycle before the self-refresh begins and a second self-refresh cycle, which may be longer than the first self-refresh cycle, after the self-refresh begins. In some examples, no self-refresh may be performed by the memory device during a self-refresh mode.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: September 19, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-jun Shin, Tae-young Oh, Kwang-il Park
  • Patent number: 9761298
    Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: September 12, 2017
    Assignee: Intel Corporation
    Inventors: John B. Halbert, Kuljit S. Bains
  • Patent number: 9753516
    Abstract: According to one embodiment of the invention, an integrated circuit device comprises one or more processor cores and a control unit coupled to the processor core(s). The control unit is adapted to control an operating frequency of at least one processor core based on an estimated activity level in lieu of a power level. The estimated activity level differing from an estimated power level by being independent of leakage power and voltage characteristics particular to that integrated circuit device.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Ryan D. Wells, Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Gary A. Andrew
  • Patent number: 9710505
    Abstract: Described herein are system and methods for mitigating index contention issues in databases. The database server may generate additional storage locations to prevent overloading one or more current storage locations. A variety of database conditions may be used to trigger an increase or decrease in storage locations. In one embodiment, more storage locations may be generated when the amount of data records waiting to be written at a storage location exceeds or equals a threshold amount. Likewise, the database server may reduce the amount of current storage locations when the amount of data records is less than a threshold amount. The record identifiers may incorporate a location reference for their designated storage location. The reference may be a string that includes numbers, letters, or a combination thereof.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: July 18, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Grant Alexander Macdonald McAlister, Chelsea C. Krueger, Dallas L. Willett, Michael J. Russo, Ramnath R. Iyer
  • Patent number: 9691466
    Abstract: A memory device may include: a target address generator suitable for storing one or more addresses for each time a refresh command is skipped, and for generating one or more target addresses for each of the stored addresses during a burst refresh operation; and a refresh controller suitable for refreshing a word line selected among a plurality of word lines of a memory bank based on the generated one or more target addresses during a target refresh operation.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: June 27, 2017
    Assignee: SK Hynix Inc.
    Inventor: Chang-Hyun Kim
  • Patent number: 9691504
    Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: June 27, 2017
    Assignee: Rambus Inc.
    Inventors: Ely Tsern, Frederick A Ware, Suresh Rajan, Thomas Vogelsang
  • Patent number: 9691442
    Abstract: In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: June 27, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Dietmar Gogl
  • Patent number: 9685218
    Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: June 20, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Soo Sohn, Chul-Woo Park, Si-Hong Kim, Kwang-Il Park, Jae-Youn Youn
  • Patent number: 9679632
    Abstract: The present invention discloses an erasure circuitry, a method for erasing a volatile memory, a volatile memory and a processing unit coupled with an operating system, where the erasure circuitry is adapted to erase the volatile memory at occurrence of a predefined event. The erasure circuitry includes a control unit for initiating a dummy operation to randomize data of one or more memory cells at the occurrence of a predefined event. The control unit is adapted to receive the addresses of the memory blocks from a processing unit via an operating system.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: June 13, 2017
    Assignee: Khalifa University of Science and Technology
    Inventors: Baker Shehadah Mohammad, Khaled Hamed Salah, Mahmoud Abdullah Al-Qutayri
  • Patent number: 9658678
    Abstract: A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventor: Kenneth D. Shoemaker
  • Patent number: 9639495
    Abstract: A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: May 2, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Glenn A. Dearth, Gerry Talbot, Anwar Kashem, Edoardo Prete, Brian Amick
  • Patent number: 9640242
    Abstract: Various embodiments of methods and systems for temperature compensated memory refresh (“TCMR”) of a dynamic random access memory (“DRAM”) component are disclosed. Embodiments of the solution leverage a memory refresh module located within a memory subsystem to apply a refresh power supply received from a source on the SoC. Advantageously, even though the refresh power supply is received from a source on the SoC according to a certain delivery rate that may not be optimal for each and every bank in the DRAM component, embodiments of the solution are able to apply an effective refresh power supply rate to each bank according to its optimal cycle.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: May 2, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Haw-Jing Lo, Dexter Tamio Chun
  • Patent number: 9619163
    Abstract: An apparatus, method, and computer program for maintaining access times in a data processing system, wherein the data processing system comprises a plurality of storage devices, the apparatus including: a receive component, for receiving a command or an availability message, wherein an availability message indicates whether the storage device is available; an evaluate component for evaluating a plurality of first relationships between the storage devices and a plurality of first values, wherein each of the first values indicates whether a related storage device is a redundant; a send component, for sending a power message to one or more of the storage devices; and an update component for updating a second relationship between the redundant storage device and a plurality of second values, wherein each of the second values indicates whether a related redundant storage device is available.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: April 11, 2017
    Assignee: International Business Machines Corporation
    Inventor: Paul Hooton
  • Patent number: 9583172
    Abstract: A self-refresh control device may be provided. The self-refresh control device may include a refresh signal output circuit configured to generate self-refresh signals with an oscillator and provide a refresh signal. The self-refresh control device may begin a self-refresh mode in response to a clock enable signal and a self-refresh signal within a self-refresh entry period, and may prevent performance of a new self-refresh operation by delaying an additional self-refresh signal until after the self-refresh entry period has ended.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: February 28, 2017
    Assignee: SK HYNIX INC.
    Inventors: Tae Sik Yun, Dong Beom Lee
  • Patent number: 9564201
    Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: February 7, 2017
    Assignee: INTEL CORPORATION
    Inventors: John B. Halbert, Kuljit S. Bains
  • Patent number: 9564186
    Abstract: Aspects of the disclosure provide an integrated circuit that includes a first memory controller, a second memory controller and at least a functional circuit coupled to the second memory controller. The first memory controller is configured to control memory access to a first memory. The second memory controller is configured to control memory access to a second memory that is able to be turned on/off. The functional circuit is configured to operate based on the second memory. The second memory controller is configured to cause the second memory to be turned on when an application requires an operation of the functional circuit.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: February 7, 2017
    Assignee: Marvell International Ltd.
    Inventors: Zhou Zhu, Xinyan Wu, Xiaofan Tian, Jiaquan Su
  • Patent number: 9564206
    Abstract: Embodiments of the present invention relate to a latch circuit (L20) which latches a data mask signal (DM) in response to a one-shot signal (NS), and changes the data mask signal (DM) to an active level in response to an error signal (ERR), which indicates that an error is present in write data (DQ), being at an active level; a buffer circuit (BF2) which outputs the data mask signal (DM) that has been latched by the latch circuit (L20), said data mask signal (DM) being output in response to a write clock signal (WCLK2); and a main amplifier (80) which outputs the write data (DQ) to an internal circuit on the condition that the data mask signal (DM) which has been output from the buffer circuit (BF2) is at an inactive level. The present invention can prevent the writing of erroneous write data, and is capable of preventing increased chip surface area.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: February 7, 2017
    Assignee: Longitude Semiconductor S.A.R.L.
    Inventor: Taihei Shido
  • Patent number: 9554358
    Abstract: Methods and apparatus enabling a wireless network to optimize paging channel operation, based on mobile device context information. In one embodiment, the wireless network is a cellular network (e.g., LTE-Advanced), and both base stations and cellular user devices dynamically exchange and maintain a paging agreement. The paging agreement limits the paging channel operation, thereby minimizing unnecessary scanning and usage of irrelevant radio resources. Such paging mechanisms are limited to the air interface between the base station and the mobile device, and are compatible with existing legacy devices and network entities. Networks with appropriately enabled user devices may improve their resource utilization. Base stations may advantageously reclaim freed-up cellular resources to support other services.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: January 24, 2017
    Assignee: APPLE INC.
    Inventors: Maik Bienas, Hyung-Nam Choi
  • Patent number: 9496037
    Abstract: A memory circuit includes: a bistable circuit (30) that writes data; nonvolatile elements (MTJ1, MTJ2) that store the data written in the bistable circuit into the nonvolataole element in a nonvolatile manner, and restore the data stored in a nonvolatile manner into the bistable circuit; and a determining unit (50) that does not store the data written in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is the same as the data in the nonvolatile elements, but stores the data in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is not the same as the data in the nonvolatile elements.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: November 15, 2016
    Assignee: Japan Science and Technology Agency
    Inventors: Shuichiro Yamamoto, Yusuke Shuto, Satoshi Sugahara
  • Patent number: 9490848
    Abstract: It is an object of the invention to provide a memory architecture that can handle data interleaving efficiently. This and other objects are achieved by the system according to the invention. The data handling system, is configured for receiving at an input a plurality of commands. The system comprises: a plurality of memory banks; a distributor connected to the input and having a plurality of distributor outputs. Each specific one of the plurality of memory banks (106) is connected to a specific one of the plurality of distributor outputs. The distributor comprises a permutator for designating for each specific command a specific distributor output. The distributor distributes the specific command to the specific designated distributor output. The permutator has a control input and the designating is reconfigurable under the control of reconfiguration data received at the control input.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: November 8, 2016
    Assignee: NXP B.V.
    Inventors: Erik Rijshouwer, Cornelis Hermanus van Berkel