Abstract: A device manages the storage of data in at least one storage device of a first type and in a storage device of a second type, the at least one storage device of the first type being physically distinct from the storage device of the second type. The device partitions data to be stored into blocks of data, determines redundancies generated by an error detection code for each block of data, stores blocks of data in the at least one storage device of the first type, the storage device(s) of the first type being compliant with an avionic quality assurance level of a given quality level, and stores redundancies in the storage device of the second type, the storage device of the second type being compliant with an avionic quality assurance level that is higher than the avionic quality assurance level of the storage device(s) of first type.

Abstract: A method of saving the power of a portable electronic device is provided. The method includes starting a power saving mode, identifying an application executed in a foreground, and changing operation settings of the portable electronic device for the identified application.

Abstract: Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice.

Abstract: A resource manager directs cache operating states of virtual machines based on cache resource latency and by distinguishing between latencies in flash memory and latencies in network communications and by distinguishing between executing read commands and executing different types of write commands. As a result, the resource manager can downgrade the cache operating state of the virtual machines differently based on the type of latency being experienced and the type of command being performed. The resource manager can upgrade and/or reset the cache operating state of the virtual machines, when appropriate, and can give priority to some virtual machines over other virtual machines when operating in a downgraded cache operating state.

Abstract: The present invention discloses an interface transmission method including: enabling a first command string including a first sub-command to be transmitted to a storage device from a processing device during a first period; enabling a second command string including a second sub-command to be transmitted to the storage device from the processing device during a second period, wherein the first sub-command and the second sub-command constitute a command; when the command is a write command, enabling a write data string to be transmitted to the storage device from the processing device during a third period, wherein the write data string includes write data; and when the command is a read command, enabling a read data string to be transmitted to the processing device from the storage device during the third period, wherein the read data string includes read data.

Abstract: Compression of address bits within a cache coherent subsystem of a chip is performed, enabling a cache coherent subsystem to avoid transmitting, storing, and operating upon unnecessary address information. Compression is performed according to any appropriate lossless algorithm, such as discarding of bits or code book lookup. The algorithm may be chosen according to constraints on logic delay and silicon area. An algorithm for minimum area would use a number of bits equal to the rounded up binary logarithm of the sum of all addresses of all memory regions. A configuration tool generates a logic description of the compression algorithm. The algorithm may be chosen automatically by the configuration tool. Decompression may be performed on addresses exiting the coherent subsystem.

Abstract: A data processing device includes: a processing block which is connected to a common bus and which processes a plurality of data, which is inputted simultaneously, in parallel; a memory which is consisted of address space which has a plurality of banks; and a common bus arbitration unit which arbitrates a request for access to the memory outputted from the processing block, and controls exchange of data via the common bus between the processing block whose access request has been accepted and the memory. The processing block includes a data transfer control device which changes an order of access to the bank of the memory corresponding to the respective data, unifies the respective data into an exchange data, and exchanges the exchange data with the memory when the processing block performs exchanging of the data to be processed in parallel with the memory via the common bus.

Abstract: Embodiments of a system that reduces power consumption by power-gating media decoders are described. During operation of the system, a decoder circuit receives encoded audio data and outputs corresponding decoded audio data to a memory, which is electrically coupled to the decoder circuit. Moreover, control logic, which is electrically coupled to the memory and the decoder circuit, provides commands to the memory and the decoder circuit that selectively disable at least a portion of the memory based on an amount of decoded audio data in the memory.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory circuit and a first controller. The first memory circuit includes a register in which a read page size is stored, and a memory cell array. The first controller is configured to access the first memory circuit by the page size stored in the register, in one of an open page policy and closed page policy.

Abstract: A memory system includes a high-bandwidth memory device, the high-bandwidth memory device having a relatively high operation bandwidth, the high-bandwidth memory device having a plurality of access channels. A low-bandwidth memory device has a relatively low operation bandwidth relative to the high-bandwidth memory device, the low-bandwidth memory device having one or more access channels. An interleaving unit performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and an access channel of the one or more access channels of the low-bandwidth memory device.

Abstract: According to one embodiment, there is provided a memory system including a volatile memory and a controller. The volatile memory has 1st to Kth memory banks (K is a natural number equal to or larger than 2) that are kept in a power-on state and (K+1)th to Nthmemory banks (N is a natural number larger than K) whose power state is changed. The power state is the power-on state or a power-down state. The controller performs wake-up operation for the (K+1)th to Nth memory banks in parallel with access operation to the 1st to Kth memory banks. The wake-up operation changes the power state from the power-down state to the power-on state.

Abstract: A data processing device includes: a processing block which is connected to a common bus and which processes a plurality of data, which is inputted simultaneously, in parallel; a memory which is consisted of address space which has a plurality of banks; and a common bus arbitration unit which arbitrates a request for access to the memory outputted from the processing block, and controls exchange of data via the common bus between the processing block whose access request has been accepted and the memory. The processing block includes a data transfer control device which changes an order of access to the bank of the memory corresponding to the respective data, unifies the respective data into an exchange data, and exchanges the exchange data with the memory when the processing block performs exchanging of the data to be processed in parallel with the memory via the common bus.

Abstract: An apparatus having a first circuit and a second circuit. The first circuit may be configured to buffer an input signal received as a single-ended signal from a data bus connected between a memory channel and a memory controller. The second circuit may be configured to condition the input signal relative to a reference voltage to generate a differential signal. The reference voltage may be isolated from the second circuit in response to a transition from a power down condition to a power on condition.

Abstract: The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel.

Abstract: Subject matter disclosed herein relates to management of a memory device.

Abstract: A memory physical layer interface circuit electrically connected between a memory controller and a memory device is provided. The memory physical layer interface circuit includes a dock generation module and first-in-first-out (FIFO) modules. The clock generation module generates a reference clock signal and output related clock signals. The reference clock signal is transmitted to the memory device. Each of the FIFO modules writes the input information therein transmitted by the memory controller according to a write-related clock signal and retrieves the input information therefrom according to one of the output related clock signals to generate an output signal. The output signal is transmitted to the memory device to operate the memory device. The write-related clock signal is generated by dividing a frequency of one of the output related clock signals.

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

Abstract: A computer-implemented method includes identifying two or more memory locations and referencing, by a memory access request, the two or more memory locations. The memory access request is a single action pursuant to a memory protocol. The computer-implemented method further includes sending the memory access request from one or more processors to a node and fetching, by the node, data content from each of the two or more memory locations. The computer-implemented method further includes packaging, by the node, the data content from each of the two or more memory locations into a memory package, and returning the memory package from the node to the one or more processors. A corresponding computer program product and computer system are also disclosed.

Abstract: According to an exemplary embodiment, a method of forming vertical structures is provided. The method includes the following operations: providing a substrate; forming a first oxide layer over the substrate; forming a first dummy layer over the first oxide layer; etching the first oxide layer and the first dummy layer to form a recess; forming a second dummy layer in the recess (and further performing CMP on the second dummy layer and stop on the first dummy layer); removing the first dummy layer; removing the first oxide layer; and etching the substrate to form the vertical structure. According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes: a substrate; an STI embedded in the substrate; and a vertical transistor having a source substantially aligned with the STI.

Abstract: A method for making memory more reliable involves accessing data stored in a removable storage device by translating a logical memory address provided by a host digital device to a physical memory address in the device. A logical memory address is received from the host digital device. The logical memory address corresponds to a location of data stored on the removable storage device. A physical memory address corresponding to the local address is determined by accessing a lookup table corresponding to the logical zone.

Abstract: Systems and methods may provide for identifying an object in a managed runtime environment and determining an age of the object at a software level of the managed runtime environment. Additionally, the object may be selectively allocated in one of a dynamic random access memory (DRAM) or a non-volatile random access memory (NVRAM) based at least in part on the age of the object. In one example, the data type of the object is also determined, wherein the object is selectively allocated further based on the data type.

Abstract: A computer-implemented method includes identifying two or more memory locations and referencing, by a memory access request, the two or more memory locations. The memory access request is a single action pursuant to a memory protocol. The computer-implemented method further includes sending the memory access request from one or more processors to a node and fetching, by the node, data content from each of the two or more memory locations. The computer-implemented method further includes packaging, by the node, the data content from each of the two or more memory locations into a memory package, and returning the memory package from the node to the one or more processors. A corresponding computer program product and computer system are also disclosed.

Abstract: A system capable of bi-directional data transfer, the system including a host configured to send downstream data to a peripheral and to receive upstream data from the peripheral, a main link coupled to the host and configured to transfer the downstream data from the host to the peripheral, and an auxiliary link coupled to the host and including a first auxiliary link lane for transferring the upstream data from the peripheral to the host in a first mode, and for transferring the downstream data from the host to the peripheral in a second mode, wherein the host is configured to engage in one or more handshake processes with the peripheral to cause the auxiliary link to switch between the first and second modes.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for on die buffered non-volatile memory management. A method includes storing data in a first set of non-volatile memory cells. A method includes determining whether to perform an error-correcting code (ECC) refresh for data to be copied from a first set of non-volatile memory cells to a second set of non-volatile memory cells based on one or more attributes associated with the data. A method includes storing data in a second set of non-volatile storage cells representing data using more storage cells per cell than a first set of non-volatile storage cells.

Abstract: An apparatus for managing a memory including a working region and a compression region is provided. The working region stores uncompressed data. The apparatus includes a management module and a compression/decompression module. According to a recent used index and a compression ratio of a set of target data stored in the working region, the management module determines whether to transfer the target data to the compression region. When the management module determines to transfer the target data to the compression region, the compression/decompression module compresses the target data and transfers the compressed target data to the compression region.

Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Abstract: An image processor includes a memory including multiple memory banks each having multiple unit storage areas and holding an image, an image processing unit that processes an image, and an access controller that controls an access from the image processing unit to the memory. In storing the image in the memory, the access controller splits the image in multiple groups of unit pixel data pieces including pixel data of multiple columns by multiple rows, and stores groups of unit pixel data pieces aligned in at least two columns in a pixel space in the same unit storage area in the same memory bank.

Abstract: Improved power management techniques for computer-readable storage devices are described. In one embodiment, for example, an apparatus may comprise a plurality of logical storage devices and a controller to manage operations of the plurality of logical storage devices, the controller comprising a configuration component to configure a global power consumption threshold defining an overall power consumption budget for the plurality of logical storage devices, a tracking component to maintain a global power consumption tally comprising an estimated total power consumption level for the plurality of logical storage devices, and an arbitration component to resolve an operation request based on the global power consumption threshold and the global power consumption tally. Other embodiments are described and claimed.

Abstract: The present invention relates to the field of communication technologies and discloses a method and an apparatus for encoding a data address, so that attacks can be effectively prevented and resources and costs required to handle a bank conflict are reduced. In solutions provided by embodiments of the present invention, an exclusive-OR operation is performed on one or more bits of a received uncoded address by using multiple preset transform polynomials; and an encoded address is obtained according to a result of the exclusive-OR operation. The solutions provided by the embodiments of the present invention are applicable to designs that require a large-capacity DRAM, high performance and high reliability, and have an anti-attack demand.

Abstract: A memory system may include a memory including a cell array having a plurality of word lines and an address storage unit that stores an address in response to a capture command, wherein the memory sequentially refreshes the word lines in response to a refresh command at a set cycle, and refreshes a word line corresponding to the stored address in response to the refresh command when the address is stored in the address storage unit; and a memory controller transmitting the refresh command to the memory at the set cycle when a word line satisfying one or more of conditions that the number of activation times is equal to or more than a reference number and an activation frequency is equal to or more than a reference frequency is detected, and transmitting the capture command and an address of the detected word line to the memory.

Abstract: The embodiments of the present invention disclose a nonvolatile memory and an electronic device, where each time the nonvolatile memory is powered on, an exchanger is used to implement a random exchange of at least one address subsignal and its inverted signal in a bank decoder and/or a row decoder in a bank and/or a column decoder in a bank, which causes that data stored before the nonvolatile memory is powered off is interrupted when the nonvolatile memory is powered off and then powered on and that data stored in the nonvolatile memory cannot be read sequentially from original storage addresses to achieve an encrypting effect and increase security of the data stored in the nonvolatile memory.

Abstract: Technologies are generally described for systems, devices and methods relating to swapping bits in memory addresses in solid state devices. In some examples, a bit swap module may receive a first memory address. The first memory address may include a first bit value at a first position of the first memory address and/or a second bit value at a second position of the first memory address. The bit swap module may swap the first bit value with the second bit value to produce a second memory address. The second memory address may be sent to a memory controller. In some examples, the first memory address may relate to a first package of memory and the second memory address may relate to a second package of memory.

Abstract: Provided are a computer program product, system, and method for providing access information to a storage controller to determine a storage tier for storing data. Access information is maintained for each data record in a data store, wherein the access information indicates a level of access to each data record in the data store. A write request directed to a data record in the data store is received. A command is generated identifying the data record and including the access information for the data record. The command is transmitted to the storage controller, wherein the storage controller uses the access information to determine one of the plurality of storage tiers on which to store the data record.

Abstract: Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device. In response, the primary driver module is disabled and an emergency driver module is enabled. Each of the plurality of slave memory chips are selected using a multiplexing unit to retrieve data using the emergency driver module.

Abstract: Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device. In response, the primary driver module is disabled and an emergency driver module is enabled. Each of the plurality of slave memory chips are selected using a multiplexing unit to retrieve data using the emergency driver module.

Abstract: System and methods for proactively refreshing portions of a nonvolatile memory including a memory system that proactively refreshes a portion of nonvolatile memory based on data associated with the portion. The data may include the time elapsed since the portion was last refreshed, the number of times the portion has been cycled, and the average operating temperature of the nonvolatile memory. A portion of nonvolatile memory, when meeting certain criteria determined from the data, may be proactively refreshed during a downtime when the nonvolatile memory is not otherwise being accessed.

Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

Abstract: Hierarchical compression includes the contemporaneous implementation of link-layer and higher-layer compression on data flowing over a link. Hierarchical compression can be achieved by configuring network nodes positioned at the link-layer to recognize higher-layer compression symbols embedded in incoming data streams, and to adapt link-layer compression to compensate for those higher-layer compression symbols. One technique for adapting link-layer compression is to perform data chunking in-between higher-layer compression symbols. This may reduce the likelihood that higher-layer compression symbols will interfere with the network nodes ability to identify redundant data chunks at the link-layer. Another technique for adapting link-layer compression is to define the HASH algorithm in such a way that the hash of a data string renders the same hash value as the hash of the higher layer compression symbol corresponding to the data string.

Abstract: Mechanisms for predicting whether a memory access may be a page hit or a page miss and applying different page policies (e.g., an open page policy or a close page policy) based on the prediction are disclosed. A counter may be used to determine a hit rate (e.g., a percentage or a ratio of the number of memory accesses that are page hits). The processing device may apply different page policies based on the hit rate. A memory access history (that includes data indicating a sequence or list of memory accesses) may be used to identify a counter from a plurality of counters. The processing device may apply different page policies based on the value of the counter (e.g., based on whether the counter is greater than a threshold).

Abstract: A semiconductor memory device is provided which includes a first port configured to connect to a first processor and including a first interface circuit; a second port configured to connect to a second processor and including a second interface circuit; and a memory cell array including a first memory area connected to the first and second ports in common. The first memory area includes a plurality of magneto-resistive random access memory cells. The first interface circuit is configured to receive a DRAM interface signals, and the second interface circuit is configured to receive a flash memory interface signals.

Abstract: A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns. Each of the rows is addressable by a row address. Each of the data elements in each of the rows is addressable by a column address. The at least one row address buffer holds a selected row address of a set of successive selected row addresses. The set of row data buffers holds respective contents of selected rows that correspond to the set of successive selected row addresses. The row decoder decodes the selected row address to access a selected row. The array of sense amplifier reads the selected row and transmits content of the selected row to one of the row data buffers through the demultiplexer, and writes the content of the selected row back to the selected row.

Abstract: A memory controller enters a memory mode, allocating memory address space within a pair of dual in line memory modules (DIMMs) such that each DIMM of the pair contains unallocated memory address space corresponding to allocated memory space in the other DIMM. The memory controller enters another memory mode, modifying the allocation of the memory address space from a first DIMM of the pair of DIMMs to a second DIMM of the pair of DIMMs. The data is moved from allocated memory address space of the first DIMM to unallocated memory address space in the second DIMM.

Abstract: A semiconductor device includes an initialization information generation unit configured to operate in response to a first clock and generate first initialization information having a value that is adjusted according to a value of an address signal that corresponds to output data, a domain crossing unit configured to receive the first initialization information in response to the first clock and output the first initialization information as second initialization information by outputting the second initialization information in response to a second clock, and a pulse generation unit configured to operate in response to the second clock and adjust a toggling point in time of a control pulse in response to the second initialization information.

Abstract: A memory controller enters a memory mode, allocating memory address space within a pair of dual in line memory modules (DIMMs) such that each DIMM of the pair contains unallocated memory address space corresponding to allocated memory space in the other DIMM. The memory controller enters another memory mode, modifying the allocation of the memory address space from a first DIMM of the pair of DIMMs to a second DIMM of the pair of DIMMs. The data is moved from allocated memory address space of the first DIMM to unallocated memory address space in the second DIMM.

Abstract: If a monitor measurement cycle is set as a long cycle, promotion in a short cycle cannot be performed; and even if the number of I/Os is very large in response to fluctuations of the number of I/Os in several minutes to several hours of normal work, pages will be promoted after waiting for several weeks. As a result, I/Os which could have normally accepted by an upper tier will be accepted by a lower tier, which results in a problem of worsening the performance efficiency. A monitoring system capable of preventing demotion due to temporary reduction of the number of I/Os for specific pages from a viewpoint of a long cycle and enabling prompt promotion in response to an increase of the number of U/Os for 3 the specific pages is realized. A load index value defined from a viewpoint of a long cycle and a load index value defined from a viewpoint of a short cycle are updated based on the number of I/Os which is counted cyclically for each storage area.

Abstract: Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network.

Abstract: A semiconductor memory device performs a modified read operation or a modified write operation. The semiconductor memory device includes a memory cell array, a read circuit, and a write circuit. The semiconductor memory device further includes an operation unit performing an operation on read data obtained by the read circuit according to operation assignment information applied through an address line to reduce memory access time when entering a modified read mode. In addition, the semiconductor memory device may optionally manage a normal read mode and the modified read mode and allow operation result data output from the operation unit to be written by the write circuit in the modified read mode.

Abstract: A circuit for a flat panel display, capable of displaying images, is provided. The circuit includes an image storage block for storing the images to be displayed, a display and timing controller block controlling the display operation, an image pixel matrix containing a multitude of rows and columns arranged pixel elements. The circuit also includes one or more controlled row driver blocks, one or more controlled column driver blocks, and a pixel pre-charge mechanism for pre-charging the pixel elements employing a back to back pre-charge operation applied to a row and/or column drive activated pixel element display operation. The back to back pre-charge operation signifies that during every other operating sequence a pre-charge operation is replaced by an activated pixel element display operation.

Abstract: A package on package (PoP) apparatus includes a shared ZQ calibration path and a shared ZQ calibration resistor for calibrating multiple channels of DRAM on a memory package of the PoP apparatus. Arbitration circuitry on a processor package of the PoP apparatus is coupled to separate memory controllers for the multiple memory channels. The arbitration circuitry is configured to indicate availability of the shared ZQ calibration resistor. The memory controllers are configured to communicate with the arbitration circuitry before performing a ZQ calibration and to delay the ZQ calibration when the arbitration circuitry indicates the ZQ calibration resistor is busy.

Abstract: A method of encoding data for transmissions from a source to a destination over a communications channel is provided. The method operates on an ordered set of source symbols and may generate zero or more redundant symbols from the source symbols, wherein data is encoded in a first step according to a simple FEC code and in a second step, data is encoded according to a second FEC code, more complex than the first FEC code. The first FEC code and/or the second FEC code might comprise coding known in the art. These steps result in two groups of encoded data in such a way that a low-complexity receiver may make use of one of the groups of encoded data while higher complexity receivers may make use of both groups of encoded data.