Abstract: A cache server is operative as one of a set of cache servers of a distributed cache. The server includes a processor and a memory connected to the processor. The memory stores instructions executed by the processor to receive a cache storage request, establish a cache eviction requirement in response to the cache storage request, and identify an evict entry within a cache in response to the cache eviction requirement. The evict entry is selected from a random sampling of entries within the cache that are subject to an eviction policy that identifies a probabilistically favorable eviction candidate. The evict entry is removed from the cache. Content associated with the storage request is loaded into the cache.

Abstract: In an image processing device, a motion image decoding processing unit extracts a feature amount of a target image to be decoded from an input stream, and changes a read size of a cache fill from an external memory to a cache memory, based on the feature amount. The feature amount represents an intra macro block ratio in, for example, one picture (frames or fields), or a motion vector variation. When the intra macro block ratio is high, the read size of the cache fill is decreased.

Abstract: A parallel track/sector switching device and associated method is provided. The method includes identifying data replication sources and locating data replication targets associated with the data replication sources. Data replication instances associated with moving data from the data replication sources to the data replication targets are determined. A first data replication instance for moving first data from a first data replication source to a first data replication target is determined and an antenna capacity associated with the first data replication source and the first data replication target is identified. A memory to track ID map associated with a storage device of the first data replication target is identified and it is determined if a last replication slot has been allotted to the first data replication target based on the memory to track ID map.

Abstract: A multi-core CPU system includes a shared L2 cache, an access control logic circuit, a plurality of cores, each core configured to access the shared L2 cache through the access control logic circuit, and a size adjusting circuit configured to adjust a size of the shared L2 cache in response to an indication signal that indicates a number of operation cores among the plurality of cores.

Abstract: Data from a group of distributed processes to a shared file is written using a parallel log-structured file system. A metadata server of a cluster file system is configured to communicate with a plurality of object storage servers of the cluster file system over a network. The metadata server further configured to implement a Parallel Log Structured File System (PLFS) library to coordinate storage on one or more of the plurality of object storage servers of a plurality of portions of a shared file generated by a plurality of applications executing on compute nodes of the cluster file system and to store metadata for the plurality of portions of the shared file. Concurrent writes to the shared file are decoupled by writing the plurality of portions of the shared file generated by each of the plurality of applications to independent write streams for each application.

Abstract: Systems and methods for enabling programmable cache size via Class of Service (COS) cache allocation are described. In some embodiments, a method may include: identifying a resource available to an Information Handling System (IHS) having a cache, where the resource is insufficient to allow the entire cache to be flushed during a power outage event; dividing a cache into at least a first portion and a second portion using a COS cache allocation, where the second portion has a size that is entirely flushable with the resource; and flushing the second portion of the cache during the power outage event.

Abstract: Aspects of the present disclosure disclose systems and methods for managing a level-two persistent cache. In various aspects, a solid-state drive is employed as a level-two cache to expand the capacity of existing caches. In particular, any data that is scheduled to be evicted or otherwise removed from a level-one cache is stored in the level-two cache with corresponding metadata in a manner that is quickly retrievable. The data contained within the level-two cache is managing using a cache list that manages and/or maintains data chunk entries added to the level-two cache based on a temporal access of the data chunk.

Abstract: A scheduling method whereby a virtualization unit, which has multiple nodes containing physical CPUs and physical memories, and which operates a virtual computer by generating logical partitions from the computer resources of the multiple nodes, allocates a physical CPU to the logical CPU. The multiple nodes are coupled via an interconnect, and the virtualization unit selects the physical CPU to be allocated to the logical CPU, and measures performance information related to the performance when the physical memory is accessed from the logical CPU. When the performance information satisfies a prescribed threshold value the physical CPU allocated to the logical CPU is selected from the same node as that of the previously allocated physical CPU, and when the performance information does not satisfy the prescribed threshold value the physical CPU allocated to the logical CPU is selected from a different node than the node of the previously allocated physical CPU.

Abstract: An electronic system includes: an interface block of a storage device configured to process system information from a system device; a memory block of the storage device, coupled to the interface block, partitioned by the interface block configured to process the system information for partitioning the memory block; and a storage block of a storage device, coupled to the memory block, configured to access a data block of the storage block provided to the system device.

Abstract: An electronic device with a cache memory and a method of operating the electronic device are provided. The electronic device includes a cache memory including a plurality of cache lines each of which includes a first area with at least one storage space and a second area with at least one storage space, where the at least one storage space of the first area has a first size and the at least one storage space of the second area has a second size different from the first size, and a cache controller for storing the data requested for storage in one of the storage spaces of the first or second area, according to a compression factor associated with the data requested for storage when a request is made to store data in the cache memory.

Abstract: Embodiments of the invention are directed to enabling concurrent commands from command requesters in a non-volatile solid-state storage subsystem in a manner that reduces contentions among the commands. Embodiments group blocks of memory into multiple sets of superblocks and associate a command requester to each superblock set. In one embodiment, the superblock sets are dynamically associated with a requester. In one embodiment, the superblock sets are dynamically associated with requesters based in part on at least one of internal memory management needs and host command throughput. In one embodiment, an erase command is executed on a superblock within a set and a simultaneous write command is executed on a superblock within another set.

Abstract: Disclosed is a method of managing a storage server in a database system. Provided is a storage server including a cache device to store at least one block that includes data; a permanent storage medium to record the at least one block stored in the cache device; and a controller to record the at least one block stored in the cache device in the permanent storage medium, wherein the controller includes a grade determiner to determine a grade of each of the at least one block based on a size of each of the at least one block; a victim block determiner to determine a victim block to be recorded in the permanent storage medium among blocks stored in the cache device based on the determined grade of each of the at least one block; and a block recorder to record the determined victim block in the permanent storage medium.

Abstract: A cache or other cluster is configuration-aware such that initialization and changes to the underlying structure of the cluster can be dynamically updated for use by a client. A client may use a client driver as an intermediary that is responsible for managing the communication with the cluster. For example, a client driver may resolve an alias from a static configuration endpoint to a storage node. The client driver may request an initial configuration from the storage node and then update configuration from one or more storage nodes that store current configuration of the cluster.

Abstract: Systems and methods to safely and efficiently handle dirty data flush are disclosed. More specifically, when a cache controller determines that one (or more) storage device of a cache device is running out of space, that storage device is given priority to be flushed prior to the other storage devices that are not in such a critical condition. In addition, a cache bypass process can be conditionally enabled to save free physical spaces already running low on such critical cache storage devices.

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to provide a first redundancy scheme when user data occupies less than a preconfigured limit and a second redundancy scheme that protects less than all of the user data when the user data occupies greater than the preconfigured limit.

Abstract: Methods, systems, and computer program products are provided for performing a secure delete operation in a wide area network (WAN) including a cache site and a home site. A method includes identifying a file for deletion at the cache site, determining whether the file has a copy stored at the home site, detecting a location of the copy at the home site prior to a disconnection event of the cache site from the home site, deleting the file from the cache site during the disconnection event, and performing a secure deletion of the copy at the home site immediately after a reconnection event of the cache site to the home site.

Abstract: A method of controlling a storage device comprises monitoring whether a quality of service (QoS) of the storage device satisfies a quality condition set through a host, and adjusting a current setting of at least one operation metric of the storage device related to the QoS, according to a result of the monitoring.

Abstract: Techniques are disclosed for improving application responsiveness, and particularly applications used to present rich media content, by precaching nearby but not-yet-displayed content, so that content can be immediately ready to display. A precache window can be used to determine what undisplayed content is precached, in accordance with an embodiment. The size of the precache window, and hence the amount of content that can be precached for later display, is dynamic in nature and is determined based on a number of variables, such as the distance of the content from being visible and the estimated memory consumption of the content. In addition, the dynamic precache window can be recalculated in real-time in response to events and/or as the user interacts with the content in a way that causes a significant enough change to warrant a new memory limit estimate be performed. Out-of-memory errors may be handled by reducing precache window.

Abstract: A system and method provide a unified cache in a Small Computer System Interface (SCSI) device which can be dynamically allocated to one or more Logical Units (LUs). A cache balancer module of the SCSI device can allocate the entire unified cache to a single LU, or divide the unified cache among multiple LUs. The cache entries for each LU can be further classified based on Quality of Service (QoS) traffic classes within each LU thereby improving the QoS performance. The system provides a cache allocation table that maintains a unified cache allocation status for each LU.

Abstract: The disclosure is directed to a system and method of cache management for a data storage system. According to various embodiments, the cache management system includes a hinting driver and a priority controller. The hinting driver generates pointers based upon data packets intercepted from data transfer requests being processed by a host controller of the data storage system. The priority controller determines whether the data packets are associated with at least a first (high) priority level or a second (normal or low) priority level based upon the pointers generated by the hinting driver. High priority data packets are stored in cache memory regardless of whether they satisfy a threshold heat quotient (i.e. a selected level of data transfer activity).

Abstract: Methods, systems, and computer program products for providing dynamic batch management of shared packet buffers are disclosed. A virtualized computer system may include a hypervisor with access to memory and executed by a processor to maintain a pool of host memory to store a plurality of incoming network packets received by a network device, adjust a number of memory buffers associated with the pool of host memory to resize the pool of host memory, receive an indication of an incoming network packet stored in the pool of host memory by the network device, and provide the incoming network packet to a guest. In an example, the hypervisor uses the pool of host memory to perform batch processing of the incoming network packets and dynamically adjusts the size of the pool during the processing by adding or removing memory buffers in response to an event, condition, request, etc.

Abstract: Improved caching mechanisms are presented herein for use with an in-memory distributed cache and, potentially, other types of caches. One mechanism permits cache clients to wait on a cache key being fetched by one or more other cache clients. When the cache key arrives at the cache, the waiting cache clients may be called back with the cache key. Another mechanism allows a service to push changed values directly into a distributed cache. Yet another mechanism allows the storage of information in a cache that defines dependencies between cached values. The dependency information can be utilized to invalidate cache values that are dependent upon other cached values that have been invalidated.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.

Abstract: Cache utility curves are determined for different software entities depending on how frequently their storage access requests lead to cache hits or cache misses. Although possible, not all access requests need be tested, but rather only a subset, determined by whether a hash value of each current storage location identifier (such as an address or block number) meets one or more sampling criteria.

Abstract: Storage tracks from at least one server are destaged from the write cache rank when it is determined that the at least one server is idle with respect to a first set of ranks, and storage tracks are refrained from being destaged from each rank when it is determined that the at least one server is not idle with respect to a second set of ranks such that storage tracks in the first set of ranks may be destaged while storage tracks in the second set of ranks are not being destaged.

Abstract: Storage tracks from at least one host are destaged from the write cache rank when it is determined that the at least one host is idle with respect to a first set of ranks, and storage tracks are refrained from being destaged from each rank when it is determined that the at least one host is not idle with respect to a second set of ranks such that storage tracks in the first set of ranks may be destaged while storage tracks in the second set of ranks are not being destaged.

Abstract: In one embodiment, the present invention includes a cache, compute engines connected to the cache, and a way mask disposed between the cache and the compute engines. This way mask may be partitioned into ways. Some of the ways may be dedicated to only one of the compute engines and other ways can be shared among more than one of the compute engines. Other embodiments are described and claimed.

Abstract: An approach is provided in which a caching appliance receives a data packet over a network connection utilizing a network protocol. The caching appliance selects a storage area based upon the network protocol and stores the data packet in the selected storage area. In one embodiment, the caching appliance identifies a service level that corresponds to the network protocol and selects the storage area based upon the identified service level.

Abstract: Systems and methods for supporting a plurality of load and store accesses of a cache are disclosed. Responsive to a request of a plurality of requests to access a block of a plurality of blocks of a load cache, the block of the load cache and a logically and physically paired block of a store coalescing cache are accessed in parallel. The data that is accessed from the block of the load cache is overwritten by the data that is accessed from the block of the store coalescing cache by merging on a per byte basis. Access is provided to the merged data.

Abstract: An example method for passive compaction of a cache includes determining first metadata associated with first data and second metadata associated with second data. The first metadata includes a first retrieval time, and the second metadata includes a second retrieval time. The example method further includes obtaining a first metadata key including a first unique identifier and obtaining a second metadata key including a second unique identifier. The example method also includes generating a first data key and generating a second data key. The example method further includes writing, at a client device, the first and second data to the cache. Each of the first and second data occupy one or more contiguous blocks of physical memory in the cache, and the first and second data are stored in the cache in an order based on the relative values of the first and second retrieval times.

Abstract: According to an embodiment, a computer-implemented method for control block management is provided. The computer-implemented method includes placing one or more control blocks in a queue for execution by a computer hardware device. The computer-implemented method also includes allocating a purge flag in each of the control blocks. The purge flag instructs the computer hardware device to skip execution of the corresponding control block.

Abstract: A system and method for providing a transactional-consistent cache for database objects is disclosed. New data is received by a cache manager. The cache manager updates an entry of a cache with the new data received by the cache manager, by registering the updating of the entry with the new data with an invalidator. The registering includes a timestamp. An invalidation event is then generated by the invalidator. The invalidation event includes a notification about the updating of the entry of the cache with the new data received by the cache manager according to the timestamp.

Abstract: A computer system that includes a central processing unit, a random-access-memory interface, a random-access memory whose addresses are allocated in an address space of the random-access-memory interface, and a reconfigurable arithmetic device is described herein. The reconfigurable arithmetic device includes input terminals, output terminals, a network of plurality of processor elements, a built-in random-access memory, a control unit, an inter-processor-element network and a configuration-data memory. In accordance with configuration on data from the configuration-data memory, the inter processor-element network is capable of changing the connection state of the input terminals and the output terminals to input ports and output ports of the plurality of processor elements, and the arithmetic function of the reconfigurable arithmetic device is capable of being dynamically changed.

Abstract: In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data.

Abstract: A method, system, and computer program product for non-interrupting performance tuning using runtime reset are provided in the illustrative embodiments. Component performance data from a component of a data processing system is analyzed. The component participates in processing a workload of a workload type. The analyzing determines a characteristic of the workload. A performance requirement of the workload is determined according to a performance requirement of the workload type. A set of preferred performance tuning parameter values is identified to apply to the component to meet the performance requirement of the workload. The set of preferred performance tuning parameter values is sent to the component such that the component is tuned using a value in the set of preferred performance tuning parameter values to meet the performance requirement of the workload.

Abstract: Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.

Abstract: A system includes a cache and a processor coupled to the cache. The cache stores data in multiple storage tracks and each storage track includes an associated multi-bit counter. The processor is configured to perform the following method. One method includes incrementing the multi-bit counter on each respective storage track a predetermined amount each time the processor writes to a respective storage track. The method further includes decrementing each multi-bit counter each scan cycle, and destaging each storage track including a zero count.

Abstract: Storage tracks are destaged from the write cache if the host(s) is/are idle and are not destaged from the write cache if one or more of the hosts is/are not idle. The storage tracks are refrained from being destaged from the write cache if the at least one host is not idle. Each rank is monitored for write operations from the at least one host, and a determination is made if the at least one host is idle with respect to each respective rank based on monitoring each rank for write operations from the at least one host such that the at least one host may be determined to be idle with respect to a first rank and not idle with respect to a second rank.

Abstract: A tiered memory system includes a memory controller for a primary memory and a secondary memory, where the secondary memory is used as a cache for the primary memory. The memory controller is configured to cause redundant data that is stored in the primary memory of the memory system to be stored in first memory locations of the secondary memory. The controller causes data that is not stored in the primary memory to be stored in second memory locations of the secondary memory. The second memory locations have at least one of lower bit error rate and higher access speed than the first memory locations.

Abstract: A method of avoiding a write collision in single port memory devices from two independent write operations is described. A first data object from a first write operation is divided into a first even sub-data object and first odd sub-data object. A second data object from a second write operation is divided into a second even sub-data object and a second odd sub-data object. The first even sub-data object is stored to a first single port memory device and the second odd sub-data object to a second single port memory device when the first write operation and the second write operation occur at the same time. The second even sub-data object is stored to the first single port memory device and the first odd sub-data object to the second single port memory device when the first write operation and the second write operation occur at the same time.

Abstract: Some of the embodiments of the present disclosure provide a method comprising receiving a data packet, and storing the received data packet in a memory; generating a descriptor for the data packet, the descriptor including information for fetching at least a portion of the data packet from the memory; and in advance of a processing core requesting the at least a portion of the data packet to execute a processing operation on the at least a portion of the data packet, fetching the at least a portion of the data packet to a cache based at least in part on information in the descriptor. Other embodiments are also described and claimed.

Abstract: A data storage system may be configured at least with a primary memory that is coupled to a host via a controller and coupled to at least one external interface. The controller may be adapted to passively partition a secondary memory into cache and user memory space regions in response to the secondary memory engaging the at least one external interface and the cache region can be allocated as cache for the primary memory by the controller.

Abstract: Systems and methods are provided for a hardware-implemented multi-buffer. A system includes a buffer memory comprising a shared memory space, where the memory space is shared between a first buffer and a second buffer, and where a dynamic delineation of the memory space between the first buffer and the second buffer is identified by a divider address. A dynamic buffer control circuit includes a control memory that is configured to store the divider address, a first memory utilization metric associated with the first buffer, and a second memory utilization metric associated with the second buffer. A system further includes one or more comparator circuits configured to compare the first memory utilization metric and the second memory utilization metric, where the dynamic buffer control circuit changes the divider address based on the comparison.

Abstract: A device and method for partitioning a cache that is expected to operate with at least two classes of clients (such as real-time clients and non-real-time clients). A first portion of the cache is dedicated to real-time clients such that non-real-time clients are prevented from utilizing said first portion.

Abstract: A method, computer program product, and computing system for reclassifying a first assigned cache portion associated with a first machine as a public cache portion associated with the first machine and at least one additional machine after the occurrence of a reclassifying event. The public cache portion includes a plurality of pieces of content received by the first machine. A content identifier for each of the plurality of pieces of content included within the public cache portion is compared with content identifiers for pieces of content included within a portion of a data array associated with the at least one additional machine to generate a list of matching data portions. The list of matching data portions is provided to at least one additional assigned cache portion within the cache system that is associated with the at least one additional machine.

Abstract: Technology is provided for partitioning a shared unified cache in a multi-processor computer system. The technology can receive a request to allocate a portion of a shared unified cache memory for storing only executable instructions, partition the cache memory into multiple partitions, and allocate one of the partitions for storing only executable instructions. The technology can further determine the size of the portion of the cache memory to be allocated for storing only executable instructions as a function of the size of the multi-processor's L1 instruction cache and the number of cores in the multi-processor.

Abstract: An apparatus and method for efficient handling of critical chunks. For example, one embodiment of an apparatus comprises a plurality of agents to perform a respective plurality of data processing functions, at least one of the data processing functions comprising transmitting and receiving chunks of data to and from a memory controller, respectively; a system agent to coordinate requests for transmitting and receiving the chunks of data to and from the memory controller, the system agent comprising: a memory for temporarily storing the chunks of data during transmission between the agents and the memory controller; and scheduling logic to prioritize critical chunks over non-critical chunks across multiple outstanding requests while ensuring that the non-critical chunks do not result in starvation.

Abstract: The illustrative embodiments provide a computer implemented method, apparatus, and computer usable program code for managing a heap. The heap is partitioned into at least one sub heap based on a relationship to at least one memory class of a plurality of memory classes. A memory allocation request comprising a memory class is received from a requester. A unique heap handle based on the memory class and associated with a specific sub heap is generated. The unique heap handle is then returned to the requester.

Abstract: Destaging storage tracks from each rank that includes a greater than a predetermined percentage of a predetermined amount of storage space with respect to a current amount of storage space allocated to each rank until the current amount of storage space used by each respective rank is equal to the predetermined percentage of the predetermined amount of storage space. The destage storage tracks are declined from being destaged from each rank that includes less than or equal to the predetermined percentage of the predetermined amount of storage space rank.

Abstract: A system and method for adjusting space allocated for different page sizes on a recording medium includes dividing the recording medium into multiple blocks such that a block size of the multiple blocks supports a largest page size, and such that each of the multiple blocks is used for a single page size, and assigning an incoming page to a block based on a temperature of the incoming page.