Abstract: Zoned initialization of a solid state drive is provided. A solid state memory device includes a controller for controlling storage and retrieval of data to and from the device. A set of solid state memory components electrically coupled to the controller. The set is electrically divided into a first zone and a second zone, wherein the first zone is at least partially initialized independent from the second zone. An interface is coupled between the controller and the set of solid state memory components to facilitate transfer of data between the set of solid state memory components and the controller.

Abstract: When a storage capacity of a file server is expanded using an online storage service, elimination of an upper-limit constraint of the file size as a constraint of the online storage service and reduction in the communication cost are realized. A kernel module including logical volumes on the online storage service divides a file into block files at a fixed length and stores and manages the block files to prevent the upper-limit constraint of the file size. When a READ/WRITE request is generated for a mounted file system, only necessary block files are downloaded and used from the online storage service based on an offset value and size information to optimize the communication and realize the communication cost reduction.

Abstract: A system protects database operations performed on a shared resource. The system may chunk memory to form a set of memory chunks which have memory blocks, at least some of the memory blocks including database objects. The system may configure at least one binary search tree using the memory chunks as nodes and buffer a set of pointers corresponding to the memory blocks. The system may further validate the buffered pointers and dereference validated buffered pointers.

Abstract: According to one embodiment, a storage device includes: a backup unit configured to perform backup at the time of a power shutoff; a storage module configured to store information; a cache memory configured to perform caching of the storage module; and a controller configured to adjust a size of a cache to the cache memory according to exhaustion of the backup unit.

Abstract: A cache memory system comprises a cache memory and a cache controller that receives a first address to access the cache memory. The cache controller includes a first address transformer receives the first address and to transform it into one first cache address; the first cache address is used for accessing the cache memory to retrieve a first part of a tag address portion. The cache controller includes a hit detector establishes an partial hit condition based on a comparison of the retrieved a first part of the tag address portion and a first predetermined part of the first address, and a second address transformer receives the first address and to transform it into one second cache address. The cache controller uses the one second cache address for accessing the cache memory to retrieve a data word in case the partial hit condition is established.

Abstract: Systems, methods and computer program products for data buffers partitioned from a cache array. An exemplary embodiment includes a method in a processor and for providing data buffers partitioned from a cache array, the method including clearing cache directories associated with the processor to an initial state, obtaining a selected directory state from a control register preloaded by the service processor, in response to the control register including the desired cache state, sending load commands with an address and data, loading cache lines and cache line directory entries into the cache and storing the specified data in the corresponding cache line.

Abstract: A method, system, and computer usable program product for isolating a workload partition space are provided in the illustrative embodiments. A boot process of a workload partition in a data processing system is started using a scratch file system, the scratch file system being in a global space. A portion of a storage device containing a file system for the workload partition is exported to the workload partition, the portion forming an exported disk. The partially booted up workload partition may discover the exported disk. The exporting causes an association between the global space and the exported disk to either not form, or sever. The exporting places the exported disk in a workload partition space associated with the workload partition. The boot process is transitioned to stop using the scratch file system and start using the data in the exported disk for continuing the boot process.

Abstract: Asymmetric hardware support for a special class of threads is provided. Preferably, the special class threads are high-priority, I/O bound threads. Preferably, a multithreaded processor contains N sets of registers for supporting concurrent execution of N threads. At least one of the register sets is dedicated for use by a special class of threads, and can not be used by other threads even if idle. The special class of threads can fill only the a limited portion of the cache memory, in order to reduce flushing of the cache which might otherwise occur.

Abstract: A mechanism for data buffering is provided. A portion of a cache is allocated as buffer regions, and another portion of the cache is designated as random access memory (RAM). One of the buffer regions is assigned to a processor. A data block is stored to the one of the buffer regions of the cache according an instruction of the processor. The data block is stored from the one of the buffer regions of the cache to the memory.

Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

Abstract: A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.

Abstract: A mechanism is provided in a virtual machine monitor for providing cache partitioning in virtualized environments. The mechanism assigns a virtual identification (ID) to each virtual machine in the virtualized environment. The processing core stores the virtual ID of the virtual machine in a special register. The mechanism also creates an entry for the virtual machine in a partition table. The mechanism may partition a shared cache using a vertical (way) partition and/or a horizontal partition. The entry in the partition table includes a vertical partition control and a horizontal partition control. For each cache access, the virtual machine passes the virtual ID along with the address to the shared cache. If the cache access results in a miss, the shared cache uses the partition table to select a victim cache line for replacement.

Abstract: Managing access to a cache memory includes dividing said cache memory into multiple of cache areas, each cache area having multiple entries; and providing at least one separate lock attribute for each cache area such that only a processor thread having possession of the lock attribute corresponding to a particular cache area can update that cache area.

Abstract: A system and method optimizing data throughput to a processor from a storage device having sequential data access capabilities where the processor enables its data cache for memory operations involving the storage device. The system includes a processor coupled to the data storage device, e.g., a NAND flash memory. The processor establishes an address window used as a cache (CW) for reading data from the flash memory and also establishes a non-cacheable address window (NCW) for commands, address delivery and writes to the flash memory. The CW is sized to be larger than the processor data cache to ensure that reads from the flash memory always encounter a cache-miss so that read data is obtained directly from the flash memory. By reading through the CW from the flash memory, the processor takes advantage of bursting, pipelining and data prefetch efficiencies which significantly increase data throughput.

Abstract: A mechanism is provided for providing an improved reconfigurable cache. The mechanism partitions a large cache into inclusive cache regions with equal-ratio size or other coarse size increase. The cache controller includes an address decoder for the large cache with a large routing structure. The cache controller includes an additional address decoder for the small cache with a smaller routing structure. The additional address decoder for the small cache reduces decode, array access, and data return latencies. When only a small cache is actively in use, the rest of the cache can be turned into low-power mode to save power.

Abstract: A multi-queue FIFO memory device that uses existing pins of the device to load a desired number of queues (N) into a queue number register is provided. The queue number register is coupled to a queue size look-up table (LUT), which provides a queue size value in response to the contents of the queue number register. The queue size value indicates the amount of memory (e.g., the number of memory blocks) to be included in each of the N queues. The queue size value is provided to a queue start/end address generator, which automatically generates the start and end address associated with each queue in response to the queue size value. These start and end addresses are stored in queue address register files, which enable proper memory read/write and flag counter operations.

Abstract: In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of non-transparent memory blocks. Software executing on one or more processors may request a non-transparent memory block in which to process data. The control circuit may allocate a first block, and may return an address (or other indication) of the allocated block so that the software can access the block. The control circuit may also provide automatic data movement between the non-transparent memory and a main memory system to which the non-transparent memory unit is coupled. For example, the automatic data movement may include filling data from the main memory system to the allocated block, or flushing the data in the allocated block to the main memory system after the processing of the allocated block is complete.

Abstract: In some embodiments, a processor-based system includes a processor, a system memory coupled to the processor, a mass storage device, a cache memory located between the system memory and the mass storage device, and code stored on the processor-based system to cause the processor-based system to utilize the cache memory. The code may be configured to cause the processor-based system to preferentially use only a selected size of the cache memory to store cache entries having less than or equal to a selected number of cache hits. Other embodiments are disclosed and claimed.

Abstract: Disclosed are a method, a system and a computer program product for operating a cache system. The cache system can include multiple cache lines, and a first cache line of the multiple of cache lines can include multiple cache cells, and a bus coupled to the multiple cache cells. In one or more embodiments, the bus can include a switch that is operable to receive a first control signal and to split the bus into first and second portions or aggregate the bus into a whole based on the first control signal. When the bus is split, a first cache cell and a second cache cell of the multiple cache cells are coupled to respective first and second portions of the bus. Data from the first and second cache cells can be selected through respective portions of the bus and outputted through a port of the cache system.

Abstract: An embodiment of this invention divides a cache memory of a storage system into a plurality of partitions and information in one or more of the partitions is composed of data different from user data and including control information. The storage system dynamically swaps data between an LU storing control information and a cache partition. Through this configuration, in a storage system having an upper limit in the capacity of the cache memory, a large amount of control information can be used while access performance to control information is kept.

Abstract: The present invention is directed to a circuit for managing data movement between an interface supporting the PLB6 bus protocol, an interface supporting the AMBA AXI bus protocol, and internal data arrays of a cache controller and/or on-chip memory peripheral. The circuit implements register file buffers for gathering data to bridge differences between the bus protocols and bus widths in a manner which addresses latency and performance concerns of the overall system.

Abstract: A method and apparatus for controlling affinity of subcaches is disclosed. When a core compute unit evicts a line of victim data, a prioritized search for space allocation on available subcaches is executed, in order of proximity between the subcache and the compute unit. The victim data may be injected into an adjacent subcache if space is available. Otherwise, a line may be evicted from the adjacent subcache to make room for the victim data or the victim data may be sent to the next closest subcache. To retrieve data, a core compute unit sends a Tag Lookup Request message directly to the nearest subcache as well as to a cache controller, which controls routing of messages to all of the subcaches. A Tag Lookup Response message is sent back to the cache controller to indicate if the requested data is located in the nearest sub-cache.

Abstract: There is provided a composite type recording apparatus restricting write operations depending on the type of a connected host apparatus, including a recording medium having a first data region, a non-volatile storage medium having a second data region and an identification information table for integrating and managing the first and second data region, an information selection section for selecting positional information having predetermined identification information from the identification information table according to the type of the host apparatus, a conversion section for converting positional information selected by the information selection section into positional information matching the first data region or positional information matching the second data region, a first write section for writing data supplied from the host apparatus in the first data region according to conversion process of the conversion section and a second write section for writing data supplied from the host apparatus in the se

Abstract: Systems and methods for background destaging storage tracks from cache when one or more hosts are idle are provided. One system includes a write cache configured to store a plurality of storage tracks and configured to be coupled to one or more hosts, and a processor coupled to the write cache. The processor includes code that, when executed by the processor, causes the processor to perform the method below. One method includes monitoring the write cache for write operations from the host(s) and determining if the host(s) is/are idle based on monitoring the write cache for write operations from the host(s). The storage tracks are destaged from the write cache if the host(s) is/are idle and are not destaged from the write cache if one or more of the hosts is/are not idle. Also provided are physical computer storage mediums including a computer program product for performing the above method.

Abstract: Systems and methods for managing destage conflicts in cache are provided. One system includes a cache partitioned into multiple ranks configured to store multiple storage tracks and a processor coupled to the cache. The processor is configured to perform the following method. One method includes allocating an amount of storage space in the cache to each rank and monitoring a current amount of storage space used by each rank with respect to the amount of storage space allocated to each respective rank. The method further includes destaging storage tracks from each rank until the current amount of storage space used by each respective rank is equal to a predetermined minimum amount of storage space with respect to the amount of storage space allocated to each rank. Also provided are physical computer storage mediums including code that, when executed by a processor, cause the processor to perform the above method.

Abstract: Technologies are generally described for allocating available prefetch bandwidth among processor cores in a multiprocessor computing system. The prefetch bandwidth associated with an off-chip memory interface of the multiprocessor may be determined, partitioned, and allocated across multiple processor cores.

Abstract: An apparatus, system, and method are disclosed for deduplicating storage cache data. A storage cache partition table has at least one entry associating a specified storage address range with one or more specified storage partitions. A deduplication module creates an entry in the storage cache partition table wherein the specified storage partitions contain identical data to one another within the specified storage address range thus requiring only one copy of the identical data to be cached in a storage cache. A read module accepts a storage address within a storage partition of a storage subsystem, to locate an entry wherein the specified storage address range contains the storage address, and to determine whether the storage partition is among the one or more specified storage partitions if such an entry is found.

Abstract: A multi-processor computer system is provided for managing physical memory domains. The system includes at least one processor having an address interface for sending a memory access message, which includes an address in physical memory and a domain identification (ID). The system also includes a physical memory portioned into a plurality of domains, where each domain includes a plurality of physical addresses. A domain mapping unit (DMU) has an interface to accept the memory access message from the processor. The DMU uses the domain ID to access a permission list, cross-reference the domain ID to a domain including addresses in physical memory, and grant the processor access to the address in response to the address being located in the domain.

Abstract: A technique implements a novel high-speed high-density packet buffer utilizing a combination of high-speed and low-speed memory devices. The novel packet buffer is organized as a plurality of FIFO queues where each FIFO queue is associated with a particular input or output line. Each queue comprises a high-speed cache portion that resides in high-speed memory and a low-speed high-density portion that resides in low-speed high-density memory. The high-speed cache portion contains FIFO data that contains head and/or tail associated with the novel FIFO queue. The low-speed high-density portion contains FIFO data that is not contained in the high-speed cache portion.

Abstract: A cache region can be created in a cache in response to receiving a cache region creation request from an application. A storage request from the application can identify the cache region and one or more objects to be stored in the cache region. Those objects can be stored in the cache region in response to receiving the storage request.

Abstract: A system and method are provided for managing cache memory in a computer system. A cache controller portions a cache memory into a plurality of partitions, where each partition includes a plurality of physical cache addresses. Then, the method accepts a memory access message from the processor. The memory access message includes an address in physical memory and a domain identification (ID). A determination is made if the address in physical memory is cacheable. If cacheable, the domain ID is cross-referenced to a cache partition identified by partition bits. An index is derived from the physical memory address, and a partition index is created by combining the partition bits with the index. A processor is granted access (read or write) to an address in cache defined by partition index.

Abstract: In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.

Abstract: A system and method determines when the entries of a reply cache, organized into microcaches each of which is allocated to a client connection, may be retired or released, thereby freeing up memory structures. A plurality of connection statistics are defined and tracked for each microcache and for the entries of the microcache. The connection statistics indicate the value of the microcache and its entries to the client. The connection statistics include a measure of the time since the last idempotent or non-idempotent request (TOLR) was received, and a count of the number of idempotent requests that have been received since the last non-idempotent request (RISLR). A microcache with a TOLR time and a RISLR count that exceed respective thresholds may be expired and removed from the reply cache.

Abstract: In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory. Other embodiments are disclosed and claimed.

Abstract: A apparatus is provided for updating data within a business planning tool. The apparatus comprises a computer memory (22) arranged to store operational data in a plurality of line items (50), each line item (50) being arranged to represent operational data in data cells (52) occupying space in a plurality of dimensions (X, Y), and each line item (50) having data cells in a first dimension (Y) configured to represent the operational data in a at least one hierarchy level, and having data cells in a second dimension (X) arranged to represent the respective operational data over at least one time period.

Abstract: A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification layer that employs multiple queues to simulate receipt of packets, calculation of destination addresses and storage of the packet data by the device. Call backs are employed to signal completion of events related to storage of packet data by the device and modeling of data processing within the verification layer. Processing of tokens within the verification layer to mimic the device's processing of corresponding packets is performed according to a dynamic DMA policy modeled on the device's policy. The policy is dynamic and can be updated or replaced during verification without interrupting the verification process.

Abstract: A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.

Abstract: Embodiments that dynamically reorganize data of cache lines in non-uniform cache access (NUCA) caches are contemplated. Various embodiments comprise a computing device, having one or more processors coupled with one or more NUCA cache elements. The NUCA cache elements may comprise one or more banks of cache memory, wherein ways of the cache are horizontally distributed across multiple banks. To improve access latency of the data by the processors, the computing devices may dynamically propagate cache lines into banks closer to the processors using the cache lines. To accomplish such dynamic reorganization, embodiments may maintain “direction” bits for cache lines. The direction bits may indicate to which processor the data should be moved. Further, embodiments may use the direction bits to make cache line movement decisions.

Abstract: A technique for limiting an amount of write data stored in a cache memory includes determining a usable region of a non-volatile storage (NVS), determining an amount of write data in a current write request for the cache memory, and determining a failure boundary associated with the current write request. A count of the write data associated with the failure boundary is maintained. The current write request for the cache memory is rejected when a sum of the count of the write data associated with the failure boundary and the write data in the current write request exceeds a determined percentage of the usable region of the NVS.

Abstract: A system comprising a host, a solid state device, and an abstract layer. The host may be configured to generate a plurality of input/output (IO) requests. The solid state device may comprise a write cache region and a read cache region. The read cache region may be a mirror of the write cache region. The abstract layer may be configured to (i) receive the plurality of IO requests, (ii) process the IO requests, and (iii) map the plurality of IO requests to the write cache region and the read cache region.

Abstract: According to the disclosure, a unique and novel archiving system that provides one or more application layer partitions to archive data is disclosed. Embodiments include an active archive including a fixed storage. The active archive can create application layer partitions that associate the application layer partitions with portions of the fixed storage. Each application layer partition, in embodiments, has a separate set of controls that allow for customized storage of different data within a single archiving system. Further, embodiments of methods for ensuring storage capacity in the active archive and the application layer partitions within the active archive is also disclosed.

Abstract: Techniques a generally described for creating a compiler determined map for the allocation of memory space within a cache. An example computing system is disclosed having a multicore processor with a plurality of processor cores. At least one cache may be accessible to at least two of the plurality of processor cores. A compiler determined map may separately allocate a memory space to threads of execution processed by the processor cores.

Abstract: A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region of the system memory. Each of the plurality of processing units includes a processor core and a cache memory including a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory and a cache controller. The cache controller, responsive to a store request from the processor core to update a particular VBSR line, performs a non-blocking update of the cache array in each other of the plurality of processing units contemporaneously holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.

Abstract: A method and system for a decentralized distributed storage data system. A plurality of central processors each having a cache may be directly coupled to a shared set of data storage units. A high speed network may be used to communicate at a physical level between the central processors. A coherency protocol may be used to communicate at a logical level between the central processors.

Abstract: The present invention provides a method and apparatus for allocating space in a unified cache. The method may include partitioning the unified cache into a first portion of lines that only store copies of instructions retrieved from a memory and a second portion of lines that only store copies of data retrieved from the memory.

Abstract: An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core.

Abstract: A storage system, which is coupled to a computer, includes a storage device, a controller, a plurality of cache memory units, and a connecting unit. Each of the plurality of cache memory units includes: a cache memory for storing data; an auxiliary storage device for holding a content of data even after shutdown of power; and a cache controller for controlling an input/output of data to/from the cache memory and the auxiliary storage device. The cache controller store data stored in the cache memory, which is divided into a plurality of parts, into a plurality of the auxiliary storage devices included in the plurality of cache memory units.

Abstract: Methods, apparatuses, and systems directed to efficient compression processing in system architectures including a control plane and a data plane. Particular implementations feature integration of compression operations and mode selection with a beltway mechanism that takes advantage of atomic locking mechanisms supported by certain classes of hardware processors to handle the tasks that require atomic access to data structures while also reducing the overhead associated with these atomic locking mechanisms.

Abstract: A computing system stores a database comprising pages. Each of the pages is the same size. When a page is requested, a block of virtual memory addresses is associated with the page and a set of physical data storage locations is committed to the block of virtual memory addresses. A copy of the page is then stored into the set of physical data storage locations. Physical data storage locations committed to the virtual memory addresses associated with available free space in the copy of the page are deallocated, thereby allowing reuse of these physical data storage locations. A reference to the copy of the page is then returned.

Abstract: A cache memory system controlled by an arbiter includes a memory unit having a cache memory whose capacity is changeable, and an invalidation processing unit that requests invalidation of data stored at a position where invalidation is performed when the capacity of the cache memory is changed in accordance with a change instruction. The invalidation processing unit includes an increasing/reducing processing unit that sets an index to be invalidated in accordance with a capacity before change and a capacity after change and requests the arbiter to invalidate the set index, and an index converter that selects either an index based on the capacity before change or an index based on the capacity after change associated with an access address from the arbiter, and the capacity of the cache memory can be changed while maintaining the number of ways of the cache memory.