Shared Cache Patents (Class 711/130)
  • Patent number: 11226822
    Abstract: A digital data processor includes an instruction memory storing instructions specifying a data processing operation and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to perform a table write in response to a look up table initialization instruction by duplicating at least one data element from a source data register to create duplicated data elements, and writing the duplicated data elements to a specified location in a specified number of at least one table and a corresponding location in at least one other table.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: January 18, 2022
    Assignee: Texas Instmments Incorporated
    Inventors: Naveen Bhoria, Dheera Balasubramanian Samudrala, Duc Bui, Rama Venkatasubramanian
  • Patent number: 11216377
    Abstract: A mechanism is provided by which a hardware accelerator detects migration of a software process among processors and uses this information to write operation results to an appropriate cache memory for faster access by the current processor. This mechanism is provided, in part, by incorporation within the hardware accelerator of a mapping table having entries including a cache memory identifier associated with a processor identifier. The hardware accelerator further includes circuitry configured to receive a processor identifier from a calling processor, and to perform a look-up in the mapping table to determine the cache memory identifier associated with the processor identifier. The hardware accelerator uses the associated cache memory identifier to write results of called operations to the cache memory associated with the calling processor, thereby accelerating subsequent operations by the calling processor that rely upon the hardware accelerator results.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: January 4, 2022
    Assignee: NXP USA, Inc.
    Inventors: Allen Lengacher, David Philip Lapp, Roy Jonathan Pledge
  • Patent number: 11200169
    Abstract: A processing node of a storage system may determine that a host system is implementing a cache-slot aware, round-robin IO distribution algorithm (CA-RR). The processing node may be configured to determine when a sufficient number of sequential IOs will be received to consume a cache slot of the a processing node. If the processing node knows that the host system is implementing CA-RR, then, in response to determining the sufficient number, the processing node may send a communication informing the next processing node about the sequential cache slot hit. If the sequential IO operation(s) are read operation(s), the next processing node may prefetch at least a cache-slot worth of next consecutive data portions. If the sequential IO operation(s) are write operation(s), then the next processing node may request allocation of one or more local cache slots for the forthcoming sequential write operations.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: December 14, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Jack Fu, Jaeyoo Jung, Arieh Don
  • Patent number: 11194721
    Abstract: To deliver up-to-date, coherent user data to applications upon request, the disclosed technology includes systems and methods for caching data and metadata after it has been synchronously loaded—for future retrieval with a page load time close to zero milliseconds. To provide this experience, data needs to be stored as locally to a user as possible, in the cache on the local device or in an edge cache located geographically nearby, for use in responding to requests. Applications which maintain caches of API results can be notified of their invalidation, and can detect the invalidation, propagate the invalidation to any further client tiers with the appropriate derivative type mapping, and refresh their cached values so that clients need not synchronously make the API requests again—insuring that the client has access to the most up-to-date copy of data as inexpensively as possible—in terms of bandwidth and latency.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: December 7, 2021
    Assignee: salesforce.com, inc.
    Inventor: Richard Perry Pack, III
  • Patent number: 11194617
    Abstract: A method includes receiving, by a level two (L2) controller, a write request for an address that is not allocated as a cache line in a L2 cache. The write request specifies write data. The method also includes generating, by the L2 controller, a read request for the address; reserving, by the L2 controller, an entry in a register file for read data returned in response to the read request; updating, by the L2 controller, a data field of the entry with the write data; updating, by the L2 controller, an enable field of the entry associated with the write data; and receiving, by the L2 controller, the read data and merging the read data into the data field of the entry.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: December 7, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, David Matthew Thompson
  • Patent number: 11159636
    Abstract: A data processing apparatus is provided, which includes receiving circuitry to receive a snoop request in respect of requested data on behalf of a requesting node. The snoop request includes an indication as to whether forwarding is to occur. Transmitting circuitry transmits a response to the snoop request and cache circuitry caches at least one data value. When forwarding is to occur and the at least one data value includes the requested data, the response includes the requested data and the transmitting circuitry transmits the response to the requesting node.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: October 26, 2021
    Assignee: ARM LIMITED
    Inventors: Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal, Klas Magnus Bruce
  • Patent number: 11157415
    Abstract: Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more page walk caches, where operation includes: receiving, at a load/store slice, an instruction to be issued; determining, at the load/store slice, a process type indicating a source of the instruction to be a host process or a guest process; and determining, in accordance with an allocation policy and in dependence upon the process type, an allocation of an entry of the page walk cache, wherein the page walk cache comprises one or more entries for both host processes and guest processes.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dwain A. Hicks, Jonathan H. Raymond, George W. Rohrbaugh, III, Shih-Hsiung S. Tung
  • Patent number: 11144470
    Abstract: Method for managing a cache memory comprising: the transformation of a received set address in order to find a word in the cache memory, into a transformed set address by means of a bijective transformation function, the selection of one or more line tags stored in the cache memory at the transformed set address. in which: the transformation function is parameterized by a parameter q such that the transformed set address obtained depends both on the received set address and on the value of this parameter q, and for all the non-zero values of the parameter q, the transformation function permutes at least 50% of the set addresses, and during the same execution of the process, a new value of the parameter q is repeatedly generated for modifying the transformation function.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 12, 2021
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Thomas Hiscock, Mustapha El Majihi, Olivier Savry
  • Patent number: 11138086
    Abstract: A computing system for collecting hardware performance data includes a number of programmable counters associated with a number of units of a computing device. The computing system further includes an assignment module executed by a processor to assign a plurality of interleaving groups of counters based on a user-defined priority list of parameters.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: October 5, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Raphael Gay, Peter Christian Peterson, Finagnon Thierry Dossou, Jr.
  • Patent number: 11119953
    Abstract: A data access method. The method is applied to a first controller, and the method includes: receiving a destination address sent by each shared cache apparatus, where the destination address is used to indicate an address at which data is to be written into the shared cache apparatus; receiving information carrying the data; and sending the destination address and the data to the shared cache apparatus that sends the destination address, so that each shared cache apparatus stores the data in storage space to which the destination address points.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: September 14, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chao Zhou, Peiqing Zhou
  • Patent number: 11106467
    Abstract: Apparatus and methods are disclosed for implementing incremental schedulers for out-of-order block-based processors, including field programmable gate array implementations. In one example of the disclosed technology, a processor includes an instruction scheduler formed by configuring one or more look up table RAMs to store ready state data for a plurality of instructions in an instruction block. The instruction scheduler further includes a plurality of queues that store ready state data for the processor and sends dependency information to ready determination logic on a first in/first out basis. The instruction scheduler selects one or more of the ready instructions to be issued and executed by the block-based processor.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: August 31, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Aaron L. Smith, Jan S. Gray
  • Patent number: 11100111
    Abstract: A streaming ingest platform can improve latency and expense issues related to uploading data into a cloud data system. The streaming ingest platform can organize the data to be ingested into per-table chunks and per-account blobs. This data may be committed and may be made available for query processing before it is ingested into the target source tables. This significantly improves latency issues. The streaming ingest platform can also accommodate uploading data from various sources with different processing and communication capabilities, such as Internet of Things (IOT) devices.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: August 24, 2021
    Assignee: Snowflake Inc.
    Inventors: Tyler Arthur Akidau, Istvan Cseri, Tyler Jones, Daniel E. Sotolongo, Zhuo Zhang
  • Patent number: 11099952
    Abstract: Populating cache of a virtual server. A data record is generated that is associated with a first virtual server. A set of data is saved that describes data in a cache that is associated with the first virtual server. In response to either (i) a failover of the first virtual server or (ii) a migration request for the first virtual server, a cache of a second virtual server is populated based on the set of data.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Vamshikrishna Thatikonda, Sanket Rathi, Venkata N. S. Anumula
  • Patent number: 11093398
    Abstract: Embodiments may include systems and methods for performing remote memory operations in a shared memory address space. An apparatus includes a first network controller coupled to a first processor core. The first network controller processes a remote memory operation request, which is generated by a first memory coherency agent based on a first memory operation for an application operating on the first processor core. The remote memory operation request is associated with a remote memory address that is local to a second processor core coupled to the first processor core. The first network controller forwards the remote memory operation request to a second network controller coupled to the second processor core. The second processor core and the second network controller are to carry out a second memory operation to extend the first memory operation as a remote memory operation. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Kshitij Doshi, Harald Servat, Francesc Guim Bernat
  • Patent number: 11036279
    Abstract: An apparatus and method are provided for managing a cache. The cache is arranged to comprise a plurality of cache sections, where each cache section is powered independently of the other cache sections in the plurality of cache sections, and the apparatus has power control circuitry to control power to each of the cache sections. The power control circuitry is responsive to a trigger condition indicative of an ability to operate the cache in a power saving mode, to perform a latency evaluation process to determine a latency indication for each of the cache sections, and to control which of a subset of the cache sections to power off in dependence on the latency indication. This can allow the power consumption savings realised by turning off one or more cache sections to be optimised to take into account the current system state.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: June 15, 2021
    Assignee: Arm Limited
    Inventor: Alex James Waugh
  • Patent number: 11032126
    Abstract: A framework in a cloud network that may allow for debugging at multiple vantage points at different layers (e.g., layer 2, layer 3, etc.). The methods may provide tracer or measurement services that filter, capture, or forward flows that may include packets, calls, or protocols to look for particular signatures.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: June 8, 2021
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Byoung-Jo Kim, Yang Xu, Muhammad Bilal Anwer
  • Patent number: 10997076
    Abstract: An apparatus has first processing circuitry and second processing circuity. The second processing circuitry has at least one hardware mechanism providing a greater level of fault protection or fault detection than is provided for the first processing circuitry. Coherency control circuitry controls access to data from at least part of a shared address space by the first and second processing circuitry according to an asymmetric coherency protocol in which a local-only update of data in a local cache of the first processing circuitry is restricted in comparison to a local-only update of data in a local cache of the second processing circuitry.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: May 4, 2021
    Assignee: ARM Limited
    Inventors: Antony John Penton, Simon John Craske
  • Patent number: 10977035
    Abstract: A data processing system includes at least one processing unit and a memory controller coupled to a system memory. The processing unit includes a processor core and a cache memory including an arithmetic logic unit (ALU). The cache memory is configured to receive, from the processor core, an atomic memory operation (AMO) request specifying a target address of a data granule to be updated by an AMO and a location indication. Based on the location indication having a first setting, the AMO indicated by the AMO request is performed in the cache memory utilizing the ALU. Based on the location indication having a different second setting, the cache memory issues the AMO request to the memory controller to cause the AMO to be performed at the memory controller.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Derek E. Williams, Guy L. Guthrie
  • Patent number: 10949355
    Abstract: Aspects of the present disclosure provide various apparatus, devices, systems and methods for dynamically configuring a cache partition in a solid state drive (SSD). The SSD may include non-volatile memory (NVM) that can be configured to store a different number of bits per cell. The NVM is partitioned into a cache partition and a storage partition, and the respective sizes of the partitions is dynamically changed based on a locality of data (LOD) of the access pattern of the NVM.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: March 16, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Avichay Haim Hodes, Oren Cohen, Judah Gamliel Hahn
  • Patent number: 10949352
    Abstract: A cache is shared by a first and second processor, and is divided into a first cache portion corresponding to a first requestor identifier (ID) and a second cache portion corresponding to a second requestor ID. The first cache portion is accessed in response to memory access requests associated with the first requestor ID, and the second cache portion is accessed in response to memory access requests associated with the second requestor ID. A memory controller communicates with a shared memory, which is a backing store for the cache. A corresponding requestor ID is received with each memory access request. Each memory access request includes a corresponding access address identifying a memory location in the shared memory and a corresponding index portion, wherein each corresponding index portion selects a set in a selected cache portion of the first and second cache portions selected based on the received corresponding requestor ID.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: March 16, 2021
    Assignee: NXP USA, Inc.
    Inventor: Paul Kimelman
  • Patent number: 10936493
    Abstract: An example memory system may include a central processing unit (CPU) comprising a CPU cache, a storage class memory, a volatile memory and a memory controller. The memory controller is to store, in the storage class memory, a first cache line including first data and a first directory tag corresponding to the first data. The memory controller is to further store, in the storage class memory, a second cache line including second data and a second directory tag corresponding to the second data. The memory controller is to store, in the volatile memory, a third cache line that comprises the first directory tag and the second directory tag, the third cache line excluding the first data and the second data.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 2, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Robert C. Elliott, James A. Fuxa
  • Patent number: 10922134
    Abstract: Techniques process data. The techniques involve determining priority of a plurality of cores of a processor based on metadata stored in a plurality of queues associated with the plurality cores, respectively, the metadata being related to data blocks to be processed that are associated with the respective cores, and the metadata in each of the queues being sorted by arrival times of the respective data blocks to be processed. The techniques further involve storing core identifiers of the plurality of cores into a cache by an order of the priorities. By means of at least some of the above techniques, quick insertion of metadata can be realized through multiple queues and the efficiency of determining data blocks to be processed is improved based on sorting of the cores.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 16, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Ming Zhang, Zan Liu, Shuo Lv
  • Patent number: 10901639
    Abstract: A system for allocating memory (e.g., heap) in multi-core processors is provided. In some implementations, the system performs operations comprising receiving, at a shared cache having a plurality of segments, a first data allocation including a plurality of data blocks, and allocating at least a first and second data block from the first allocation. First and second segments in the shared cache can each comprise a plurality of data slots (e.g., of equal length). Allocating the first and second data blocks can include storing the first data block in a data slot of the first segment and storing the second data block in a data slot of the second segment. The plurality of data slots which do not contain data may contain padding, and/or the data slots to which the first and second data blocks are allocated are not adjacent. Related systems, methods, and articles of manufacture are also described.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: January 26, 2021
    Assignee: SAP SE
    Inventors: Daniel Booss, Robert Kettler, Mehul Wagle, Harshada Khandekar, Ivan Schreter
  • Patent number: 10878883
    Abstract: The present disclosure includes apparatuses and methods for cache invalidate. An example apparatus comprises a bit vector capable memory device and a channel controller coupled to the memory device. The channel controller is configured to cause a bulk invalidate command to be sent to a cache memory system responsive to receipt of a bit vector operation request.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Richard C. Murphy
  • Patent number: 10867644
    Abstract: A memory system includes a plurality of nonvolatile memory devices sharing a communication line; and a controller including a buffer and a core, and suitable for controlling the nonvolatile memory devices through the communication line, wherein the core determines a type of a plurality of read requests for the nonvolatile memory devices, and sets a usable size of the buffer depending on the type.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: December 15, 2020
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 10860376
    Abstract: Provided is a communication apparatus and a base station. The apparatus includes a clock management resource pool and a power management resource pool, and further includes at least one of: a baseband resource pool, a general-purpose computing resource pool, or a network exchange processing resource pool. The baseband resource pool includes at least one baseband processing unit, the general-purpose computing resource pool includes at least one computing unit, the clock management resource pool includes at least one clock management unit, the network exchange processing resource pool includes at least one network exchange processing unit, and the power management resource pool includes at least one power management unit.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: December 8, 2020
    Assignee: ZTE CORPORATION
    Inventors: Wei Zhang, Fan Wang, Minchao Liang, Jinqing Yu, He Zhang
  • Patent number: 10854310
    Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Chiaki Dono, Taihei Shido, Yuki Ebihara
  • Patent number: 10853249
    Abstract: Facilitating processing in a computing environment. A request to access a cache of the computing environment is obtained from a transaction executing on a processor of the computing environment. Based on obtaining the request, a determination is made as to whether a tracking set to be used to track cache accesses is to be updated. The tracking set includes a read set to track read accesses of at least a selected portion of the cache and a write set to track write accesses of at least the selected portion of the cache. The tracking set is assigned to the transaction, and another transaction to access the cache has another tracking set assigned thereto. The tracking set assigned to the transaction is updated based on the determining indicating the tracking set is to be updated.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: December 1, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10831494
    Abstract: A main processor 4 executes a main program and has an associated cache memory 6. Event detection circuitry 12 detects events consequent upon execution of the main program and indicative of data to be used by the main processor. One or more programmable further processors 16, 18 is triggered to execute a further program by the events detected by the event detection circuitry 12. Prefetch circuitry 28 is responsive to the further program executed by the one or more programmable further processors to trigger prefetching of the data to be used by the main processor to the cache memory.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: November 10, 2020
    Assignees: ARM Limited, The Chancellor, Masters and Scholars of the University of Cambridge
    Inventors: Thomas Christopher Grocutt, Sam Ainsworth, Timothy Martin Jones
  • Patent number: 10831674
    Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Markus Helms, Christian Jacobi, Ulrich Mayer, Martin Recktenwald, Johannes C. Reichart, Anthony Saporito, Aaron Tsai
  • Patent number: 10809918
    Abstract: Options for handling write operations may be selected based on a determined probability that a read operation for a portion of data will occur while the data portion is still in an I/O cache as a result of a write operation. As used herein, a “read-after-write event (“RAW”) is an occurrence of a read operation for a portion of data while the data portion is still in an I/O cache as a result of a write operation. The probability of a RAW may be determined by applying Bayesian inference, and may include applying exponential smoothing to calculations made on historical I/O information so that more recent I/O events have greater weight in determining RAW probability. Based on the determined RAW probability, write data may either be journaled in a write journal or written to a cache slot and de-staged to a physical storage device as part of write-in-place processing.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 20, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Owen Martin, Mark J. Halstead, William R. Smith-Vaniz
  • Patent number: 10802973
    Abstract: An apparatus includes a first database, a memory, and first and second processors. The first database stores a list including a first identifier assigned to the first processor and a second identifier assigned to the second processor. The processors each randomly shuffle a copy of the list and place the first element of their shuffled copy in a third list. Each processor further determines that the first identifier appears a first number of times and the second identifier appears a second number of times in the third list, the first number greater than the second number. In response to determining that the first number is greater than the second number, the first processor copies data stored in a second database into the memory and sets a flag to true, while the second processor determines that the flag is set to true and accesses the data copy stored in the memory.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: October 13, 2020
    Assignee: Bank of America Corporation
    Inventors: Udaya Kumar Raju Ratnakaram, Niroop Reddy Patimeedi, Sarvari Tadimalla, Maruthi Shanmugam, Jian Jim Chen, Punit Srivastava
  • Patent number: 10795599
    Abstract: A host of a storage system is coupled to multiple SSDs. Each SSD is configured with a migration cache, and each SSD corresponds to one piece of access information. The host obtains migration data information of to-be-migrated data in a source SSD, determines a target SSD, and sends a read instruction carrying information about to-be-migrated data and the target SSD to the source SSD. The source SSD reads a data block according to the read instruction from a flash memory of the source SSD into a migration cache of the target SSD. After a read instruction is completed by the SSD, the host sends a write instruction to the target SSD to instruct the target SSD to write the data block in the cache of the target SSD to a flash memory of the target SSD.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: October 6, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ge Du, Yu Hu, Jiancen Hou
  • Patent number: 10776274
    Abstract: Data processing circuitry comprises a cache memory to cache a subset of data elements from a main memory; a processing element to execute program code to access data elements having respective memory addresses, the processing element being configured to access the data elements in the cache memory and, in the case of a cache miss, to fetch the data elements from the main memory; prefetch circuitry, responsive to an access to a current data element, to initiate prefetching into the cache memory of a data element at a memory address defined by a current offset value relative to the address of the current data element; and offset value selection circuitry comprising: an address table to store memory addresses for which a data element accessed by the processing element resulted in a cache miss or an access to a previously prefetched data element; and detector circuitry to detect, for each of a group of candidate offset values, one or more respective metrics representing a proportion of a set of data element acces
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: September 15, 2020
    Assignee: Arm Limited
    Inventors: Lucas Garcia, Geoffray Matthieu Lacourba, Natalya Bondarenko, Nathanael Premillieu
  • Patent number: 10769069
    Abstract: Data processing circuitry comprises a cache memory to cache a subset of data elements from a main memory; a processing element to execute program code to access data elements having respective memory addresses, the processing element being configured to access the data elements in the cache memory and, in the case of a cache miss, to fetch the data elements from the main memory; prefetch circuitry, responsive to an access to a current data element, to initiate prefetching into the cache memory of a data element at a memory address defined by a current offset value relative to the address of the current data element; offset value selection circuitry comprising: an address table to store memory addresses for which a data element accessed by the processing element resulted in a cache miss or an access to a previously prefetched data element; detector circuitry to detect, for each of a group of candidate offset values, one or more respective metrics representing a proportion of a set of data element accesses whic
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: September 8, 2020
    Assignee: Arm Limited
    Inventors: Natalya Bondarenko, Lucas Garcia, Geoffray Matthieu Lacourba
  • Patent number: 10740281
    Abstract: A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: August 11, 2020
    Assignee: INTEL CORPORATION
    Inventors: Varghese George, Sanjeev S. Jahagirdar, Deborah T. Marr
  • Patent number: 10728324
    Abstract: An example embodiment may involve receiving, by a web server device and from a client device, a request for web content. The example embodiment may also involve determining, by the web server device, that a web document includes a script containing a synchronous client-side function call matching pre-determined criteria. The web content may be at least in part derivable from the web document. The example embodiment may also involve executing, by the web server device, the synchronous client-side function call to obtain output data. The example embodiment may also involve modifying, by the web server device, the web document to include the output data in a data structure associated with the synchronous client-side function call. The example embodiment may also involve transmitting, by the web server device and to the client device, the web document as modified.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: July 28, 2020
    Assignee: ServiceNow, Inc.
    Inventors: Christopher Tucker, Kyle Barron-Kraus
  • Patent number: 10678441
    Abstract: The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Robert M. Walker, James A. Hall, Jr., Frank F. Ross
  • Patent number: 10635806
    Abstract: A security agent can implement a least recently used (LRU)-based approach to suppressing events observed on a computing device. The security agent may observe events that occur on a computing device. These observed events may then be inserted into a LRU table that tracks, for a subset of the observed events maintained in the LRU table, a rate-based statistic for multiple event groups in which the subset of the observed events are classified. In response to a value of the rate-based statistic for a particular event group satisfying a threshold for the LRU-table, observed events that are classified in the event group can be sent to a remote security system with suppression by refraining from sending, to the remote security system, at least some of the observed events in the event group. The security agent may cease suppression after the rate-based statistic falls below a predetermined threshold level.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: April 28, 2020
    Assignee: CrowdStrike, Inc.
    Inventor: Daniel W. Brown
  • Patent number: 10628330
    Abstract: A method is described for enabling inter-process communication between a first application and a second application, the first application running within a first virtual machine (VM) in a host and the second application running within a second VM in the host, The method includes receiving a request to attach a shared region of memory to a memory allocation, identifying a list of one or more physical memory pages defining the shared region that corresponds to the handle, and mapping guest memory pages corresponding to the allocation to the physical memory pages. The request may be received by a framework from the second application and includes a handle that uniquely identifies the shared region of memory as well as an identification of at least one guest memory page corresponding to the memory allocation.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: April 21, 2020
    Assignee: VMware, Inc.
    Inventors: Gustav Seth Wibling, Jagannath Gopal Krishnan
  • Patent number: 10628267
    Abstract: Certain embodiments disclosed herein reduce or eliminate a communication bottleneck at the storage manager by reducing communication with the storage manager while maintaining functionality of an information management system. In some implementations, a client obtains information for enabling a secondary storage job (e.g., a backup or restore) from a storage manager and stores the information (which may be referred to as job metadata) in a local cache. The client may then reuse the job metadata for multiple storage jobs reducing the frequency of communication with the storage manager. When a configuration of the information management system changes, or the availability of resources changes, the storage manager can push updates to the job metadata to the clients. Further, a client can periodically request updated job metadata from the storage manager ensuring that the client does not rely on out-of-date job metadata.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: April 21, 2020
    Assignee: Commvault Systems, Inc.
    Inventors: Manoj Kumar Pradhan, Hemant Mishra, Dmitriy Borisovich Zakharkin, Sanath Kumar, Hetalkumar N. Joshi, Sunil Babu Telagamsetti, Divakar Radhakrishnan, Jayasree Yakkala, Rohit Sivadas, Pavan Kumar Reddy Bedadala, Gopikannan Venugopalsamy
  • Patent number: 10613999
    Abstract: Techniques and mechanisms for providing a shared memory which spans an interconnect fabric coupled between compute nodes. In an embodiment, a field-programmable gate array (FPGA) of a first compute node requests access to a memory resource of another compute node, where the memory resource is registered as part of the shared memory. In a response to the request, the first FPGA receives data from a fabric interface which couples the first compute node to an interconnect fabric. Circuitry of the first FPGA performs an operation, based on the data, independent of any requirement that the data first be stored to a shared memory location which is at the first compute node. In another embodiment, the fabric interface includes a cache agent to provide cache data and to provide cache coherency with one or more other compute nodes.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Thomas Willhalm, Karthik Kumar, Daniel Rivas Barragan, Patrick Lu
  • Patent number: 10614007
    Abstract: Providing interrupt service routine (ISR) prefetching in multicore processor-based systems is disclosed. In one aspect, a multicore processor-based system provides an ISR prefetch control circuit communicatively coupled to an interrupt controller and a plurality of instruction fetch units (IFUs) of a corresponding plurality of processor elements (PEs). Upon receiving an interrupt directed to a target PE of the plurality of PEs, the interrupt controller provides an interrupt request (IRQ) identifier to the ISR prefetch control circuit. Based on the IRQ identifier, the ISR prefetch control circuit fetches an ISR pointer to an ISR corresponding to the IRQ identifier. The ISR prefetch control circuit next selects a prefetch PE of the plurality of PEs to perform a prefetch operation to retrieve the ISR on behalf of the target PE, and provides an ISR prefetch request, including the ISR pointer, to an IFU of the prefetch PE.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: April 7, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Raghavendra Srinivas, Kaustav Roychowdhury, Siddesh Halavarthi Math Revana
  • Patent number: 10613972
    Abstract: Graphics processing systems and methods are described. For example, one embodiment of a graphics processing apparatus comprises a graphics processing unit (GPU), the GPU including an on-die cache and a cache configuration circuitry to dynamically configure the on-die cache for a plurality of contexts executed by the GPU. The cache configuration block is to receive a cache configuration request, the cache configuration request including context-specific cache requirements for a new context, and determine a priority associated with the context-specific cache requirements. The CCB can compare the context-specific cache requirements with pre-existing cache requirements based on the priority, and reallocate the cache based on the context-specific cache requirements and the priority.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Hema Chand Nalluri, Balaji Vembu, Pattabhiraman K, Altug Koker
  • Patent number: 10606755
    Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventors: Anil Vasudevan, Venkata Krishnan, Andrew J. Herdrich, Ren Wang, Robert G. Blankenship, Vedaraman Geetha, Shrikant M. Shah, Marshall A. Millier, Raanan Sade, Binh Q. Pham, Olivier Serres, Chyi-Chang Miao, Christopher B. Wilkerson
  • Patent number: 10579526
    Abstract: A data processing apparatus includes receiving circuitry to receive a snoop request sent by a source node in respect of requested data and transmitting circuitry. Cache circuitry caches at least one data value. The snoop request includes an indication as to whether the requested data is to be returned to the source node and when the at least one data value includes the requested data, the transmitting circuitry transmits a response to the source node including said requested data, in dependence on said indication.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: March 3, 2020
    Assignee: ARM Limited
    Inventors: Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal, Klas Magnus Bruce
  • Patent number: 10572320
    Abstract: In an approach to detection of co-location of container services, a method may include receiving, by a first program in a first cloud container on a first host, a bit string over a side channel within a trial period of time. The method may also include determining whether a key corresponding to the bit string matches a pre-determined key corresponding to a second program in a second cloud container. The method may further include determining whether the second cloud container is located on the first host based, at least in part, on whether the key corresponding to the bit string matches the pre-determined key. The side channel may include a first resource on the first host that is accessible by cloud containers located on the first host and the bit string is received by monitoring the first resource for activity indicative of bit values.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alisa Arno, Yuji Watanabe, Ai Yoshino
  • Patent number: 10567493
    Abstract: Some embodiments provide intelligent predictive stream caching for live, linear, or video-on-demand streaming content using prefetching, segmented caching, and request clustering. Prefetching involves retrieving streaming content segments from an origin server prior to the segments being requested by users. Prefetching live or linear streaming content segments involves continually reissuing requests to the origin until the segments are obtained or a preset retry duration is completed. Prefetching is initiated in response to a first request for a segment falling within a particular interval. Request clustering commences thereafter. Subsequent requests are queued until the segments are retrieved. Segmented caching involves caching segments for one particular interval. Segments falling within a next interval are not prefetched until a first request for one such segment in the next interval is received.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 18, 2020
    Assignee: Verizon Digital Media Services Inc.
    Inventors: Jonathan DiVincenzo, Seungyeob Choi, Karthik Sathyanarayana, Robert J. Peters, Eric Dyoniziak
  • Patent number: 10565112
    Abstract: Methods and apparatus for memory management are described. In a disclosed embodiment, a system has a first and a second processor, with each processor able to access a memory system. A first work unit is received for execution by the first processor, with the memory system being accessed. A second work unit is generated for execution by a second processor upon execution of a first work unit. Only after the memory system is updated does processing of the second work unit by the second processor occur. This work unit message based ordering provides relay consistency for memory operations of multiple processors.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 18, 2020
    Assignee: Fungible, Inc.
    Inventors: Wael Noureddine, Jean-Marc Frailong, Pradeep Sindhu, Bertrand Serlet
  • Patent number: 10558570
    Abstract: Described herein are embodiments of asymmetric memory management to enable high bandwidth accesses. In embodiments, a high bandwidth cache or high bandwidth region can be synthesized using the bandwidth capabilities of more than one memory source. In one embodiment, memory management circuitry includes input/output (I/O) circuitry coupled with a first memory and a second memory. The I/O circuitry is to receive memory access requests. The memory management circuitry also includes logic to determine if the memory access requests are for data in a first region of system memory or a second region of system memory, and in response to a determination that one of the memory access requests is to the first region and a second of the memory access requests is to the second region, access data in the first region from the cache of the first memory and concurrently access data in the second region from the second memory.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventors: Nadav Bonen, Zvika Greenfield, Randy Osborne