Abstract: A method, computer program product, and computing system for receiving, at a local node, a request to buffer data on a remote persistent cache memory system of a remote node. A target memory address within the remote persistent cache memory system may be sent from the local node via a remote procedure call (RPC). The data may be sent from the local node to the target memory address within the remote persistent cache memory system via a remote direct memory access (RDMA) command.

Abstract: Apparatus, methods, and computer-readable storage media are disclosed for core-to-core communication between physical and/or virtual processor cores. In some examples of the disclosed technology, application cores write notification data (e.g., to doorbell or PCI configuration memory space accesses via a memory interface), without synchronizing with the other application cores or the service cores. In one examples of the disclosed technology, a message selection circuit is configured to, serialize data from the plurality of user cores by: receiving data from a user core, selecting one of the service cores to send the data based on a memory location addressed by the sending user core, and sending the received data to a respective message buffer dedicated to the selected service core.

Abstract: A system for cloud-based file services, comprising: a plurality of single-tenant file system nodes configured to provide file system access to an object store via a plurality of multitenant storage nodes; the plurality of multitenant storage nodes sharing access to the object store; and one or more management nodes configured to provision resources for the plurality of single-tenant file system nodes and the plurality of multitenant storage nodes.

Abstract: Disclosed are a memory system, a memory controller, and a method of operating a memory system. The memory system may control the memory device to store data into zones of memory blocks in the memory device by assigning each data to be written with an address subsequent to a most recently written address in a zone, store journal information including mapping information between a logical address and a physical address for one of the one or more zones in a journal cache, search for journal information corresponding to a target zone targeted to write data when mapping information for the target zone among the one or more zones is updated, and replace the journal information corresponding to the target zone with journal information including the updated mapping information.

Abstract: First and second-level caches are provided. Cache control circuitry performs a first-level cache lookup of the first-level cache based on a lookup address, to determine whether the first-level cache stores valid cached data corresponding to the lookup address. When lookup hint information associated with the lookup address is available, the cache control circuitry determines based on the lookup hint information whether to activate or deactivate a second-level cache lookup of the second-level cache. The lookup hint information is indicative of whether the second-level cache is predicted to store valid cached data associated with the lookup address. When the second-level cache lookup is activated, the second-level cache lookup of the second-level cache is performed based on the lookup address to determine whether the second-level cache stores valid cached data corresponding to the lookup address.

Abstract: An apparatus includes a plurality of processor cores; a shared cache connected to the plurality of processor cores; a cache control unit connected to the shared cache; and a way allocation circuitry connected to at least one of the plurality of processor cores. The way allocation circuitry is external to the plurality of processor cores. The cache control unit and the way allocation circuitry are cooperatively configured to process an intercepted memory request with respect to designated ways in the shared cache, the designated ways being based on a partition identifier and a partition table.

Abstract: Various embodiments described herein provide for using a prefetch buffer with a cache of a memory sub-system to store prefetched data (e.g., data prefetched from the cache), which can increase read access or sequential read access of the memory sub-system over that of traditional memory sub-systems.

Abstract: Techniques for consolidating shared state for translation lookaside buffer (TLB) shootdowns are provided. In one set of embodiments, an operating system (OS) kernel of a computer system can co-locate, in a system memory of the computer system, a plurality of shared data accessed by first and second processing cores of the computer system for performing a translation lookaside buffer (TLB) shootdown of the first processing core by the second processing core, where the co-locating allows the plurality of shared data to occupy a single cache line when brought from the system memory into a CPU (central processing unit) cache of the first or second processing core. This can include, e.g.

Abstract: Embodiments of the present disclosure provide an apparatus, comprising: one or more instruction executing circuitries, wherein each instruction executing circuitry of the one or more instruction executing circuitries is configured to execute an instruction of a corresponding instruction type, and an instruction scheduling circuitry that is communicatively coupled to the one or more instruction executing circuitries, the instruction scheduling circuitry is configured to: determine according to an instruction type of the instruction and a number of instructions that have been allocated to the one or more instruction executing circuitries, an instruction executing circuitry from the one or more instruction executing circuitries to schedule the instruction for execution, and allocated the instruction to the determined instruction executing circuitry.

Abstract: A pluggable trust architecture addresses the problem of establishing trust in hardware. The architecture has low impact on system performance and comprises a simple, user-supplied, and pluggable hardware element. The hardware element physically separates the untrusted components of a system from peripheral components that communicate with the external world. The invention only allows results of correct execution of software to be communicated externally.

Abstract: A method for thread-safe development of a computer program configured for parallel thread execution comprises maintaining a digital record of read or write access to a data object from each of a plurality of sibling threads executing on a computer system. Pursuant to each instance of read or write access from a given sibling thread, an entry comprising an indicator of the access type is added to the digital record. The method further comprises assessing the thread safety of the read or write access corresponding to each entry in the digital record and identifying one or more thread-unsafe instances of read or write access based on the assessment of thread safety.

Abstract: A streaming ingest platform can improve latency and expense issues related to uploading data into a cloud data system. The streaming ingest platform can organize the data to be ingested into per-table chunks and per-account blobs. This data may be committed and may be made available for query processing before it is ingested into the target source tables. This significantly improves latency issues. The streaming ingest platform can also accommodate uploading data from various sources with different processing and communication capabilities, such as Internet of Things (IOT) devices.

Abstract: A digital data processor includes an instruction memory storing instructions specifying a data processing operation and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to perform a table write in response to a look up table initialization instruction by duplicating at least one data element from a source data register to create duplicated data elements, and writing the duplicated data elements to a specified location in a specified number of at least one table and a corresponding location in at least one other table.

Abstract: A mechanism is provided by which a hardware accelerator detects migration of a software process among processors and uses this information to write operation results to an appropriate cache memory for faster access by the current processor. This mechanism is provided, in part, by incorporation within the hardware accelerator of a mapping table having entries including a cache memory identifier associated with a processor identifier. The hardware accelerator further includes circuitry configured to receive a processor identifier from a calling processor, and to perform a look-up in the mapping table to determine the cache memory identifier associated with the processor identifier. The hardware accelerator uses the associated cache memory identifier to write results of called operations to the cache memory associated with the calling processor, thereby accelerating subsequent operations by the calling processor that rely upon the hardware accelerator results.

Abstract: A processing node of a storage system may determine that a host system is implementing a cache-slot aware, round-robin IO distribution algorithm (CA-RR). The processing node may be configured to determine when a sufficient number of sequential IOs will be received to consume a cache slot of the a processing node. If the processing node knows that the host system is implementing CA-RR, then, in response to determining the sufficient number, the processing node may send a communication informing the next processing node about the sequential cache slot hit. If the sequential IO operation(s) are read operation(s), the next processing node may prefetch at least a cache-slot worth of next consecutive data portions. If the sequential IO operation(s) are write operation(s), then the next processing node may request allocation of one or more local cache slots for the forthcoming sequential write operations.

Abstract: A method includes receiving, by a level two (L2) controller, a write request for an address that is not allocated as a cache line in a L2 cache. The write request specifies write data. The method also includes generating, by the L2 controller, a read request for the address; reserving, by the L2 controller, an entry in a register file for read data returned in response to the read request; updating, by the L2 controller, a data field of the entry with the write data; updating, by the L2 controller, an enable field of the entry associated with the write data; and receiving, by the L2 controller, the read data and merging the read data into the data field of the entry.

Abstract: To deliver up-to-date, coherent user data to applications upon request, the disclosed technology includes systems and methods for caching data and metadata after it has been synchronously loaded—for future retrieval with a page load time close to zero milliseconds. To provide this experience, data needs to be stored as locally to a user as possible, in the cache on the local device or in an edge cache located geographically nearby, for use in responding to requests. Applications which maintain caches of API results can be notified of their invalidation, and can detect the invalidation, propagate the invalidation to any further client tiers with the appropriate derivative type mapping, and refresh their cached values so that clients need not synchronously make the API requests again—insuring that the client has access to the most up-to-date copy of data as inexpensively as possible—in terms of bandwidth and latency.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more page walk caches, where operation includes: receiving, at a load/store slice, an instruction to be issued; determining, at the load/store slice, a process type indicating a source of the instruction to be a host process or a guest process; and determining, in accordance with an allocation policy and in dependence upon the process type, an allocation of an entry of the page walk cache, wherein the page walk cache comprises one or more entries for both host processes and guest processes.

Abstract: A data processing apparatus is provided, which includes receiving circuitry to receive a snoop request in respect of requested data on behalf of a requesting node. The snoop request includes an indication as to whether forwarding is to occur. Transmitting circuitry transmits a response to the snoop request and cache circuitry caches at least one data value. When forwarding is to occur and the at least one data value includes the requested data, the response includes the requested data and the transmitting circuitry transmits the response to the requesting node.

Abstract: Method for managing a cache memory comprising: the transformation of a received set address in order to find a word in the cache memory, into a transformed set address by means of a bijective transformation function, the selection of one or more line tags stored in the cache memory at the transformed set address. in which: the transformation function is parameterized by a parameter q such that the transformed set address obtained depends both on the received set address and on the value of this parameter q, and for all the non-zero values of the parameter q, the transformation function permutes at least 50% of the set addresses, and during the same execution of the process, a new value of the parameter q is repeatedly generated for modifying the transformation function.

Abstract: A computing system for collecting hardware performance data includes a number of programmable counters associated with a number of units of a computing device. The computing system further includes an assignment module executed by a processor to assign a plurality of interleaving groups of counters based on a user-defined priority list of parameters.

Abstract: A data access method. The method is applied to a first controller, and the method includes: receiving a destination address sent by each shared cache apparatus, where the destination address is used to indicate an address at which data is to be written into the shared cache apparatus; receiving information carrying the data; and sending the destination address and the data to the shared cache apparatus that sends the destination address, so that each shared cache apparatus stores the data in storage space to which the destination address points.

Abstract: Apparatus and methods are disclosed for implementing incremental schedulers for out-of-order block-based processors, including field programmable gate array implementations. In one example of the disclosed technology, a processor includes an instruction scheduler formed by configuring one or more look up table RAMs to store ready state data for a plurality of instructions in an instruction block. The instruction scheduler further includes a plurality of queues that store ready state data for the processor and sends dependency information to ready determination logic on a first in/first out basis. The instruction scheduler selects one or more of the ready instructions to be issued and executed by the block-based processor.

Abstract: Populating cache of a virtual server. A data record is generated that is associated with a first virtual server. A set of data is saved that describes data in a cache that is associated with the first virtual server. In response to either (i) a failover of the first virtual server or (ii) a migration request for the first virtual server, a cache of a second virtual server is populated based on the set of data.

Abstract: A streaming ingest platform can improve latency and expense issues related to uploading data into a cloud data system. The streaming ingest platform can organize the data to be ingested into per-table chunks and per-account blobs. This data may be committed and may be made available for query processing before it is ingested into the target source tables. This significantly improves latency issues. The streaming ingest platform can also accommodate uploading data from various sources with different processing and communication capabilities, such as Internet of Things (IOT) devices.

Abstract: Embodiments may include systems and methods for performing remote memory operations in a shared memory address space. An apparatus includes a first network controller coupled to a first processor core. The first network controller processes a remote memory operation request, which is generated by a first memory coherency agent based on a first memory operation for an application operating on the first processor core. The remote memory operation request is associated with a remote memory address that is local to a second processor core coupled to the first processor core. The first network controller forwards the remote memory operation request to a second network controller coupled to the second processor core. The second processor core and the second network controller are to carry out a second memory operation to extend the first memory operation as a remote memory operation. Other embodiments may be described and/or claimed.

Abstract: An apparatus and method are provided for managing a cache. The cache is arranged to comprise a plurality of cache sections, where each cache section is powered independently of the other cache sections in the plurality of cache sections, and the apparatus has power control circuitry to control power to each of the cache sections. The power control circuitry is responsive to a trigger condition indicative of an ability to operate the cache in a power saving mode, to perform a latency evaluation process to determine a latency indication for each of the cache sections, and to control which of a subset of the cache sections to power off in dependence on the latency indication. This can allow the power consumption savings realised by turning off one or more cache sections to be optimised to take into account the current system state.

Abstract: A framework in a cloud network that may allow for debugging at multiple vantage points at different layers (e.g., layer 2, layer 3, etc.). The methods may provide tracer or measurement services that filter, capture, or forward flows that may include packets, calls, or protocols to look for particular signatures.

Abstract: An apparatus has first processing circuitry and second processing circuity. The second processing circuitry has at least one hardware mechanism providing a greater level of fault protection or fault detection than is provided for the first processing circuitry. Coherency control circuitry controls access to data from at least part of a shared address space by the first and second processing circuitry according to an asymmetric coherency protocol in which a local-only update of data in a local cache of the first processing circuitry is restricted in comparison to a local-only update of data in a local cache of the second processing circuitry.

Abstract: A data processing system includes at least one processing unit and a memory controller coupled to a system memory. The processing unit includes a processor core and a cache memory including an arithmetic logic unit (ALU). The cache memory is configured to receive, from the processor core, an atomic memory operation (AMO) request specifying a target address of a data granule to be updated by an AMO and a location indication. Based on the location indication having a first setting, the AMO indicated by the AMO request is performed in the cache memory utilizing the ALU. Based on the location indication having a different second setting, the cache memory issues the AMO request to the memory controller to cause the AMO to be performed at the memory controller.

Abstract: Aspects of the present disclosure provide various apparatus, devices, systems and methods for dynamically configuring a cache partition in a solid state drive (SSD). The SSD may include non-volatile memory (NVM) that can be configured to store a different number of bits per cell. The NVM is partitioned into a cache partition and a storage partition, and the respective sizes of the partitions is dynamically changed based on a locality of data (LOD) of the access pattern of the NVM.

Abstract: A cache is shared by a first and second processor, and is divided into a first cache portion corresponding to a first requestor identifier (ID) and a second cache portion corresponding to a second requestor ID. The first cache portion is accessed in response to memory access requests associated with the first requestor ID, and the second cache portion is accessed in response to memory access requests associated with the second requestor ID. A memory controller communicates with a shared memory, which is a backing store for the cache. A corresponding requestor ID is received with each memory access request. Each memory access request includes a corresponding access address identifying a memory location in the shared memory and a corresponding index portion, wherein each corresponding index portion selects a set in a selected cache portion of the first and second cache portions selected based on the received corresponding requestor ID.

Abstract: An example memory system may include a central processing unit (CPU) comprising a CPU cache, a storage class memory, a volatile memory and a memory controller. The memory controller is to store, in the storage class memory, a first cache line including first data and a first directory tag corresponding to the first data. The memory controller is to further store, in the storage class memory, a second cache line including second data and a second directory tag corresponding to the second data. The memory controller is to store, in the volatile memory, a third cache line that comprises the first directory tag and the second directory tag, the third cache line excluding the first data and the second data.

Abstract: Techniques process data. The techniques involve determining priority of a plurality of cores of a processor based on metadata stored in a plurality of queues associated with the plurality cores, respectively, the metadata being related to data blocks to be processed that are associated with the respective cores, and the metadata in each of the queues being sorted by arrival times of the respective data blocks to be processed. The techniques further involve storing core identifiers of the plurality of cores into a cache by an order of the priorities. By means of at least some of the above techniques, quick insertion of metadata can be realized through multiple queues and the efficiency of determining data blocks to be processed is improved based on sorting of the cores.

Abstract: A system for allocating memory (e.g., heap) in multi-core processors is provided. In some implementations, the system performs operations comprising receiving, at a shared cache having a plurality of segments, a first data allocation including a plurality of data blocks, and allocating at least a first and second data block from the first allocation. First and second segments in the shared cache can each comprise a plurality of data slots (e.g., of equal length). Allocating the first and second data blocks can include storing the first data block in a data slot of the first segment and storing the second data block in a data slot of the second segment. The plurality of data slots which do not contain data may contain padding, and/or the data slots to which the first and second data blocks are allocated are not adjacent. Related systems, methods, and articles of manufacture are also described.

Abstract: The present disclosure includes apparatuses and methods for cache invalidate. An example apparatus comprises a bit vector capable memory device and a channel controller coupled to the memory device. The channel controller is configured to cause a bulk invalidate command to be sent to a cache memory system responsive to receipt of a bit vector operation request.

Abstract: A memory system includes a plurality of nonvolatile memory devices sharing a communication line; and a controller including a buffer and a core, and suitable for controlling the nonvolatile memory devices through the communication line, wherein the core determines a type of a plurality of read requests for the nonvolatile memory devices, and sets a usable size of the buffer depending on the type.

Abstract: Provided is a communication apparatus and a base station. The apparatus includes a clock management resource pool and a power management resource pool, and further includes at least one of: a baseband resource pool, a general-purpose computing resource pool, or a network exchange processing resource pool. The baseband resource pool includes at least one baseband processing unit, the general-purpose computing resource pool includes at least one computing unit, the clock management resource pool includes at least one clock management unit, the network exchange processing resource pool includes at least one network exchange processing unit, and the power management resource pool includes at least one power management unit.

Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.

Abstract: Facilitating processing in a computing environment. A request to access a cache of the computing environment is obtained from a transaction executing on a processor of the computing environment. Based on obtaining the request, a determination is made as to whether a tracking set to be used to track cache accesses is to be updated. The tracking set includes a read set to track read accesses of at least a selected portion of the cache and a write set to track write accesses of at least the selected portion of the cache. The tracking set is assigned to the transaction, and another transaction to access the cache has another tracking set assigned thereto. The tracking set assigned to the transaction is updated based on the determining indicating the tracking set is to be updated.

Abstract: A main processor 4 executes a main program and has an associated cache memory 6. Event detection circuitry 12 detects events consequent upon execution of the main program and indicative of data to be used by the main processor. One or more programmable further processors 16, 18 is triggered to execute a further program by the events detected by the event detection circuitry 12. Prefetch circuitry 28 is responsive to the further program executed by the one or more programmable further processors to trigger prefetching of the data to be used by the main processor to the cache memory.

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

Abstract: Options for handling write operations may be selected based on a determined probability that a read operation for a portion of data will occur while the data portion is still in an I/O cache as a result of a write operation. As used herein, a “read-after-write event (“RAW”) is an occurrence of a read operation for a portion of data while the data portion is still in an I/O cache as a result of a write operation. The probability of a RAW may be determined by applying Bayesian inference, and may include applying exponential smoothing to calculations made on historical I/O information so that more recent I/O events have greater weight in determining RAW probability. Based on the determined RAW probability, write data may either be journaled in a write journal or written to a cache slot and de-staged to a physical storage device as part of write-in-place processing.

Abstract: An apparatus includes a first database, a memory, and first and second processors. The first database stores a list including a first identifier assigned to the first processor and a second identifier assigned to the second processor. The processors each randomly shuffle a copy of the list and place the first element of their shuffled copy in a third list. Each processor further determines that the first identifier appears a first number of times and the second identifier appears a second number of times in the third list, the first number greater than the second number. In response to determining that the first number is greater than the second number, the first processor copies data stored in a second database into the memory and sets a flag to true, while the second processor determines that the flag is set to true and accesses the data copy stored in the memory.

Abstract: A host of a storage system is coupled to multiple SSDs. Each SSD is configured with a migration cache, and each SSD corresponds to one piece of access information. The host obtains migration data information of to-be-migrated data in a source SSD, determines a target SSD, and sends a read instruction carrying information about to-be-migrated data and the target SSD to the source SSD. The source SSD reads a data block according to the read instruction from a flash memory of the source SSD into a migration cache of the target SSD. After a read instruction is completed by the SSD, the host sends a write instruction to the target SSD to instruct the target SSD to write the data block in the cache of the target SSD to a flash memory of the target SSD.

Abstract: Data processing circuitry comprises a cache memory to cache a subset of data elements from a main memory; a processing element to execute program code to access data elements having respective memory addresses, the processing element being configured to access the data elements in the cache memory and, in the case of a cache miss, to fetch the data elements from the main memory; prefetch circuitry, responsive to an access to a current data element, to initiate prefetching into the cache memory of a data element at a memory address defined by a current offset value relative to the address of the current data element; and offset value selection circuitry comprising: an address table to store memory addresses for which a data element accessed by the processing element resulted in a cache miss or an access to a previously prefetched data element; and detector circuitry to detect, for each of a group of candidate offset values, one or more respective metrics representing a proportion of a set of data element acces

Abstract: Data processing circuitry comprises a cache memory to cache a subset of data elements from a main memory; a processing element to execute program code to access data elements having respective memory addresses, the processing element being configured to access the data elements in the cache memory and, in the case of a cache miss, to fetch the data elements from the main memory; prefetch circuitry, responsive to an access to a current data element, to initiate prefetching into the cache memory of a data element at a memory address defined by a current offset value relative to the address of the current data element; offset value selection circuitry comprising: an address table to store memory addresses for which a data element accessed by the processing element resulted in a cache miss or an access to a previously prefetched data element; detector circuitry to detect, for each of a group of candidate offset values, one or more respective metrics representing a proportion of a set of data element accesses whic

Abstract: A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.

Abstract: An example embodiment may involve receiving, by a web server device and from a client device, a request for web content. The example embodiment may also involve determining, by the web server device, that a web document includes a script containing a synchronous client-side function call matching pre-determined criteria. The web content may be at least in part derivable from the web document. The example embodiment may also involve executing, by the web server device, the synchronous client-side function call to obtain output data. The example embodiment may also involve modifying, by the web server device, the web document to include the output data in a data structure associated with the synchronous client-side function call. The example embodiment may also involve transmitting, by the web server device and to the client device, the web document as modified.

Abstract: The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.