Abstract: A memory system includes a plurality of nonvolatile memory devices sharing a communication line; and a controller including a buffer and a core, and suitable for controlling the nonvolatile memory devices through the communication line, wherein the core determines a type of a plurality of read requests for the nonvolatile memory devices, and sets a usable size of the buffer depending on the type.

Abstract: Provided is a communication apparatus and a base station. The apparatus includes a clock management resource pool and a power management resource pool, and further includes at least one of: a baseband resource pool, a general-purpose computing resource pool, or a network exchange processing resource pool. The baseband resource pool includes at least one baseband processing unit, the general-purpose computing resource pool includes at least one computing unit, the clock management resource pool includes at least one clock management unit, the network exchange processing resource pool includes at least one network exchange processing unit, and the power management resource pool includes at least one power management unit.

Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.

Abstract: Facilitating processing in a computing environment. A request to access a cache of the computing environment is obtained from a transaction executing on a processor of the computing environment. Based on obtaining the request, a determination is made as to whether a tracking set to be used to track cache accesses is to be updated. The tracking set includes a read set to track read accesses of at least a selected portion of the cache and a write set to track write accesses of at least the selected portion of the cache. The tracking set is assigned to the transaction, and another transaction to access the cache has another tracking set assigned thereto. The tracking set assigned to the transaction is updated based on the determining indicating the tracking set is to be updated.

Abstract: A main processor 4 executes a main program and has an associated cache memory 6. Event detection circuitry 12 detects events consequent upon execution of the main program and indicative of data to be used by the main processor. One or more programmable further processors 16, 18 is triggered to execute a further program by the events detected by the event detection circuitry 12. Prefetch circuitry 28 is responsive to the further program executed by the one or more programmable further processors to trigger prefetching of the data to be used by the main processor to the cache memory.

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

Abstract: Options for handling write operations may be selected based on a determined probability that a read operation for a portion of data will occur while the data portion is still in an I/O cache as a result of a write operation. As used herein, a “read-after-write event (“RAW”) is an occurrence of a read operation for a portion of data while the data portion is still in an I/O cache as a result of a write operation. The probability of a RAW may be determined by applying Bayesian inference, and may include applying exponential smoothing to calculations made on historical I/O information so that more recent I/O events have greater weight in determining RAW probability. Based on the determined RAW probability, write data may either be journaled in a write journal or written to a cache slot and de-staged to a physical storage device as part of write-in-place processing.

Abstract: An apparatus includes a first database, a memory, and first and second processors. The first database stores a list including a first identifier assigned to the first processor and a second identifier assigned to the second processor. The processors each randomly shuffle a copy of the list and place the first element of their shuffled copy in a third list. Each processor further determines that the first identifier appears a first number of times and the second identifier appears a second number of times in the third list, the first number greater than the second number. In response to determining that the first number is greater than the second number, the first processor copies data stored in a second database into the memory and sets a flag to true, while the second processor determines that the flag is set to true and accesses the data copy stored in the memory.

Abstract: A host of a storage system is coupled to multiple SSDs. Each SSD is configured with a migration cache, and each SSD corresponds to one piece of access information. The host obtains migration data information of to-be-migrated data in a source SSD, determines a target SSD, and sends a read instruction carrying information about to-be-migrated data and the target SSD to the source SSD. The source SSD reads a data block according to the read instruction from a flash memory of the source SSD into a migration cache of the target SSD. After a read instruction is completed by the SSD, the host sends a write instruction to the target SSD to instruct the target SSD to write the data block in the cache of the target SSD to a flash memory of the target SSD.

Abstract: Data processing circuitry comprises a cache memory to cache a subset of data elements from a main memory; a processing element to execute program code to access data elements having respective memory addresses, the processing element being configured to access the data elements in the cache memory and, in the case of a cache miss, to fetch the data elements from the main memory; prefetch circuitry, responsive to an access to a current data element, to initiate prefetching into the cache memory of a data element at a memory address defined by a current offset value relative to the address of the current data element; and offset value selection circuitry comprising: an address table to store memory addresses for which a data element accessed by the processing element resulted in a cache miss or an access to a previously prefetched data element; and detector circuitry to detect, for each of a group of candidate offset values, one or more respective metrics representing a proportion of a set of data element acces

Abstract: Data processing circuitry comprises a cache memory to cache a subset of data elements from a main memory; a processing element to execute program code to access data elements having respective memory addresses, the processing element being configured to access the data elements in the cache memory and, in the case of a cache miss, to fetch the data elements from the main memory; prefetch circuitry, responsive to an access to a current data element, to initiate prefetching into the cache memory of a data element at a memory address defined by a current offset value relative to the address of the current data element; offset value selection circuitry comprising: an address table to store memory addresses for which a data element accessed by the processing element resulted in a cache miss or an access to a previously prefetched data element; detector circuitry to detect, for each of a group of candidate offset values, one or more respective metrics representing a proportion of a set of data element accesses whic

Abstract: A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.

Abstract: An example embodiment may involve receiving, by a web server device and from a client device, a request for web content. The example embodiment may also involve determining, by the web server device, that a web document includes a script containing a synchronous client-side function call matching pre-determined criteria. The web content may be at least in part derivable from the web document. The example embodiment may also involve executing, by the web server device, the synchronous client-side function call to obtain output data. The example embodiment may also involve modifying, by the web server device, the web document to include the output data in a data structure associated with the synchronous client-side function call. The example embodiment may also involve transmitting, by the web server device and to the client device, the web document as modified.

Abstract: The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.

Abstract: A security agent can implement a least recently used (LRU)-based approach to suppressing events observed on a computing device. The security agent may observe events that occur on a computing device. These observed events may then be inserted into a LRU table that tracks, for a subset of the observed events maintained in the LRU table, a rate-based statistic for multiple event groups in which the subset of the observed events are classified. In response to a value of the rate-based statistic for a particular event group satisfying a threshold for the LRU-table, observed events that are classified in the event group can be sent to a remote security system with suppression by refraining from sending, to the remote security system, at least some of the observed events in the event group. The security agent may cease suppression after the rate-based statistic falls below a predetermined threshold level.

Abstract: A method is described for enabling inter-process communication between a first application and a second application, the first application running within a first virtual machine (VM) in a host and the second application running within a second VM in the host, The method includes receiving a request to attach a shared region of memory to a memory allocation, identifying a list of one or more physical memory pages defining the shared region that corresponds to the handle, and mapping guest memory pages corresponding to the allocation to the physical memory pages. The request may be received by a framework from the second application and includes a handle that uniquely identifies the shared region of memory as well as an identification of at least one guest memory page corresponding to the memory allocation.

Abstract: Certain embodiments disclosed herein reduce or eliminate a communication bottleneck at the storage manager by reducing communication with the storage manager while maintaining functionality of an information management system. In some implementations, a client obtains information for enabling a secondary storage job (e.g., a backup or restore) from a storage manager and stores the information (which may be referred to as job metadata) in a local cache. The client may then reuse the job metadata for multiple storage jobs reducing the frequency of communication with the storage manager. When a configuration of the information management system changes, or the availability of resources changes, the storage manager can push updates to the job metadata to the clients. Further, a client can periodically request updated job metadata from the storage manager ensuring that the client does not rely on out-of-date job metadata.

Abstract: Providing interrupt service routine (ISR) prefetching in multicore processor-based systems is disclosed. In one aspect, a multicore processor-based system provides an ISR prefetch control circuit communicatively coupled to an interrupt controller and a plurality of instruction fetch units (IFUs) of a corresponding plurality of processor elements (PEs). Upon receiving an interrupt directed to a target PE of the plurality of PEs, the interrupt controller provides an interrupt request (IRQ) identifier to the ISR prefetch control circuit. Based on the IRQ identifier, the ISR prefetch control circuit fetches an ISR pointer to an ISR corresponding to the IRQ identifier. The ISR prefetch control circuit next selects a prefetch PE of the plurality of PEs to perform a prefetch operation to retrieve the ISR on behalf of the target PE, and provides an ISR prefetch request, including the ISR pointer, to an IFU of the prefetch PE.

Abstract: Graphics processing systems and methods are described. For example, one embodiment of a graphics processing apparatus comprises a graphics processing unit (GPU), the GPU including an on-die cache and a cache configuration circuitry to dynamically configure the on-die cache for a plurality of contexts executed by the GPU. The cache configuration block is to receive a cache configuration request, the cache configuration request including context-specific cache requirements for a new context, and determine a priority associated with the context-specific cache requirements. The CCB can compare the context-specific cache requirements with pre-existing cache requirements based on the priority, and reallocate the cache based on the context-specific cache requirements and the priority.

Abstract: Techniques and mechanisms for providing a shared memory which spans an interconnect fabric coupled between compute nodes. In an embodiment, a field-programmable gate array (FPGA) of a first compute node requests access to a memory resource of another compute node, where the memory resource is registered as part of the shared memory. In a response to the request, the first FPGA receives data from a fabric interface which couples the first compute node to an interconnect fabric. Circuitry of the first FPGA performs an operation, based on the data, independent of any requirement that the data first be stored to a shared memory location which is at the first compute node. In another embodiment, the fabric interface includes a cache agent to provide cache data and to provide cache coherency with one or more other compute nodes.

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

Abstract: A data processing apparatus includes receiving circuitry to receive a snoop request sent by a source node in respect of requested data and transmitting circuitry. Cache circuitry caches at least one data value. The snoop request includes an indication as to whether the requested data is to be returned to the source node and when the at least one data value includes the requested data, the transmitting circuitry transmits a response to the source node including said requested data, in dependence on said indication.

Abstract: In an approach to detection of co-location of container services, a method may include receiving, by a first program in a first cloud container on a first host, a bit string over a side channel within a trial period of time. The method may also include determining whether a key corresponding to the bit string matches a pre-determined key corresponding to a second program in a second cloud container. The method may further include determining whether the second cloud container is located on the first host based, at least in part, on whether the key corresponding to the bit string matches the pre-determined key. The side channel may include a first resource on the first host that is accessible by cloud containers located on the first host and the bit string is received by monitoring the first resource for activity indicative of bit values.

Abstract: Methods and apparatus for memory management are described. In a disclosed embodiment, a system has a first and a second processor, with each processor able to access a memory system. A first work unit is received for execution by the first processor, with the memory system being accessed. A second work unit is generated for execution by a second processor upon execution of a first work unit. Only after the memory system is updated does processing of the second work unit by the second processor occur. This work unit message based ordering provides relay consistency for memory operations of multiple processors.

Abstract: Some embodiments provide intelligent predictive stream caching for live, linear, or video-on-demand streaming content using prefetching, segmented caching, and request clustering. Prefetching involves retrieving streaming content segments from an origin server prior to the segments being requested by users. Prefetching live or linear streaming content segments involves continually reissuing requests to the origin until the segments are obtained or a preset retry duration is completed. Prefetching is initiated in response to a first request for a segment falling within a particular interval. Request clustering commences thereafter. Subsequent requests are queued until the segments are retrieved. Segmented caching involves caching segments for one particular interval. Segments falling within a next interval are not prefetched until a first request for one such segment in the next interval is received.

Abstract: Described herein are embodiments of asymmetric memory management to enable high bandwidth accesses. In embodiments, a high bandwidth cache or high bandwidth region can be synthesized using the bandwidth capabilities of more than one memory source. In one embodiment, memory management circuitry includes input/output (I/O) circuitry coupled with a first memory and a second memory. The I/O circuitry is to receive memory access requests. The memory management circuitry also includes logic to determine if the memory access requests are for data in a first region of system memory or a second region of system memory, and in response to a determination that one of the memory access requests is to the first region and a second of the memory access requests is to the second region, access data in the first region from the cache of the first memory and concurrently access data in the second region from the second memory.

Abstract: Systems and methods for retrieving a set of ordered items from a distributed database. A plurality of ordered items may be stored at a cache. The plurality of ordered items may have a length of N+B at a first instant in time. A first instruction to delete a first item of the plurality of ordered items may be received. A second instruction to add a second item to the plurality of ordered items may be received. The first instruction and the second instruction may be stored in a change log. A request for the first N items of the plurality of ordered items may be received. The first instruction may be executed by deleting the first item from the plurality of ordered items. The second instruction may be executed by adding the second item to the plurality of ordered items. The first N items of the plurality of ordered items may be sent in response to the request.

Abstract: A system, computer-readable storage device and method relate to a local stream storage device of a local proxy that caches streams of data transmitted to a remote proxy. The method includes caching, in the local stream storage device4 of the local proxy, a stream of data transmitted over a wide area network to the remote proxy, wherein the stream is stored in a continuous manner, to yield a cached stream. The method includes comparing a flow of data received from a device with the cached stream to determine whether a portion of the flow of data has been previously transmitted to the remote proxy and, when the portion of the flow has been previously transmitted to the remote proxy, transmitting a message to the remote proxy to indicate that the portion of the flow of data has been transmitted previously to the remote proxy.

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

Abstract: A multi-core CPU includes a Last-Level Cache (LLC) interconnected with a plurality of cores. The LLC may include a shared portion and a private portion. The shared portion may be shared by the plurality of cores. The private portion may be connected to a first core of the plurality of cores and may be exclusively assigned to the first core. The first core may be configured to initiate a data access request to access data stored in the LLC and initiate a data access request to access data stored in the LLC. The first core may route the data access request to the private portion based on the determination that the data access request is the TLS type of access request and route the data access request to the shared portion based on the determination that the data access request is not the TLS type of access request.

Abstract: A network-on-chip and a corresponding method are provided. The network-on-chip includes at least one bufferless ring network in at least one dimension of the network-on-chip. At least one bufferless ring network includes multiple routing nodes, and at least one of the multiple routing nodes is a switching node. Two bufferless ring networks in different dimensions may intersect. The two bufferless ring networks exchange data by using switching nodes. A dedicated slot and a public slot are configured in each bufferless ring network. Only one switching node has permission to use a dedicated slot at a same moment in each bufferless ring network, the permission to use the dedicated slot is transferred successively between switching nodes in each bufferless ring network. The permission to use the dedicated slot is transferred after transmission of data in the dedicated slot is completed.

Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.

Abstract: A mechanism called time-deterministic replay (TOR) that can reproduce the execution of a program, including its precise timing. Without TOR, reproducing the timing of an execution is difficult because there are many sources of timing variability. TOR uses a combination of techniques to either mitigate or eliminate most of these sources of variability. Using a prototype implementation of TOR in a Java Virtual Machine, we show it is possible to reproduce the timing to within 1.85% of the original execution. A study of one of the applications of TOR is described: the detection of a covert timing channel. Timing channels can be used to exfiltrate information from a compromised machine by subtly varying timing of the machine's outputs, TOR can detect this variation. Unlike prior solutions, which generally look for a specific type of timing channel, our approach can detect a wide variety of channels with high accuracy.

Abstract: Techniques for using a cache to accelerate virtual machine (VM) I/O are provided. In one embodiment, a host system can intercept an I/O request from a VM running on the host system, where the I/O request is directed to a virtual disk residing on a shared storage device. The host system can then process the I/O request by accessing a cache that resides on one or more cache devices directly attached to the host system, where the accessing of the cache is transparent to the VM.

Abstract: A database management system (DBMS) generates a query execution plan including information representing one or more database (DB) operations necessary for executing a query and executes the query based on the query execution plan. In the execution of the query, the DBMS dynamically generates a task for executing a DB operation and executes the dynamically generated task. The DBMS executes a task in a plurality of threads executed by a processor core.

Abstract: A storage method and device for a solid-state drive is provided in embodiments of the present disclosure. The method includes: configuring a checkpoint drive and a cache drive; backing up data blocks from a data drive into the checkpoint drive; and in response to the data drives being corrupted, writing into a further data drive part of the data blocks backed up into the checkpoint drive and part of data blocks in the cache drive. The number of required SSD drives can be significantly reduced with the method and device without losing the data restoration capability. In addition, the degrading performance can also be maintained at a relatively high level.

Abstract: A congestion controller may be configured to control traffic on an interconnect between a higher level cache and a lower level cache. The lower level cache may also be coupled to a main memory. The congestion controller may be configured to reduce congestion on the interconnect by blocking transactions that include writing of data to the lower level cache if the data has not been modified relative to a copy of the data in the main memory. The congestion controller may also be configured to control the traffic by blocking certain transactions in a controlled manner for traffic shaping or for performance features.

Abstract: A data storage device includes a filter, a central processing unit (CPU), a first memory configured to store a page, a second memory, and a page type analyzer configured to analyze a type of the page output from the first memory and to transmit an indication signal to the CPU according to an analysis result. According to control of the CPU that operates based on the indication signal, the filter passes the page to the second memory or filters each row in the page, and transmits first filtered data to the second memory.

Abstract: A storage control apparatus includes a cache memory, and a processor configured to access to a first area of the cache memory in accordance with a command, generate a first processing report identifying the first area, input the first processing report to a processing report queue when a plurality of second processing reports each of which identifies the first area are not stored in the processing report queue, execute management list update processing in which the access to the first area is recorded in a management list in accordance with the first processing report, identify data to be deleted from the cache memory in accordance with the management list, and not to input the first processing report to the processing report queue when the plurality of second processing reports are stored in the processing report queue.

Abstract: In an embodiment, a prefetch circuit may implement prefetch “boosting” to reduce the cost of cold (compulsory) misses and thus potentially improve performance. When a demand miss occurs, the prefetch circuit may generate one or more prefetch requests. The prefetch circuit may monitor the progress of the demand miss (and optionally the previously-generated prefetch requests as well) through the cache hierarchy to memory. At various progress points, if the demand miss remains a miss, additional prefetch requests may be launched. For example, if the demand miss accesses a lower level cache and misses, additional prefetch requests may be launched because the latency avoided in prefetching the additional cache blocks is higher, which may over ride the potential that the additional cache blocks are incorrectly prefetched.

Abstract: In one embodiment, a processor includes: a plurality of cores each to independently execute instructions; a shared cache memory coupled to the plurality of cores and having a plurality of clusters each associated with one or more of the plurality of cores; a plurality of cache activity monitors each associated with one of the plurality of clusters, where each cache activity monitor is to monitor one or more performance metrics of the corresponding cluster and to output cache metric information; a plurality of thermal sensors each associated with one of the plurality of clusters and to output thermal information; and a logic coupled to the plurality of cores to receive the cache metric information from the plurality of cache activity monitors and the thermal information and to schedule one or more threads to a selected core based at least in part on the cache metric information and the thermal information for the cluster associated with the selected core. Other embodiments are described and claimed.

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

Abstract: A cache system is configurable to trade power consumption for cache access latency. When it is desired for a system with a cache to conserve dynamic power, the lookup of accesses (e.g., snoops) to cache tag ways is serialized to perform one (or less than all) tag way access per clock (or even slower). Thus, for an N-way set associative cache, instead of performing a lookup/comparison on the N tag ways in parallel, the lookups are performed one tag way at a time. This take N times more cycles thereby reducing the access/snoop bandwidth by a factor of N. However, the power consumption of the serialized access when compared to ‘all parallel’ accesses/snoops is reduced.

Abstract: A computer-readable recording medium storing an information processing program for causing a computer to execute a process, the process includes: acquiring a cache memory size allocated to each process within an application program; acquiring a cash miss ratio for a process executed using an allocated cache memory size; correcting a cache memory size to be allocated to the process based on an acquired cache miss ratio; acquiring a first cache memory size allocated to the process after the correcting is performed; acquiring a first performance value when the process is executed using the first cache memory size; acquiring a second cache memory size which is allocated to the process later than the first cache memory size; acquiring a second performance value when the process is executed using the second cache memory size; and correcting the second cache memory size based on the first performance value and the second performance value.

Abstract: The present invention relates to a distributed processing system having a master node and a plurality of worker nodes. Each worker node has an assigned identifier. A worker node caches in its own memory first output data, which is the result of the execution of a first task, and copies said first output data to another worker node. The master node selects, on the basis of the identifier information of the first worker node, a worker node to which to assign a second task, wherein the first output data is used as input data.

Abstract: Methods determine a capacity-forecast model based on historical capacity metric data and historical business metric data. The capacity-forecast model may be to estimate capacity requirements with respect to changes in demand for the data center customer's application program. The capacity-forecast model provides an analytical “what-if” approach to reallocating data center resources in order to satisfy projected business level expectations of a data center customer and calculate estimated capacities for different business scenarios.

Abstract: In one general embodiment, a computer-implemented method includes receiving at a first system a request for data, searching one or more local buffers within the first system for the requested data, determining whether the requested data is located within an additional buffer of an additional system in communication with the first system, in response to determining that the one or more local buffers within the first system do not contain the requested data, receiving the requested data by the first system from the additional buffer of the additional system, in response to determining that the requested data is located within the additional buffer of the additional system, and retrieving the requested data from a data disk within the first system, in response to determining that the requested data is not located within the additional buffer of the additional system.

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

Abstract: A plurality of processing entities of a processor complex is maintained, wherein each processing entity has a local cache and the processor complex has a shared cache and a shared memory. One of the plurality of processing entities is allocated for execution of a critical task. In response to the allocating of one of the plurality of processing entities for the execution of the critical task, other processing entities of the plurality of processing entities are folded. The critical task utilizes the local cache of the other processing entities that are folded, the shared memory, and the shared cache, in addition to the local cache of the processing entity allocated for the execution of the critical task.