Least Recently Used Patents (Class 711/136)
  • Patent number: 11144639
    Abstract: Provided are a computer program product, system, and method for determining whether to destage write data in cache to storage based on whether the write data has malicious data. Write data for a storage is cached in a cache. A determination is made as to whether the write data in the cache comprises random data according to a randomness criteria. The write data in the cache to the storage in response to determining that the write data does not comprise random data according to the randomness criteria. The write data is processed as malicious data after determining that the write data comprises random data according to the randomness criteria.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Carol S. Mellgren, John G. Thompson
  • Patent number: 11144475
    Abstract: A computer program product, system, and method for managing adding of accessed tracks in cache to a most recently used end of a cache list. A cache list for the cache has a least recently used (LRU) end and a most recently used (MRU) end. Tracks in the cache are indicated in the cache list. A track in the cache indicated on the cache list is accessed. A determination is made as to whether a track cache residency time since the accessed track was last accessed while in the cache list is within a region of lowest track cache residency times. A flag is set for the accessed track indicating to indicate the track at the MRU end in response to determining that the track cache residency time of the accessed track is within the region of lowest track cache residency times. The accessed track remains at a current position in the cache list before being accessed after setting the flag.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Patent number: 11138118
    Abstract: The sizes of cache partitions, in a partitioned cache, are dynamically adjusted by determining, for each request, how many cache misses will occur in connection with implementing the request against the cache partition. The cache partition associated with the current request is increased in size by the number of cache misses and one or more other cache partitions is decreased in size causing cache evictions to occur from the other cache partitions rather than from the current cache partition. The other cache partitions, that are to be decreased in size, may be determined by ranking the cache partitions according to frequency of use and selecting the least frequently used cache partition to be reduced in size.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: October 5, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Hugo de Oliveira Barbalho, Jonas Furtado Dias, Vinícius Michel Gottin
  • Patent number: 11119679
    Abstract: Data blocks of a memory sub-system that have been accessed by a host system can be determined. An access pattern associated with the data blocks by the host system can be determined. A spatial characteristic for each respective pair of the data blocks of the memory sub-system can be received. A data graph can be generated with nodes that are based on the access pattern associated with the data blocks of the memory sub-system and edge values between the nodes that are based on the spatial characteristic for each respective pair of the data blocks of the memory sub-system.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Anirban Ray, Samir Mittal, Gurpreet Anand
  • Patent number: 11119921
    Abstract: State machine generation for a multi-buffer electronic system can include receiving, using a processor, a user input specifying a reader policy and a number of a plurality of buffers used by a reader and a writer of the multi-buffer electronic system. A state machine can be generated as a data structure. The state machine has a plurality of states determined based on the number of the plurality of buffers and the reader policy. The state machine allocates different buffers of the plurality of buffers to the reader in temporally accurate order over time. Each state can specify an allocation from the plurality of buffers to the reader and the writer. A state machine description including one or more program code components can be generated, where the one or more program components may be used in an implementation of the reader and an implementation of the writer.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: September 14, 2021
    Assignee: Xilinx, Inc.
    Inventor: Uday M. Hegde
  • Patent number: 11070650
    Abstract: A method, computer program product, and a computing system are provided for de-duplicating remote procedure calls at a client. In an implementation, the method may include generating a plurality of local pending remote procedure calls. The method may also include identifying a set of duplicate remote procedure calls among the plurality of remote procedure calls. The method may also include associating each remote procedure call within the set of duplicate remote procedure calls with one another. The method may also include executing a remote procedure call of the set of duplicate remote procedure calls. The method may further include providing a response for the remote procedure call of the set of duplicate remote procedure calls with the other remote procedure calls of the set of duplicate remote procedure calls.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: John T. Kohl, Shailaja S. Golikeri
  • Patent number: 11049570
    Abstract: A method for dynamically altering a writes-per-day classification of multiple storage drives is disclosed. In one embodiment, such a method monitors, within a storage environment, an amount of overprovisioning utilized by multiple storage drives. Each storage drive has a writes-per-day classification associated therewith. Based on the amount of overprovisioning, the method periodically modifies the writes-per-day classification of the storage drives. The method then reorganizes the storage drives within various storage groups (e.g., RAID arrays, storage tiers, workloads, etc.) based on their writes-per-day classification. For example, the method may place, as much as possible, storage drives of the same writes-per-day classification within the same storage groups. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Karl A. Nielsen, Micah Robison
  • Patent number: 11048667
    Abstract: A method for improving asynchronous data replication between a primary storage system and a secondary storage system is disclosed. In one embodiment, such a method includes monitoring, in a cache of the primary storage system, unmirrored data elements needing to be mirrored, but that have not yet been mirrored, from the primary storage system to the secondary storage system. The method maintains an LRU list designating an order in which data elements are demoted from the cache. The method determines whether a data element at an LRU end of the LRU list is an unmirrored data element. In the event the data element at the LRU end of the LRU list is an unmirrored data element, the method moves the data element to an MRU end of the LRU list. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: June 29, 2021
    Assignees: International Business, Machines Corporation
    Inventors: Gail Spear, Lokesh M. Gupta, Kevin J. Ash, David B. Schreiber, Kyler A. Anderson
  • Patent number: 11030089
    Abstract: A portion of a logical block address to physical block address (“L2P”) translation map may be identified. A last snapshot of the portion of the L2P translation map may be identified. One or more write operations may be determined, where the write operations are associated with logical block addresses of the portion of the L2P translation map. The write operations may have been performed after the last snapshot of the portion of the L2P translation map was stored. An address on the portion of the L2P translation map may be updated by a processing device based on the determined one or more write operations and the last snapshot of the portion of the L2P translation map.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Daniel A. Boals, Byron D. Harris, Karl D. Schuh, Amy L. Wohlschlegel
  • Patent number: 10990541
    Abstract: A controller controls an operation of a semiconductor memory device. The controller includes a cache buffer, a request analyzer, and a cache controller. The cache buffer stores multiple cache data. The request analyzer generates request information including information on a size of read data to be read. The cache controller determines an eviction policy of the multiple cache data, based on the size of the read data in the request information.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: April 27, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Patent number: 10949109
    Abstract: An expansion cartridge (200) and a method for deduplicating the data chunks stored at a client device (100) using the expansion cartridge (200), (300) are claimed herein. As per the invention, the expansion cartridge (200) is attachable, externally, to client devices (100) carrying the electronic data files to be transferred, wherein the expansion cartridge (200) is characterized by a file management component (220), a chunk management component (240), a storage component (260), and a mirroring component (280), and wherein, the expansion cartridge (200) on being attached with the client devices (100) interfaces with a client side data historian (125) and a client side processor (150) in the client device (100) using interfacing options, including without limitation, Small Computer System Interfaces (SCSI), Fibre Channel (FC) Interface, Ethernet Interface, Advanced Technology Attachment (ATA) Interface or a combination thereof.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: March 16, 2021
    Assignee: ARC Document Solutions, LLC
    Inventors: Rahul Roy, Srinivasa Rao Mukkamala, Himadri Majumder, Dipali Bhattacharya
  • Patent number: 10901916
    Abstract: Provided are a computer program product, system, and method for managing adding of accessed tracks to a cache list based on accesses to different regions of the cache list. A cache has a least recently used (LRU) end and a most recently used (MRU) end. A determination is made of a high access region of tracks from the MRU end of the cache list based on a number of accesses to the tracks in the high access region. A flag is set for an accessed track, indicating to indicate the accessed track at the MRU end upon processing the accessed track at the LRU end, in response to the determining the accessed track is in the high access region. After the setting the flag, the accessed track remains at a current position in the cache list before being accessed.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Patent number: 10891167
    Abstract: A method of protecting software in a computer system includes defining a memory fractionation configuration for an application software program in the computer system, fractionating at least one page of the application software program into fractions according to the memory fractionation configuration, and running the application in such a manner that, at any particular point in time when the application is running, at least a first one of the fractions is stored in a manner that is not accessible from a user space or a kernel space of the computer system.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: January 12, 2021
    Assignee: Siege Technologies, LLC
    Inventor: Joseph James Sharkey
  • Patent number: 10872038
    Abstract: A system comprises a memory, a plurality of memory banks, and an organizer. The memory is configured to store elements of a matrix, wherein the elements are distributed into overlapping subgroups and each shares at least one element of the matrix with another overlapping subgroup. The plurality of memory banks is configured to store the overlapping subgroups, wherein the subgroups are distributed among the memory banks using a circular shifted pattern. The organizer is configured to read specific ones of the overlapping subgroups in the plurality of memory banks in a specified pattern associated with transposing the matrix.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: December 22, 2020
    Assignee: Facebook, Inc.
    Inventors: Krishnakumar Narayanan Nair, Ehsan Khish Ardestani Zadeh, Olivia Wu, Yuchen Hao
  • Patent number: 10838870
    Abstract: The described technology is generally directed towards caching and aggregated write operations based on predicted patterns of data transfer operations. According to an embodiment, a system can comprise a memory that can store computer executable components, and a processor that can execute the computer executable components stored in the memory. The components can comprise a pattern identifying component to identify a first pattern of data transfer operations performed on a data store, resulting in an identified first pattern, based on monitored data transfer operations. The components can further comprise a pattern predicting component to predict a second pattern of future data transfer operations performed on the data store, resulting in a predicted second pattern, based on the identified first pattern. The components can further comprise a host adapter to generate a data transfer operation to be performed on the data store based on the predicting the second pattern.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: November 17, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Malak Alshawabkeh, Steven John Ivester, Ramesh Doddaiah, Kaustubh S. Sahasrabudhe
  • Patent number: 10802895
    Abstract: A method and an apparatus for determining a usage level of a memory device to notify a running application to perform memory reduction operations selected based on the memory usage level are described. An application calls APIs (Application Programming Interface) integrated with the application codes in the system to perform memory reduction operations. A memory usage level is determined according to a memory usage status received from the kernel of a system. A running application is associated with application priorities ranking multiple running applications statically or dynamically. Selecting memory reduction operations and notifying a running application are based on application priorities. Alternatively, a running application may determine a mode of operation to directly reduce memory usage in response to a notification for reducing memory usage without using API calls to other software.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: October 13, 2020
    Assignee: Apple Inc.
    Inventors: Matthew G. Watson, James Michael Magee
  • Patent number: 10776275
    Abstract: A method comprises a cache manager receiving reference attributes associated with network data and selecting a replacement data location of a cache to store cache-line data associated with the network data. The replacement data location is selected based on the reference attributes and an order of reference states stored in a replacement stack of the cache. The stored reference states are associated with respective cached-data stored in the cache and based on reference attributes associated with respective cached-data. The reference states are stored in the replacement stack based on a set of the reference attributes and the stored reference states. In response to receiving reference attributes, the cache manager can modify a stored reference state, determine a second order of the state locations, and store a reference state in the replacement stack based on the second order. A system can comprise a network computing element having a cache, a cache manager, and a replacement stack.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brian W. Thompto, Bernard C. Drerup, Mohit S. Karve
  • Patent number: 10761988
    Abstract: Aspects of the present disclosure relate to an apparatus comprising a data array having locality-dependent latency characteristics such that an access to an open unit of the data array has a lower latency than an access to a closed unit of the data array. Set associative cache indexing circuitry determines, in response to a request for data associated with a target address, a cache set index. Mapping circuitry identifies, in response to the index, a set of data array locations corresponding to the index, according to a mapping in which a given unit of the data array comprises locations corresponding to a plurality of consecutive indices, and at least two locations of the set of locations corresponding to the same index are in different units of the data array. Cache access circuitry accesses said data from one of the set of data array locations.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: September 1, 2020
    Assignee: Arm Limited
    Inventors: Radhika Sanjeev Jagtap, Nikos Nikoleris, Andreas Lars Sandberg, Stephan Diestelhorst
  • Patent number: 10691607
    Abstract: Disclosed are a method and a device for increasing the performance of processes through cache splitting in a computing device using a plurality of cores. According to the present invention, a cache splitting method for performing a cache splitting in a computing device comprises the steps of: identifying, among a plurality of processes being executed, a process generating a cache flooding; and controlling the process generating the cache flooding such that the process uses a cache of a limited size.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 23, 2020
    Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: Jinkyu Koo, Hyeonsang Eom, Myung Sun Kim, Hanul Sung
  • Patent number: 10684946
    Abstract: A method may include: partitioning data on an on-chip and/or an off-chip storage medium into different data blocks according to a pre-determined data partitioning principle, wherein data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block; and a data indexing step for successively loading different data blocks to at least one on-chip processing unit according a pre-determined ordinal relation of a replacement policy, wherein the repeated data in a loaded data block being subjected to on-chip repetitive addressing. Data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block, and the data partitioned into the same data block can be loaded on a chip once for storage, and is then used as many times as possible, so that the access is more efficient.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: June 16, 2020
    Assignee: INSTITUTE OF COMPUTING TECHNOLOGY, CHINESE ACADEMY OF SCIENCE
    Inventors: Qi Guo, Tianshi Chen, Yunji Chen
  • Patent number: 10664393
    Abstract: A memory includes a plurality of pages used as a cache area. A processor allocates a first storage resource to a first link indicating a first page group of the plurality of pages, and a second storage resource to a second link indicating a second page group of the plurality of pages. The processor uses the first and the second links, and processes access requests for accessing to the first and the second storage resources, in parallel.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: May 26, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Takuro Kumabe, Motohiro Sakai, Keima Abe
  • Patent number: 10656945
    Abstract: Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of a next sequential instruction. The access intent indicates usage of the operand by one or more instructions subsequent to the next sequential instruction. The computer executes the access intent instruction. The computer obtains the next sequential instruction. The computer executes the next sequential instruction, whose execution comprises, based on the access intent, adjusting one or more cache behaviors for the operand of the next sequential instruction.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christian Jacobi, Chung-Lung Kevin Chum, Timothy J. Slegel, Gustav E. Sittmann, III, Cynthia Sittmann
  • Patent number: 10649901
    Abstract: A set-associative cache memory includes a plurality of ways and a plurality of congruence classes. Each of the plurality of congruence classes includes a plurality of members each belonging to a respective one of the plurality of ways. In the cache memory, a data structure records a history of an immediately previous N ways from which cache lines have been evicted. In response to receipt of a memory access request specifying a target address, a selected congruence class among a plurality of congruence classes is selected based on the target address. At least one member of the selected congruence class is removed as a candidate for selection for victimization based on the history recorded in the data structure, and a member from among the remaining members of the selected congruence class is selected. The cache memory then evicts the victim cache line cached in the selected member of the selected congruence class.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bernard Drerup, Guy L. Guthrie, Jeffrey Stuecheli, Phillip Williams
  • Patent number: 10630530
    Abstract: Embodiments of the present application provide a cache method, the cache method includes: receiving, from the cache core server, information about a Transmission Control Protocol (TCP) flow; determining, according to the information, whether the cache edge server stores content corresponding to the information; sending a migrate-out request to the cache core server based on that the cache edge server stores the content corresponding to the information; receiving a migrate-out response from the cache core server upon the sending of the migrate-out request; performing a TCP connection to user equipment according to the migrate-out response; and reading content corresponding to the connection from storage of the cache edge server according to a byte quantity, sent by the cache core server, of the content, and sending the content to the user equipment.
    Type: Grant
    Filed: June 25, 2017
    Date of Patent: April 21, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zanfeng Yang, Tao Song, Xinyu Ge, Pinhua Zhao, Jianzhong Yu, Bo Zhou, Wentao Wang
  • Patent number: 10621104
    Abstract: Examples herein involve a variable cache. An example variable cache controller obtains cache lines corresponding to accesses of a non-volatile memory of a system, monitors access history of the non-volatile memory, determines a number of distinct objects accessed in the access history during a time period from the object information, and sets a size of a variable cache of the system based on the number of distinct objects accessed in the access history during the time period.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 14, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Pengcheng Li, Dhruva Chakrabarti
  • Patent number: 10621083
    Abstract: A storage system selects from a plurality of physical areas constituting a physical address space as copy source physical areas, one or more non-additionally recordable physical areas each including a fragmented free area, and also selects a recordable physical area as a copy destination physical area. The storage system then writes one or more pieces of live data from the selected one or more copy source physical areas to the free area of the selected copy destination physical area on a per-strip or per-stripe basis, sequentially from the beginning of the free area. If the size of the write target data is such that it is not possible to write the write target data to the free area on a per-strip or per-stripe basis, then the storage system pads the write target data, and writes the padded write target data to the free area on a per-strip or per-stripe basis.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: April 14, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Nakagoe, Akira Yamamoto, Yoshihiro Yoshii
  • Patent number: 10599661
    Abstract: A method includes receiving a first signal and updating a bitmap index responsive to the first signal. The bitmap index includes a plurality of bit strings, where a value stored in a particular location in each of the bit strings indicates whether a corresponding signal associated with a signal source has been received. Updating the bitmap index responsive to the first signal includes updating a first bit of the bitmap index and updating first metadata values stored in the bitmap index, wherein the first metadata values comprise a plurality of sort index values indicating relative ranks of the first bit string relative to other bit strings. The method also includes outputting query results based on a query, wherein the query results identify one or more signals associated with one or more bit strings of the plurality of bit strings and one or more signal sources of a plurality of signal sources, and wherein the query results are sorted according to one of the first metadata values.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: March 24, 2020
    Assignee: Molecula Corp.
    Inventors: Travis Turner, Todd Wesley Gruben, Ben Johnson, Cody Stephen Soyland, Higinio O. Maycotte
  • Patent number: 10547876
    Abstract: A video cache rule generation system for generating cache rules for caching and playing back a video includes an obtaining module, a determining module, an extracting module, a comparing module, and a generating module. The obtaining module obtains URL addresses. The determining module determines whether each URL address belongs to a video URL address according to a media tag library. The extracting module divides a first URL address into chunks and extracts first key chunks from the chunks after division. The comparing module compares each first key chunk with a key chunk subclass, and marks a second key chunk where the second key chunk is found to be different from the key chunk subclass. The generating module generates a cache rule through generating a list of marked key parameter chunks. A video cache rule generation method is also provided.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: January 28, 2020
    Assignee: NANNING FUGUI PRECISION INDUSTRIAL CO., LTD.
    Inventor: Chi-Feng Lee
  • Patent number: 10489148
    Abstract: According to an exemplary embodiment of the present disclosure, disclosed is a method for seamless application version management in a system including a plurality of application servers.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: November 26, 2019
    Assignee: TMAXSOFT CO., LTD.
    Inventors: Junsoo Jeong, Yujeong Ha, Chanpyo Hong
  • Patent number: 10440142
    Abstract: Among other things, this document describes systems, devices, and methods for improving cache efficiency by automatically discovering and updating time to live (TTL) settings for cached content. TTL values define how long content may be served from a cache before the cache should return to origin to verify the freshness of the content. TTL values may be set by an origin server, using an appropriate HTTP header for example, or by manual configuration action, or otherwise. A cache may adjust this TTL value—or generate a TTL value if none is provided, based at least in part on cache performance characteristics and targets, along with an analysis of the history of purge events.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: October 8, 2019
    Assignee: Akamai Technologies, Inc.
    Inventors: Alexandre Menai, Charles Patrick Dublin
  • Patent number: 10430188
    Abstract: Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of a next sequential instruction. The access intent indicates usage of the operand by one or more instructions subsequent to the next sequential instruction. The computer executes the access intent instruction. The computer obtains the next sequential instruction. The computer executes the next sequential instruction, whose execution comprises, based on the access intent, adjusting one or more cache behaviors for the operand of the next sequential instruction.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: October 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christian Jacobi, Chung-Lung Kevin Shum, Timothy J Siegel, Gustav E Sittmann, III
  • Patent number: 10409504
    Abstract: Embodiments of the disclosure provide a method, a computer [program product and apparatus for a soft-switch in a storage system, by setting data in a source of the soft-switch to be read-only and starting a replication process of the data to a destination of the soft-switch in response to a soft-switch request; recording at the source an update operation for the data during the replication process and synchronously recording the update operation into the destination; updating the replicated data at the destination with the synchronously recorded update operation in response to the completion of the replication process; and disabling a data access to the source and enabling a data access to the destination.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: September 10, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Bernie Bo Hu, Bob Biao Yan, Jia Huang, Ming Yue, Adam Yu Zhang
  • Patent number: 10324809
    Abstract: Techniques related to cache recovery for failed database instances are disclosed. A first database instance and a second database instance share a primary persistent storage and a secondary persistent storage. Each database instance stores, in volatile memory, a respective primary cache of a respective set of data stored on the primary persistent storage. Each database instance also stores, in volatile memory, a respective set of header data. Further, each database instance moves the respective set of data from the respective primary cache to a respective secondary cache on the secondary persistent storage. Still further, each database instance stores, on the secondary persistent storage, a respective set of persistent metadata. When the first database instance becomes inoperative, the second database instance retrieves, from the secondary persistent storage, persistent metadata corresponding to data stored in a secondary cache of the first database instance.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: June 18, 2019
    Assignee: Oracle International Corporation
    Inventors: Dungara Ram Choudhary, Yu Kin Ho, Norman Lee, Wilson Wai Shun Chan
  • Patent number: 10320414
    Abstract: This application sets forth methods and apparatus to parallelize data decompression. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Sudhir K. Satpathy, Sanu K. Mathew
  • Patent number: 10311228
    Abstract: A data processing system can use a method of fine-grained address space layout randomization to mitigate the system's vulnerability to return oriented programming security exploits. The randomization can occur at the sub-segment level by randomizing clumps of virtual memory pages. The randomized virtual memory can be presented to processes executing on the system. The mapping between memory spaces can be obfuscated using several obfuscation techniques to prevent the reverse engineering of the shuffled virtual memory mapping.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: June 4, 2019
    Assignee: Apple Inc.
    Inventors: Jacques A. Vidrine, Nicholas C. Allegra, Simon P. Cooper, Gregory D. Hughes
  • Patent number: 10282543
    Abstract: Provided are a computer program product, system, and method for determining whether to destage write data in cache to storage based on whether the write data has malicious data. Write data for a storage is cached in a cache. A determination is made as to whether the write data in the cache comprises random data according to a randomness criteria. The write data in the cache to the storage in response to determining that the write data does not comprise random data according to the randomness criteria. The write data is processed as malicious data after determining that the write data comprises random data according to the randomness criteria.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Carol S. Mellgren, John G. Thompson
  • Patent number: 10261915
    Abstract: A processor architecture which partitions on-chip data caches to efficiently cache translation entries alongside data which reduces conflicts between virtual to physical address translation and data accesses. The architecture includes processor cores that include a first level translation lookaside buffer (TLB) and a second level TLB located either internally within each processor core or shared across the processor cores. Furthermore, the architecture includes a second level data cache (e.g., located either internally within each processor core or shared across the processor cores) partitioned to store both data and translation entries. Furthermore, the architecture includes a third level data cache connected to the processor cores, where the third level data cache is partitioned to store both data and translation entries. The third level data cache is shared across the processor cores. The processor architecture can also include a data stack distance profiler and a translation stack distance profiler.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: April 16, 2019
    Assignee: Board of Regents, The University Of Texas System
    Inventors: Lizy K. John, Yashwant Marathe, Jee Ho Ryoo, Nagendra Gulur
  • Patent number: 10235247
    Abstract: A computer program product, system, and method for generating coded fragments comprises receiving a request to generate a memory snapshot for a virtual machine (VM), copying the VM's memory to generate a memory snapshot, obtaining information about cache structures within the memory snapshot, invalidating one or more of the cache structures and zeroing out corresponding cache data within the memory snapshot, and storing the memory snapshot to storage.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: March 19, 2019
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Assaf Natanzon, Philip Derbeko, Moran Zahavy, Maya Bakshi, Anton Pavlinov
  • Patent number: 10229145
    Abstract: A method, a computer system, and/or a computer program product are disclosed. One computer-implemented method for building a hash table includes dividing a hash table into plural blocks; and dividing each block into plural sub-blocks. A certain sub-block uses a first pattern of association between a key and a location for storing the key. Another sub-block which belongs to the same block having the certain sub-block uses a second pattern which is different from the first pattern. The method may further include building a hash table by using memory blocks in a Field Programmable Gate Array.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Raymond H. Rudy, Takanori Ueda
  • Patent number: 10191849
    Abstract: A cache is sized using an ordered data structure having data elements that represent different target locations of input-output operations (IOs), and are sorted according to an access recency parameter. The cache sizing method includes continually updating the ordered data structure to arrange the data elements in the order of the access recency parameter as new IOs are issued, and setting a size of the cache based on the access recency parameters of the data elements in the ordered data structure. The ordered data structure includes a plurality of ranked ring buffers, each having a pointer that indicates a start position of the ring buffer. The updating of the ordered data structure in response to a new IO includes updating one position in at least one ring buffer and at least one pointer.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: January 29, 2019
    Assignee: VMware, Inc.
    Inventors: Jorge Guerra Delgado, Wenguang Wang
  • Patent number: 10192602
    Abstract: A memory device for storing data is disclosed. The memory device comprises a memory bank comprising a plurality of addressable memory cells configured in a plurality of segments wherein each segment contains N rows per segment, wherein the memory bank comprises a total of B entries, and wherein the memory cells are characterized by having a prescribed word error rate, E. Further, the device comprises a pipeline comprising M pipestages and configured to process write operations of a plurality of data words addressed to a given segment of the memory bank. The device also comprises a cache memory comprising Y number of entries, the cache memory associated with the given segment of the memory bank, and wherein the Y number of entries is based on the M, the N and the prescribed word error rate, E, to prevent overflow of the cache memory.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: January 29, 2019
    Assignee: SPIN TRANSFER TECHNOLOGIES, INC.
    Inventors: Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele, Daniel Hillman
  • Patent number: 10185496
    Abstract: A reception-side apparatus determines whether or not data duplicating a part of received data from a transmission-side apparatus is stored in the first storage that stores first data which has been received, and notifies, when data duplicating a part of the received data is stored in the first storage, the transmission-side apparatus of prediction information on duplicate reception of the first data. A transmission-side apparatus compares, when the prediction information is received, second data to be transmitted and a part of the first data in a second storage that stores the first data which has been transmitted based on the prediction information, determines whether or not there is a first part of the first data matching the second data in the second storage, and transmits, when there is the first part of the first data in the second storage, outline information on the second data.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: January 22, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Shinichi Sazawa, Hiroaki Kameyama
  • Patent number: 10180901
    Abstract: Aspects of the present disclosure disclose systems and methods for managing space in storage devices. In various aspects, the disclosure is directed to providing more efficient method for managing free space in the storage system, and related apparatus and methods. In particular, the system provides for freeing blocks of memory that are no longer being used based on the information stored in a file system. More specifically, the system allows for reclaiming of large segments of free blocks at one time by providing information on aggregated blocks that were being freed to the storage devices.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: January 15, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventor: Eric Carl Taylor
  • Patent number: 10169233
    Abstract: A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address field and a data field. A TLB purge process performs operations for invalidating data in the primary cache memory which do not conform to the current state of the translation lookaside buffer. Whenever the TLB purge process and a cache update process perform a write operation to the primary cache memory concurrently, the write operation by the TLB purge process has no effect on the content of the primary cache memory and the cache update process overwrites a data field in a cache line of the primary cache memory but does not overwrite a virtual address field of said cache line. The translation lookaside buffer purge process is subsequently restored to an earlier state and restarted from the earlier state.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Simon H. Friedmann, Markus Kaltenbach, Dietmar Schmunkamp, Johannes C. Reichart
  • Patent number: 10169234
    Abstract: A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address field and a data field. A TLB purge process performs operations for invalidating data in the primary cache memory which do not conform to the current state of the translation lookaside buffer. Whenever the TLB purge process and a cache update process perform a write operation to the primary cache memory concurrently, the write operation by the TLB purge process has no effect on the content of the primary cache memory and the cache update process overwrites a data field in a cache line of the primary cache memory but does not overwrite a virtual address field of said cache line. The translation lookaside buffer purge process is subsequently restored to an earlier state and restarted from the earlier state.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Simon H. Friedmann, Markus Kaltenbach, Dietmar Schmunkamp, Johannes C. Reichart
  • Patent number: 10096065
    Abstract: Various examples are directed to systems and methods for distributed transactions with extended locks. A transaction node may receive from a coordinator node an instruction to execute an assigned operation on an object. The assigned operation may be part of a distributed transaction. The transaction node may obtain a lock associated with the object and execute the assigned operation. The transaction node may also set a time-to-expiration of a lock timer to an initial value and start the lock timer. When the transaction node determines that the lock timer has expired, it may release the lock.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: October 9, 2018
    Assignee: Red Hat, Inc.
    Inventor: Mark Little
  • Patent number: 9990142
    Abstract: A mass storage system for storing mass data generated by a mass data source. The system includes a data buffer coupled to the mass data source, and a file system and command generator. The data buffer caches the mass data. The file system and command generator generates file system data corresponding to the mass data stored in the data buffer. The file system and command generator also automatically configures a SATA host controller so that the SATA host controller will move the cached mass data and the generated file system data to a mass storage device.
    Type: Grant
    Filed: September 4, 2016
    Date of Patent: June 5, 2018
    Assignee: NXP USA, INC.
    Inventors: Shuwei Wu, Bin Feng, Bin Sai
  • Patent number: 9983821
    Abstract: A method of memory deduplication includes identifying hash tables each corresponding to a hash function, and each including physical buckets, each physical bucket including ways and being configured to store data, identifying virtual buckets each including some physical buckets, and each sharing a physical bucket with another virtual bucket, identifying each of the physical buckets having data stored thereon as being assigned to a single virtual bucket, hashing a data line according to a hash function to produce a hash value, determining whether a corresponding virtual bucket has available space for a block of data according to the hash value, sequentially moving data from the corresponding virtual bucket to an adjacent virtual bucket when the corresponding virtual bucket does not have available space until the corresponding virtual bucket has space for the block of data, and storing the block of data in the corresponding virtual bucket.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: May 29, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Frederic Sala, Chaohong Hu, Hongzhong Zheng, Dimin Niu, Mu-Tien Chang
  • Patent number: 9965607
    Abstract: Embodiments may take the form of devices and methods to help expedite matching biometric data in a validation process. One embodiment, for example, may take the form of a method for biometric validation including receiving a biometric input and retrieving metadata data of a most recently matched template. The method also includes evaluating the metadata and selecting one or more nodes from the most recently matched template for comparison. Additionally, the method includes comparing the selected one or more nodes with the received biometric input and determining if the selected one or more nodes match with the received biometric input. Also, the method includes validating the received biometric input if the selected one or more nodes match with the received biometric input.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: May 8, 2018
    Assignee: Apple Inc.
    Inventor: Craig A. Marciniak
  • Patent number: 9952981
    Abstract: A method includes reading memory pages from a non-volatile memory that holds at least first memory pages having a first bit significance and second memory pages having a second bit significance, different from the first bit significance. At least some of the read memory pages are cached in a cache memory. One or more of the cached memory pages are selected for eviction from the cache memory, in accordance with a selection criterion that gives eviction preference to the memory pages of the second bit significance over the memory pages of the first bit significance. The selected memory pages are evicted from the cache memory.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: April 24, 2018
    Assignee: APPLE INC.
    Inventors: Alex Radinski, Tsafrir Kamelo