Abstract: Physical storage devices are configured as a redundant array of independent disks (RAID). As such, storage space of the physical storage devices is allocated to the RAID, and each physical storage device is part of the RAID. Where a portion of the storage space of the physical storage devices is not allocated to the RAID, this portion of the storage space from a mixed drive capacity is configured so that it is usable and is not wasted.

Abstract: The subject technology discloses configurations for selecting a set of objects stored in volatile memory that have not been recently used by the application in which each object from among the set of object resides at a respective range of memory addresses in the volatile memory and each object was created by the application. Memory protection is set on the respective range of addresses in the volatile memory for each object from among the set of objects in which the memory protection flags the respective range of addresses for handling when the application subsequently performs a read or write operation to the respective range of addresses. The subject technology copies the set of objects from the volatile memory to a non-volatile memory. The respective range of memory addresses in the volatile memory are freed for each object from among the set of objects.

Abstract: A method, device and computer program for efficiently identifying items having a high frequency of occurrence among items included in a large-volume text data stream. Identification information for identifying an item and a count of items are stored in a higher level of memory and only identification information is stored in a lower level. Text data stream input is received, the increment of the count of an item is increased in response to storage in the higher level memory of identification information for an item included in a bucket divided from the received text data stream input, identification information for the item is transferred with the initial count to the higher level of memory in response to storage in the lower level and the identification information for the item is newly stored with the initial count in the higher level in response to not being stored on any level.

Abstract: Embodiments of the present invention provide a method and an apparatus for storing data, which relate to the field of data processing. In the present invention, a current device is divided into different load modes in the process of service processing, and manners of storing various data in a Cache are dynamically adjusted, so that nodes with different characteristics in the current device may control operations on the Cache, thus achieving lower power consumption and optimum performance of a large-capacity system under a heavy load.

Abstract: A method, computer program product, and computing system for storing a plurality of frontend data chunks within a cache system. The plurality of frontend data chunks correspond to a plurality of backend data chunks stored within a data array. A device weight is determined for each of the plurality of backend data chunks. The device weight is indicative of the type of storage device upon which each of the plurality of backend data chunks is stored within the data array. A deletion score is assigned to each of the plurality of frontend data chunks. Each deletion score is based, at least in part, upon the device weight determined for its corresponding backend data chunk.

Abstract: The present invention is directed to systems and methods for opportunistically defragmenting a data storage device during garbage collection. During garbage collection, valid data is identified and cached in a buffer assigned to the garbage collection process. When the buffer has been filled or reached a threshold, the valid data in the buffer is then coalesced and rewritten back to the data storage medium. In addition, a translation table is reduced by updating its entries to indicate the new locations of the coalesced valid data.

Abstract: A system and method for efficiently storing data both on-site and off-site in a cloud storage system. Data read and write requests are received by a cloud data storage system. The cloud storage system has at least three data storage layers. A first high-speed layer, a second efficient storage layer, and a third off-site storage layer. The first high-speed layer stores data in raw data blocks. The second efficient storage layer divides data blocks from the first layer into data slices and eliminates duplicate data slices. The third layer stores data slices at an off-site location.

Abstract: The present invention is directed to a method for providing storage acceleration in a data storage system. In the data storage system described herein, multiple independent controllers may be utilized, such that a first storage controller may be connected to a first storage tier (ex.—a fast tier) which includes a solid-state drive, while a second storage controller may be connected to a second storage tier (ex.—a slower tier) which includes a hard disk drive. The accelerator functionality may be split between the host of the system and the first storage controller of the system (ex.—some of the accelerator functionality may be offloaded to the first storage controller) for promoting improved storage acceleration performance within the system.

Abstract: Systems and techniques are described for thread cache allocation. A described technique includes monitoring input and output accesses for a plurality of threads executing on a computing device that includes a cache comprising a quantity of memory blocks, determining a respective reuse intensity for each of the threads, determining a respective read ratio for each of the threads, determining a respective quantity of memory blocks for each of the partitions by optimizing a combination of cache utilities, each cache utility being based on the respective reuse intensity, the respective read ratio, and a respective hit ratio for a particular partition, and resizing one or more of the partitions to be equal to the respective quantity of the memory blocks for the partition.

Abstract: In an embodiment, a processor includes a decode logic to receive and decode a first memory access instruction to store data in a cache memory with a replacement state indicator of a first level, and to send the decoded first memory access instruction to a control logic. In turn, the control logic is to store the data in a first way of a first set of the cache memory and to store the replacement state indicator of the first level in a metadata field of the first way responsive to the decoded first memory access instruction. Other embodiments are described and claimed.

Abstract: Apparatuses, systems, and methods are disclosed for managing cache pools. A storage request module monitors storage requests received by a cache. The storage requests include read requests and write requests. A read pool module adjusts a size of a read pool of the cache to increase a read hit rate of the storage requests. A dirty write pool module adjusts a size of a dirty write pool of the cache to increase a dirty write hit rate of the storage requests.

Abstract: A cache control apparatus comprises a primary cache part, a secondary cache part for caching data destaged from the primary cache part, and a controller connected to the primary cache part and to the secondary cache part. The secondary cache part has a first storage part and a second storage part having a lifetime longer than that of the first storage part. The controller determines whether the data destaged from the primary cache part is to be stored in the first storage part or the second storage part in the secondary cache part, based on a use state indicating whether or not the data has been updated, and stores the data in the first storage part or the second storage part determined.

Abstract: The present invention is a system and method for utilizing shadow/ghost list to prevent excessive wear on FLASH based cache devices. The method determines when data is highly likely to be accessed again, and avoids writes to a FLASH based caching device when data is unlikely to be accessed again through the use of “shadow” or “ghost” lists that are also used to perform adaptive caching.

Abstract: Some embodiments include a partitioning mechanism that partitions a cache memory into sub-partitions for sub-entities. In the described embodiments, the cache memory is initially partitioned into two or more partitions for one or more corresponding entities. During a partitioning operation, the partitioning mechanism is configured to partition one or more of the partitions in the cache memory into two or more sub-partitions for one or more sub-entities of a corresponding entity. A cache controller then uses a corresponding sub-partition for memory accesses by the one or more sub-entities.

Abstract: Described are techniques for performing recovery processing in a data storage system. A providing a flash-based memory is provided with includes cached write data that has not been destaged to a data storage device. It is determined whether said flash-based memory has a threshold amount of storage available thereon. If the flash-based memory does not have the threshold amount of storage available thereon, portions of the cache write data are destaged until said flash-based memory has a threshold amount of storage available thereon. Received data requests are processed in accordance with a first policy different from a second policy used in connection with processing received data requests if said flash-based memory has a threshold amount of storage available thereon.

Abstract: A method and apparatus for monitor and mwait in a distributed cache architecture is disclosed. One embodiment includes an execution thread sending a MONITOR request for an address to a portion of a distributed cache that stores the data corresponding to that address. At the distributed cache portion the MONITOR request and an associated speculative state is recorded locally for the execution thread. The execution thread then issues an MWAIT instruction for the address. At the distributed cache portion the MWAIT and an associated wait-to-trigger state are recorded for the execution thread. When a write request matching the address is received at the distributed cache portion, a monitor-wake event is then sent to the execution thread and the associated monitor state at the distributed cache portion for that execution thread can be reset to idle.

Abstract: A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.

Abstract: A host configured to interact with a storage device includes a write-back (WB) cache configured to write data to the storage device, a cache managing module configured to manage the WB cache, and a file system module configured to determine whether live blocks in victim segments among a plurality of segments stored in the storage device are stored in the WB cache, to read the live blocks from the storage device as a consequence of determining that the live blocks are not stored in the WB cache, to load the read live blocks to the WB cache, and to request the cache managing module to set dirty flags for the stored live blocks.

Abstract: Technologies are generally described for a cache coherence directory in multi-processor architectures. In an example, a directory in a die may receive a request for a particular block. The directory may determine a block aging threshold relating to a likelihood that data blocks, including the particular data block, are stored in one or more caches in the die. The directory may further analyze a memory to identify a particular cache indicated as storing the particular data block and identify a number of cache misses for the particular cache. The directory may identify a time when an event occurred for the particular data block and determine whether to send the request for the particular data block to the particular cache based on the aging threshold, the time of the event, and the number of cache misses.

Abstract: An I/O controller, coupled to a processing unit and to a memory, includes an I/O link interface configured to receive data packets having virtual addresses; an address translation unit having an address translator to translate received virtual addresses into real addresses by translation control entries and a cache allocated to the address translator to cache a number of the translation control entries; an I/O packet processing unit for checking the data packets received at the I/O link interface and for forwarding the checked data packets to the address translation unit; and a prefetcher to forward address translation prefetch information from a data packet received to the address translation unit; the address translator configured to fetch the translation control entry for the data packet by the address translation prefetch information from the allocated cache or, if the translation control entry is not available in the allocated cache, from the memory.

Abstract: Exemplary methods, apparatuses, and systems determine that a cache is to be migrated from a first storage device to a second storage device. The cache includes cache entries organized in a first list of cache entries and a second list of cache entries. Only a portion of all cache entries from the first and second lists is selected for migration to the second storage device. The selected cache entries and metadata for cache entries from the first or second list that were not selected are migrated from the first storage device to the second storage device.

Abstract: Exemplary methods, apparatuses, and systems determine that a cache is to be migrated from a first storage device to a second storage device. Each cache entry within the cache includes a first indicator to indicate whether or not the cache entry has long-term utility. Only a portion of all cache entries are selected to be migrated and the portion is selected from cache entries with the first indicator set to indicate long-term utility. The selected cache entries and metadata for cache entries that were not selected are migrated from the first storage device to the second storage device.

Abstract: A controller receives a request to perform a release space operation. A determination is made that a new discard scan has to be performed on a cache, in response to the received request to perform the release space operation. A determination is made as to how many task control blocks are to be allocated to the perform the new discard scan, based on how many task control blocks have already been allocated for performing one or more discard scans that are already in progress.

Abstract: A set associative cache is managed by a memory controller which places writeback instructions for modified (dirty) cache lines into a virtual write queue, determines when the number of the sets containing a modified cache line is greater than a high water mark, and elevates a priority of the writeback instructions over read operations. The controller can return the priority to normal when the number of modified sets is less than a low water mark. In an embodiment wherein the system memory device includes rank groups, the congruence classes can be mapped based on the rank groups. The number of writes pending in a rank group exceeding a different threshold can additionally be a requirement to trigger elevation of writeback priority. A dirty vector can be used to provide an indication that corresponding sets contain a modified cache line, particularly in least-recently used segments of the corresponding sets.

Abstract: In general, the disclosure is directed to techniques for choosing which pages to evict from the buffer pool to make room for caching additional pages in the context of a database table scan. A buffer pool is maintained in memory. A fraction of pages of a table to persist in the buffer pool are determined. A random number is generated as a decimal value of 0 to 1 for each page of the table cached in the buffer pool. If the random number generated for a page is less than the fraction, the page is persisted in the buffer pool. If the random number generated for a page is greater than the fraction, the page is included as a candidate for eviction from the buffer pool.

Abstract: An amount of sequential fast write (SFW) Tracks are metered by providing an adjustable threshold for performing a destage scan that moves the SFW tracks from a SFW least recently used (LRU) list to a destaging wait list (DWL). Priorities are set for the destaging of the SFW tracks from the DWL.

Abstract: Cluster data is generated based on a history of storage operations. The cluster data may include an address range and an access history. The access history may comprise a bit pattern that represents a history of storage operations associated with a cluster. A prefix or counter may identify the number of storage operations identified in the bit pattern. The bit pattern and/or address range may be updated to reflect new storage operations associated with the cluster. The bit pattern then may determine when to cache data in a cache memory. The bit pattern tracks a large number of storage operations in a relatively small amount of memory enabling quick effective caching decisions.

Abstract: A method of identifying a cache line of a cache memory (180) for replacement, is disclosed. Each cache line in the cache memory has a stored sequence number and a stored transaction data stream identifying label. A request (e.g., 400) associated with a label identifying a transaction data stream is received. The label corresponds to the stored transaction data stream identifying label of the cache line. The stored sequence number of the cache line is compared with a response sequence number. The response sequence number is associated with the stored transaction data stream identifying label of the cache line. The cache line is identified for replacement based on the comparison.

Abstract: A method is used in enhancing memory buffering by using secondary storage. A buffer cache pool is supplemented with a secondary storage. A portion of a volatile memory of a data storage system is reserved as the buffer cache pool. The buffer cache pool includes a set of buffer cache objects for storing file system data and metadata. The secondary storage includes a set of data blocks. A first buffer cache object of the set of buffer cache objects is aged out by copying contents of the buffer cache object to a data block of the secondary storage. Contents of the first buffer cache object are retrieved from the secondary storage by copying contents of the data block of the secondary storage to a second buffer cache object of the set of buffer cache objects of the buffer cache pool.

Abstract: An information processing device includes a memory and a processor coupled to the memory, wherein the processor executes a process comprising selecting data included in a same file as deletion target data from the memory when deleting the data cached in the memory at the caching from the memory and deleting the deletion target data and the data selected at the selecting, from the memory.

Abstract: A method and computer program product for managing a file cache with a filesystem cache manager is disclosed. The method may include installing the filesystem cache manager for the file cache by a mount command. The filesystem cache manager may include a specified time interval and a first cache elimination instruction. The method may further include starting a first timer upon the installation of the filesystem cache manager. The method may further include running the first cache elimination instruction when the first timer reaches the specified time interval.

Abstract: The present disclosure discloses a method, a system and a server of removing a distributed caching object. In one embodiment, the method receives a removal request, where the removal request includes an identifier of an object. The method may further apply consistent Hashing to the identifier of the object to obtain a Hash result value of the identifier, locates a corresponding cache server based on the Hash result value and renders the corresponding cache server to be a present cache server. In some embodiments, the method determines whether the present cache server is in an active status and has an active period greater than an expiration period associated with the object. Additionally, in response to determining that the present cache server is in an active status and has an active period greater than the expiration period associated with the object, the method removes the object from the present cache server.

Abstract: A method and computer program product for managing a file cache with a filesystem cache manager is disclosed. The method may include installing the filesystem cache manager for the file cache by a mount command. The filesystem cache manager may include a specified time interval and a first cache elimination instruction. The method may further include starting a first timer upon the installation of the filesystem cache manager. The method may further include running the first cache elimination instruction when the first timer reaches the specified time interval.

Abstract: Embodiments relate to a transactional read footprint after a cache line eviction. An aspect includes executing one or more read instructions in an active transaction. A cross invalidate (XI) request for a target cache line is received, and it is determined if the target cache line is part of a congruence class in a local cache. It is further determined whether an extension flag associated with the congruence class is set. The extension flag is used to indicate that cache lines of the congruence class associated with the active transaction have been replaced based only on being least recently used and that the target cache line is not in the cache. Execution of the active transaction continues based on determining that the extension flag is not set. Execution of the active transaction is aborted based on determining that the extension flag is set.

Abstract: According to an embodiment, in a cache system, the sequence storage stores sequence data in association with each piece of data to be stored in the volatile cache memory in accordance with the number of pieces of data stored in the nonvolatile cache memory that have been unused for a longer period of time than the data stored in the volatile cache memory or the number of pieces of data stored in the nonvolatile cache memory that have been unused for a shorter period of time than the data stored in the volatile cache memory. The controller causes the first piece of data to be stored in the nonvolatile cache memory in a case where it can be determined that the first piece of data has been unused for a shorter period of time than any piece of the data stored in the nonvolatile cache memory.

Abstract: Embodiments herein provide for using one or more cache memory to facilitate non-temporal transaction. A request to store data into a cache associated with a processor is received. In response to receiving the request, a determination is made as to whether the data to be stored is non-temporal data. A predetermined location of the cache is selected; the location to which storing of the non-temporal data is restricted to a predetermined location, in response to determining the data to be stored is non-temporal data. The non-temporal data is data that is not accessed within a predetermined period of time. The non-temporal data is stored into the predetermined location.

Abstract: A cache manager application provides a data caching policy in a multiple tenant enterprise resource planning (ERP) system. The cache manager application manages multiple tenant caches in a single process. The application applies the caching policy. The caching policy optimizes system performance compared to local cache optimization. As a result, tenants with high cache consumption receive a larger portion of caching resources.

Abstract: Embodiments of the present invention provide a method and apparatus for removing cached data. The method comprises determining activeness of a plurality of divided lists; ranking the plurality of divided lists according to the determined activeness of the plurality of divided lists. The method comprises removing a predetermined amount of cached data from the plurality of divided lists according to the ranking result when the used capacity in the cache area reaches a predetermined threshold. Through embodiments of the present invention, the activeness of each divided list may be used to wholly measure the heat of access to the cached data included by each divided list, and upon removal, the cached data with lower heat of access in the whole system can be removed and the cached data with higher heat of access in the whole system can be retained so as to improve the read/write rate of the system.

Abstract: A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided.

Abstract: A cache page management method can include paging out a memory page to an input/output controller, paging the memory page from the input/output controller into a real memory, modifying the memory page in the real memory to an updated memory page and purging the memory page paged to the input/output controller.

Abstract: Technology is disclosed for generating predictive cache statistics for various cache sizes. In some embodiments, a storage controller includes a cache tracking mechanism for concurrently generating the predictive cache statistics for various cache sizes for a cache system. The cache tracking mechanism can track simulated cache blocks of a cache system using segmented cache metadata while performing an exemplary workload including various read and write requests (client-initiated I/O operations) received from client systems (or clients). The segmented cache metadata corresponds to one or more of the various cache sizes for the cache system.

Abstract: A method of shielding a memory device (110) from high write rates comprising receiving instructions to write data at a memory container (105), the memory controller (105) composing a cache (120) comprising a number of cache lines defining stored data, with the memory controller (105), updating a cache line in response to a write hit in the cache (120), and with the memory controller (105), executing the instruction to write data in response to a cache miss to a cache line within the cache (120) in which the memory controller (105) prioritizes for writing to the cache (120) over writing to the memory device (110).

Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

Abstract: Provided are techniques for handling a store buffer in conjunction with a processor, the store buffer comprising a free list; a merge window; and an evict list; and logic, for, upon receipt of a T_STORE operation, comparing a first address associated with the T_STORE operation with a plurality of addresses associated with previous T_STORE operations, wherein the previous T_STORE operations are part of the same transaction as the T_STORE operation and the entries corresponding to the previous T_STORE operations are stored in the merge window; in response to a match between the first address and a second address, associated with a second T_STORE operation, of the plurality of addresses, merging a first entry corresponding to the first T_STORE operation with a second entry corresponding to the second T_STORE operation; and consolidating results associated with the first T_STORE operation with results associated with the second T_STORE operation.

Abstract: A level of cache memory receives modified data from a higher level of cache memory. A set of cache lines with an index associated with the modified data is identified. The modified data is stored in the set in a cache line with an eviction priority that is at least as high as an eviction priority, before the modified data is stored, of an unmodified cache line with a highest eviction priority among unmodified cache lines in the set.

Abstract: Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.

Abstract: Embodiments of the disclosure provide techniques for creating a compressed mapping structure in a system of resources. For example, a distributed resources system may use delta encoding to store, in memory, numerous entries of dense data structures in the system. In a compressed block of such entries, the distributed resources system encodes the key of each entry as the delta from the key of the previous entry. The content of each entry is encoded similarly. The distributed resources system suppresses the leading zero bits of each resulting field.

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract: A cache memory control procedure has: cache area allocating including allocating, in response to an acquisition request, and according to an effective cache usage degree that is based on a memory access frequency and a difference between a cache hit rate in a case where the dedicated cache area is allocated and a cache hit rate in a case where a shared cache area in the cache memory is allocated, the dedicated cache area for a higher effective cache usage degree and the shared cache area for a lower effective cache usage degree; and releasing the dedicated cache area which is allocated, in response to a release request which is issued during execution of a process by the processor and requests the release of the allocated dedicated cache area.

Abstract: A processing unit includes a processor core and a cache memory. Entries in the cache memory are grouped in multiple congruence classes. The cache memory includes tracking logic that tracks a transaction footprint including cache line(s) accessed by transactional memory access request(s) of a memory transaction. The cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class, forms a working set of ways in the congruence class containing cache line(s) within the transaction footprint and updates a replacement order of the cache lines in the congruence class. Based on membership of the at least one cache line in the working set, the update promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced.