Abstract: An adaptive data replication and caching system configured for deployment at the network edge. This system can include a data caching system configured to cache application data in a data store and to satisfy queries for application data from the cache. The system also can include a data replication system configured to replicate application data in the data store and to satisfy queries for application data against the replicated application data. Finally, the adaptive data replication and caching system can include a configurator for configuring portions of the data store for exclusive use by the data caching system and the data replication system.

Abstract: Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.

Abstract: Systems and methods for managing data input/output operations are described. In one aspect, a device driver identifies a data read operation generated by a virtual machine in a virtual environment. The device driver is located in the virtual machine and the data read operation identifies a physical cache address associated with the data requested in the data read operation. A determination is made regarding whether data associated with the data read operation is available in a cache associated with the virtual machine.

Abstract: In one embodiment, a method includes receiving data at a cache node in a network of cache nodes, the cache node located on a data path between a source of the data and a network device requesting the data, and determining if the received data is to be cached at the cache node, wherein determining comprises calculating a cost incurred to retrieve the data. An apparatus and logic are also disclosed.

Abstract: A mechanism for selectively disabling and enabling read caching based on past performance of the cache and current read/write requests. The system improves overall performance by using an autonomic algorithm to disable read caching for regions of backend disk storage (i.e., the backstore) that have had historically low cache hit ratios. The result is that more cache becomes available for workloads with larger hit ratios, and less time and machine cycles are spent searching the cache for data that is unlikely to be there.

Abstract: A system and method for efficiently determining whether a requested memory location is in a large row-based memory of a computing system. A computing system includes a processing unit that generates memory requests on a first chip and a cache (LLC) on a second chip connected to the first chip. The processing unit includes an access filter that determines whether to access the cache. The cache is fabricated on top of the processing unit. The processing unit determines whether to access the access filter for a given memory request. The processing unit accesses the access filter to determine whether given data associated with a given memory request is stored within the cache. In response to determining the access filter indicates the given data is not stored within the cache, the processing unit generates a memory request to send to off-package memory.

Abstract: Approaches for caching addressable items in a multiprocessor system. Instructions are cached in a plurality of first-level instruction caches respectively coupled to a plurality of processors of the multiprocessor system. First-type data items are cached in a plurality of first-level data caches respectively coupled to the plurality of processors. Second-type data items are cached in a second-level cache and are not cached in any of the plurality of first-level data caches.

Abstract: A data storage system comprises a controller, a first lower performance storage medium and a second higher performance storage medium. The controller is connected to the storage mediums and is arranged to control I/O access to the storage mediums. The controller is further arranged to store an image on the first storage medium, initiate a copy function from the first storage medium to the second storage medium, direct all I/O access for the image to the second storage medium, periodically age data from the second storage medium to the first storage medium, create a new empty bitmap for each period, and in response to an I/O access for data in the image, update the latest bitmap to indicate that the data has been accessed and update the previous bitmaps to indicate that the data has not been accessed.

Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.

Abstract: A data storage system comprises a controller, a first lower performance storage medium and a second higher performance storage medium. The controller is connected to the storage mediums and is arranged to control I/O access to the storage mediums. The controller is further arranged to store an image on the first storage medium, initiate a copy function from the first storage medium to the second storage medium, direct all I/O access for the image to the second storage medium, periodically age data from the second storage medium to the first storage medium, create a new empty bitmap for each period, and in response to an I/O access for data in the image, update the latest bitmap to indicate that the data has been accessed and update the previous bitmaps to indicate that the data has not been accessed.

Abstract: In a multiprocessor system with at least two levels of cache, a speculative thread may run on a core processor in parallel with other threads. When the thread seeks to do a write to main memory, this access is to be written through the first level cache to the second level cache. After the write though, the corresponding line is deleted from the first level cache and/or prefetch unit, so that any further accesses to the same location in main memory have to be retrieved from the second level cache. The second level cache keeps track of multiple versions of data, where more than one speculative thread is running in parallel, while the first level cache does not have any of the versions during speculation. A switch allows choosing between modes of operation of a speculation blind first level cache.

Abstract: An apparatus having a cache and a circuit is disclosed. The cache includes a plurality of cache lines. The cache is configured to (i) store a plurality of data items in the cache lines and (ii) generate a map that indicates a dirty state or a clean state of each of the cache lines. The cache also has a write-back policy to a memory. The circuit is configured to (i) check a location in the map corresponding to a read address of a read request and (ii) obtain read data directly from the memory by bypassing the cache in response to the location having the clean state.

Abstract: Techniques for escalating a real time agent's request that has an address conflict with a best effort agent's request. A best effort request can be allocated in a memory controller cache but can progress slowly in the memory system due to its low priority. Therefore, when a real time request has an address conflict with an older best effort request, the best effort request can be escalated if it is still pending when the real time request is received at the memory controller cache. Escalating the best effort request can include setting the push attribute of the best effort request or sending another request with a push attribute to bypass or push the best effort request.

Abstract: A system and method is provided wherein, in one aspect, a currently-requested item of information is stored in a cache based on whether it has been previously requested and, if so, the time of the previous request. If the item has not been previously requested, it may not be stored in the cache. If the subject item has been previously requested, it may or may not be cached based on a comparison of durations, namely (1) the duration of time between the current request and the previous request for the subject item and (2) for each other item in the cache, the duration of time between the current request and the previous request for the other item. If the duration associated with the subject item is less than the duration of another item in the cache, the subject item may be stored in the cache.

Abstract: Provided are a computer program product, system, and method for caching data in a storage system having multiple caches. A sequential access storage device includes a sequential access storage medium and a non-volatile storage device integrated in the sequential access storage device, received modified tracks are cached in the non-volatile storage device, wherein the non-volatile storage device is a faster access device than the sequential access storage medium. A spatial index indicates the modified tracks in the non-volatile storage device in an ordering based on their physical location in the sequential access storage medium. The modified tracks are destaged from the non-volatile storage device by comparing a current position of a write head to physical locations of the modified tracks on the sequential access storage medium indicated in the spatial index to select a modified track to destage from the non-volatile storage device to the storage device.

Abstract: Provided a computer program product, system, and method for cache management of tracks in a first cache and a second cache for a storage. The first cache maintains modified and unmodified tracks in the storage subject to Input/Output (I/O) requests. Modified and unmodified tracks are demoted from the first cache. The modified and the unmodified tracks demoted from the first cache are promoted to the second cache. The unmodified tracks demoted from the second cache are discarded. The modified tracks in the second cache that are at proximate physical locations on the storage device are grouped and the grouped modified tracks are destaged from the second cache to the storage device.

Abstract: To increase the efficiency of a running application, it is determined whether using a cache or directly a storage is more efficient block size-specifically; and the determined memory type is used for a data stream having a corresponding block size.

Abstract: A bit or other vector may be used to identify whether an address range entered into an intermediate buffer corresponds to most recently updated data associated with the address range. A bit or other vector may also be used to identify whether an address range entered into an intermediate buffer overlaps with an address range of data that is to be loaded. A processing device may then determine whether to obtain data that is to be loaded entirely from a cache, entirely from an intermediate buffer which temporarily buffers data destined for a cache until the cache is ready to accept the data, or from both the cache and the intermediate buffer depending on the particular vector settings. Systems, devices, methods, and computer readable media are provided.

Abstract: A load store pipeline 18 includes an issue queue 20 and load store circuitry 24. The load store circuitry 24 includes the plurality of access slot circuits 26 to 40. Dependency tracking circuitry 42, 44, 46, 48 serves to track a freeable number of access slot circuits 26 to 42 corresponding to the sum of access slot circuits that are empty and those processing data access instructions which have not bypassed any preceding data access instructions within the program execution order.

Abstract: Some embodiments include a computing device with a control circuit that handles memory requests. The control circuit checks one or more conditions to determine when a memory request should be bypassed to a main memory instead of sending the memory request to a cache memory. When the memory request should be bypassed to a main memory, the control circuit sends the memory request to the main memory. Otherwise, the control circuit sends the memory request to the cache memory.

Abstract: A method for supporting a plurality of requests for access to a data cache memory (“cache”) is disclosed. The method comprises accessing a first set of requests to access the cache, wherein the cache comprises a plurality of blocks. Further, responsive to the first set of requests to access the cache, the method comprises accessing a tag memory that maintains a plurality of copies of tags for each entry in the cache and identifying tags that correspond to individual requests of the first set. The method also comprises performing arbitration in a same clock cycle as the accessing and identifying of tags, wherein the arbitration comprises: (a) identifying a second set of requests to access the cache from the first set, wherein the second set accesses a same block within the cache; and (b) selecting each request from the second set to receive data from the same block.

Abstract: Provided a computer program product, system, and method for cache management of tracks in a first cache and a second cache for a storage. The first cache maintains modified and unmodified tracks in the storage subject to Input/Output (I/O) requests. Modified and unmodified tracks are demoted from the first cache. The modified and the unmodified tracks demoted from the first cache are promoted to the second cache. The unmodified tracks demoted from the second cache are discarded. The modified tracks in the second cache that are at proximate physical locations on the storage device are grouped and the grouped modified tracks are destaged from the second cache to the storage device.

Abstract: According to one embodiment, a method for exchanging data in a system that includes a main processor in communication with an active memory device is provided. The method includes a processing element in the active memory device receiving an instruction from the main processor and receiving a store request from a thread running on the main processor, the store request specifying a memory address associated with the processing element. The method also includes storing a value provided in the store request in a queue in the processing element and the processing element performing the instruction using the value from the queue.

Abstract: According to one embodiment, a method for exchanging data in a system that includes a main processor in communication with an active memory device is provided. The method includes a processing element in the active memory device receiving an instruction from the main processor and receiving a store request from a thread running on the main processor, the store request specifying a memory address associated with the processing element. The method also includes storing a value provided in the store request in a queue in the processing element and the processing element performing the instruction using the value from the queue.

Abstract: Methods and apparatus relating to buffering in media and pipelined processing components are described. In one embodiment, a buffer may include an arbiter to receive data structure information from a producer, a memory to store the information, and an address generator to indicate a location in the memory to store the data structure information. Other embodiments are also disclosed.

Abstract: A cache is provided for operatively coupling a processor with a main memory. The cache includes a cache memory and a cache controller operatively coupled with the cache memory. The cache controller is configured to receive memory requests to be satisfied by the cache memory or the main memory. In addition, the cache controller is configured to process cache activity information to cause at least one of the memory requests to bypass the cache memory.

Abstract: A system and method is provided wherein, in one aspect, a currently-requested item of information is stored in a cache based on whether it has been previously requested and, if so, the time of the previous request. If the item has not been previously requested, it may not be stored in the cache. If the subject item has been previously requested, it may or may not be cached based on a comparison of durations, namely (1) the duration of time between the current request and the previous request for the subject item and (2) for each other item in the cache, the duration of time between the current request and the previous request for the other item. If the duration associated with the subject item is less than the duration of another item in the cache, the subject item may be stored in the cache.

Abstract: A storage system in an embodiment of this invention comprises a non-volatile storage area for storing write data from a host, a cache area capable of temporarily storing the write data before storing the write data in the non-volatile storage area, and a controller that determines whether to store the write data in the cache area or to store the write data in the non-volatile storage area without storing the write data in the cache area, and stores the write data in the determined area.

Abstract: In an embodiment, a system includes a memory controller, processors and corresponding caches. The system may include sources of uncertainty that prevent the precise scheduling of data forwarding for a load operation that misses in the processor caches. The memory controller may provide an early response that indicates that data should be provided in a subsequent clock cycle. An interface unit between the memory controller and the caches/processors may predict a delay from a currently-received early response to the corresponding data, and may speculatively prepare to forward the data assuming that it will be available as predicted. The interface unit may monitor the delays between the early response and the forwarding of the data, or at least the portion of the delay that may vary. Based on the measured delays, the interface unit may modify the subsequently predicted delays.

Abstract: A method to monitor the behavior of a working set cache of a full data set at run time and determine whether it provides a performance benefit is disclosed. An effectiveness metric of the working set cache is tracked over a period of time by efficiently computing the amount of physical memory consumption the cache saves and comparing this to a straightforward measure of its overhead. If the effectiveness metric is determined to be on an ineffective side of a selected threshold amount, the working set cache is disabled. The working set cache can be re-enabled in response to a predetermined event.

Abstract: A host device is provided comprising an interface configured to communicate with a storage device having a public memory area and a private memory area, wherein the public memory area stores a virtual file that is associated with content stored in the private memory area. The host device also comprises a cache, a host application, and a server. The server is configured to receive a request for the virtual file from the host application, send a request to the storage device for the virtual file, receive the content associated with the virtual file from the private memory area of the storage device, wherein the content is received by bypassing the cache, generate a response to the request from the host application, the response including the content, and send the response to the host application.

Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.

Abstract: Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core including a core bus agent, a bus interface unit (BIU), and a bridge module operatively coupling the processing core to the BIU, the bridge module configured to selectively route information from the core bus agent to a cache or to the BIU by bypassing the cache. Other embodiments are also described and claimed.

Abstract: Techniques are disclosed relating to prefetching data from memory. In one embodiment, an integrated circuit may include a processor containing an execution core and a data cache. The execution core may be configured to receive an instance of a prefetch instruction that specifies a memory address from which to retrieve data. In response to the instance of the instruction, the execution core retrieves data from the memory address and stores it in the data in the data cache, regardless of whether the data corresponding to that particular memory address is already stored in the data cache. In this manner, the data cache may be used as a prefetch buffer for data in memory buffers where coherence has not been maintained.

Abstract: A cache is provided for operatively coupling a processor with a main memory. The cache includes a cache memory and a cache controller operatively coupled with the cache memory. The cache controller is configured to receive memory requests to be satisfied by the cache memory or the main memory. In addition, the cache controller is configured to process cache activity information to cause at least one of the memory requests to bypass the cache memory.

Abstract: Provided are a computer program product, system, and method for caching data in a storage system having multiple caches. A sequential access storage device includes a sequential access storage medium and a non-volatile storage device integrated in the sequential access storage device, received modified tracks are cached in the non-volatile storage device, wherein the non-volatile storage device is a faster access device than the sequential access storage medium. A spatial index indicates the modified tracks in the non-volatile storage device in an ordering based on their physical location in the sequential access storage medium. The modified tracks are destaged from the non-volatile storage device by comparing a current position of a write head to physical locations of the modified tracks on the sequential access storage medium indicated in the spatial index to select a modified track to destage from the non-volatile storage device to the storage device.

Abstract: A method for data transmission on a device without intermediate buffering is provided. An application request is received to transmit data from the device to a second device over a network. The data from application memory is formatted for transmitting to the second device. The data are transmitted from the device to the second device without intermediate buffering. A send state is retrieved. The send state is compared to expected send state. If the send state meets the expected send state, a completion of the data transmit request is generated.

Abstract: The present disclosure includes systems and techniques relating to customization of a bus adapter card. In some implementations, an apparatus includes a processor and a program memory, a bus adapter card coupled with the computing apparatus and configured to connect with a storage device, the bus adapter card comprising a cache memory and a controller to cache in the cache memory data associated with the storage device, where the program memory includes a driver to communicate with the bus adapter card responsive to requests corresponding to the storage device, and the driver is configured to modify its communications with the bus adapter card responsive to information provided separate from the requests.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk comprising a plurality of data tracks, where each data track comprises a plurality of data sectors. The hybrid drive further comprises a non-volatile semiconductor memory (NVSM) comprising a plurality of memory segments. When a write command is received from a host including write data, the write data is written to one of a disk cache and a NVSM cache, wherein the write data is eventually flushed to a non-cache area of the disk.

Abstract: A method and apparatus used within memory and data processing that reduces the number of references allowed in processor cache by using active rows to reject references that are less frequently used from the cache. Comparators within a memory controller are used to generate a signal indicative of a row hit or miss, which signal is then applied to one or more demultiplexers to enable or disable transfer of a memory reference to processor cache locations. The cache may be level one (L1) or level two (L2) caches including data and or instructions or some combination of L1, L2, data, and instructions.

Abstract: A network caching system has a multi-protocol caching filer coupled to an origin server to provide storage virtualization of data served by the filer in response to data access requests issued by multi-protocol clients over a computer network. The multi-protocol caching filer includes a file system configured to manage a sparse volume that “virtualizes” a storage space of the data to thereby provide a cache function that enables access to data by the multi-protocol clients. To that end, the caching filer further includes a multi-protocol engine configured to translate the multi-protocol client data access requests into generic file system primitive operations executable by both the caching filer and the origin server.

Abstract: A processor having a cache memory provided therein controls use of the cache memory based on operation mode information which changeably designates use/no-use of a cache memory and on designation of cache memory use in an access instruction word in a program at the time of an access to a main storage memory from the program in operation.

Abstract: A system, method, and computer-readable medium that facilitate efficient use of cache memory in a massively parallel processing system are provided. A residency time of a data block to be stored in cache memory or a disk drive is estimated. A metric is calculated for the data block as a function of the residency time. The metric may further be calculated as a function of the data block size. One or more data blocks stored in cache memory are evaluated by comparing a respective metric of the one or more data blocks with the metric of the data block to be stored. A determination is then made to either store the data block on the disk drive or flush the one or more data blocks from the cache memory and store the data block in the cache memory. In this manner, the cache memory may be more efficiently utilized by storing smaller data blocks with lesser residency times by flushing larger data blocks with significant residency times from the cache memory.

Abstract: A method for caching data in a storage medium implementing tiered data structures may include storing a first portion of critical data at the instruction of a storage control module. The first portion of critical data may be separated into data having different priority levels based upon at least one data utilization characteristic associated with a file system implemented by the storage control module. The method may also include storing a second portion of data at the instruction of the storage control module. The second storage medium may have at least one performance, reliability, or security characteristic different from the first storage medium.

Abstract: Implementations described and claimed herein provide a method and system for comparing a storage location related to a new write command on a storage device with storage locations of a predetermined number of write commands stored in a first table to determine frequency of write commands to the storage location. If the frequency is determined to be higher than a first threshold, the data related to the write command is stored in a write cache.

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract: A device includes a data collector module, a policy module, and an optimizer module. The data collector module is to collect values for a plurality of device parameters. The policy module is to receive the values for the plurality of device parameters and update a policy table. The optimizer module is to receive the policy table from the policy module, determine, based on the policy table, whether to proceed with buffered input/output or un-buffered input/output for a read call, and instruct a read module of a backup application to proceed with either buffered input/output or un-buffered input/output for the read call.

Abstract: A system and method is provided wherein, in one aspect, a currently-requested item of information is stored in a cache based on whether it has been previously requested and, if so, the time of the previous request. If the item has not been previously requested, it may not be stored in the cache. If the subject item has been previously requested, it may or may not be cached based on a comparison of durations, namely (1) the duration of time between the current request and the previous request for the subject item and (2) for each other item in the cache, the duration of time between the current request and the previous request for the other item. If the duration associated with the subject item is less than the duration of another item in the cache, the subject item may be stored in the cache.

Abstract: In a first aspect, a first cryptography method is provided. The first method includes the steps of (1) in response to receiving a request to perform a first operation on data in a first memory cacheline, accessing data associated with the first memory cacheline; (2) performing cryptography on data of the first memory cacheline when necessary; and (3) speculatively accessing data associated with a second memory cacheline based on the first memory cacheline before receiving a request to perform an operation on data in the second memory cacheline. Numerous other aspects are provided.

Abstract: A system and method is provided wherein, in one aspect, a currently-requested item of information is stored in a cache based on whether it has been previously requested and, if so, the time of the previous request. If the item has not been previously requested, it may not be stored in the cache. If the subject item has been previously requested, it may or may not be cached based on a comparison of durations, namely (1) the duration of time between the current request and the previous request for the subject item and (2) for each other item in the cache, the duration of time between the current request and the previous request for the other item. If the duration associated with the subject item is less than the duration of another item in the cache, the subject item may be stored in the cache.