Abstract: A method and system for file-system based caching can be used to improve efficiency and security at network sites. In one set of embodiments, the delivery of content and storing content component(s) formed during generation of the content may be performed by different software components. Content that changes at a relatively high frequency or is likely to be regenerated between requests may not have some or all of its corresponding files cached. Additionally, extra white space may be removed before storing to reduce the file size. File mapping may be performed to ensure that a directory within the cache will have an optimal number of files. Security at the network site may be increased by using an internally generated filename that is not used or seen by the client computer. Many variations may be used is achieving any one or more of the advantages described herein.

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract: A host device is provided comprising an interface configured to communicate with a storage device having a public memory area and a private memory area, wherein the public memory area stores a virtual file that is associated with content stored in the private memory area. The host device also comprises a cache, a host application, and a server. The server is configured to receive a request for the virtual file from the host application, send a request to the storage device for the virtual file, receive the content associated with the virtual file from the private memory area of the storage device, wherein the content is received by bypassing the cache, generate a response to the request from the host application, the response including the content, and send the response to the host application. In one embodiment, the server is a hypertext transfer protocol (HTTP) server.

Abstract: A host device is provided comprising an interface configured to communicate with a storage device having a public memory area and a private memory area, wherein the public memory area stores a virtual file that is associated with content stored in the private memory area. The host device also comprises a cache, a host application, and a server. The server is configured to receive a request for the virtual file from the host application, send a request to the storage device for the virtual file, receive the content associated with the virtual file from the private memory area of the storage device, wherein the content is received by bypassing the cache, generate a response to the request from the host application, the response including the content, and send the response to the host application. In one embodiment, the server is a hypertext transfer protocol (HTTP) server.

Abstract: According to one embodiment, an information reproducing apparatus includes a memory, a decoder, an intermediate memory which is disposed between the memory and the decoder and which temporarily stores, in succession, the data that are supplied from the memory and then outputs the data to the decoder, switching circuit for switching an output of the memory to one of the decoder and the intermediate memory, memory management circuit for managing arrangement information of the data that are stored in the memory, determination circuit for determining whether the data that are stored in the memory are arranged in physically discontinuous memory areas of the memory, and switching control circuit for switching, in a case where the determination circuit determines that the data are arranged in the physically divided memory areas, the switching circuit in a manner to input the data output from the memory to the decoder via the intermediate memory.

Abstract: A method, system, and computer program product for prioritizing directory scans in cache by a processor is provided. While traversing a directory in the cache, one of attempting to acquire a lock for a directory entry and attempting to acquire access to a track in the directory entry is performed. If one of the lock is not obtained for the directory entry and the access to the track in the directory entry is not obtained, the directory entry is added to a reserved data space. Following completion of traversing the directory, a return is made to the reserved data space to process the directory entry and the track in the directory entry.

Abstract: A nonvolatile semiconductor memory device for an efficient program of multilevel data includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks. Accordingly, the time taken in programming can be reduced without increasing a unit of program in a multilevel flash memory, thereby improving performance in a multilevel program of a nonvolatile semiconductor memory device.

Abstract: The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory.

Abstract: A method, computer program product, and system for webpage request handling is described. A method may comprise recording, in a memory, a change time for each of a plurality of elements of a website available from an origin server, each time a change to any one of the plurality of elements occurs. The method may further comprise updating a system-last-modified time of the website to a latest change time.

Abstract: A method and system is provided for securing micro-architectural instruction caches (I-caches). Securing an I-cache involves providing security critical instructions to indicate a security critical code section; and implementing an I-cache locking policy to prevent unauthorized eviction and replacement of security critical instructions in the I-cache. Securing the I-cache may further involve dynamically partitioning the I-cache into multiple logical partitions, and sharing access to the I-cache by an I-cache mapping policy that provides access to each I-cache partition by only one logical processor.

Abstract: The page table walker is moved from its conventional location in the memory management unit associated with the data processor to a location in main memory i.e. the main memory controller. As a result, an implementation is provided wherein the processing of requests for data could selectively avoid or bypass cumbersome caches associated with the data processor.

Abstract: A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.

Abstract: A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design is provided. The design structure includes a page table walker. The page table walker is moved from its conventional location in the memory management unit associated with the data processor to a location in main memory i.e. the main memory controller. As a result, wherein the processing of requests for data could selectively avoid or bypass cumbersome caches associated with the data processor.

Abstract: Embodiments of an apparatus, method, and system for encoding direct cache access transactions based on a memory access data structure are disclosed. In one embodiment, an apparatus includes memory access logic and transaction logic. The memory access logic is to determine whether to allow a memory access based on a memory access data structure. The transaction logic is to assign direct cache access attributes to a transaction based on the memory access data structure.

Abstract: A data processing system is provided with a general purpose programmable processor and an accelerator processor. Coherency control circuitry manages data coherence between data items which may be stored within a cache memory and/or a further memory. Memory access requests from the accelerator processor are received by a memory request switching circuitry which is responsive to a signal from the accelerator processor to direct the memory access request either via coherency control circuit or directly to the further memory.

Abstract: The present invention is directed towards a “flash crowd” technique for handling situations where the cache receives additional requests, e.g.,. nearly simultaneous requests, for the same object during the time the server is processing and returning the response object for a first requester. Once all such nearly simultaneous requests are responded to by the cache, the object is flushed from the cache, with no additional expire time or invalidation action needed. This technique of the present invention enables data to be cached and served for very small amounts of time for objects that would otherwise be considered non-cacheable. As such, this technique yields a significant improvement in applications that serve fast changing data to a large volume of concurrent users, such, for example, as real time stock quotes, or a fast evolving news story.

Abstract: Under the present invention, when a request for a web page is received from a client on a server, the web page is built and analyzed for cacheability. If the web page is cacheable, an entity tag is generated. The entity tag generally identifies the various sources of dynamic content in the web page, and includes cacheability flags and time values associated with the dependencies. The entity tag is sent to the client with the web page where it is stored in local cache memory. If a subsequent request for the same web page is issued from the client, the request is accompanied with the entity tag (e.g., in a header). The entity tag is decoded and analyzed by the server to determine whether the cached web page is still valid.

Abstract: A system and method is provided wherein, in one aspect, a currently-requested item of information is stored in a cache based on whether it has been previously requested and, if so, the time of the previous request. If the item has not been previously requested, it may not be stored in the cache. If the subject item has been previously requested, it may or may not be cached based on a comparison of durations, namely (1) the duration of time between the current request and the previous request for the subject item and (2) for each other item in the cache, the duration of time between the current request and the previous request for the other item. If the duration associated with the subject item is less than the duration of another item in the cache, the subject item may be stored in the cache.

Abstract: A data caching method comprising monitoring read and write requests submitted for accessing target data in a first data block on a storage medium; identifying a sequence of access requests for target data as a first stream; and determining whether the first stream is suitable for direct disk access based on inter-arrival times of the read or write requests in the stream.

Abstract: A data packet access control apparatus and a data packet access control method are disclosed. RAM resources in a data packet processing chip are used to implement a Bypass FIFO. The Bypass FIFO is used as a first-level cache for small amount of data, and an external RAM of the data packet processing chip is used as a second-level cache for large amount of data. In this way, some data packets are read and written within the chip and not all data packets have to be read and written through the external RAM. A data packet reading/writing operation may be performed to the external RAM by a BANK interleave mode.

Abstract: A circuit arrangement and method bypass the storage of requested data in a higher level cache of a multi-level memory architecture during the return of the requested data to a requester, while caching the requested data in a lower level cache. For certain types of data, e.g., data that is only used once and/or that is rarely modified or written back to memory, bypassing storage in a higher level cache reduces the likelihood of the requested data casting out frequently used data from the higher level cache. By caching the data in a lower level cache, however, the lower level cache can still snoop data requests and return requested data in the event the data is already cached in the lower level cache.

Abstract: Upon receiving a request for one or a set of data blocks associated with a given data segment, a disk cache controller may retrieve into cache the some part of the entire data segment from a disk. Each data segment on a disk may include a fixed number of data blocks, and all data segments may include the same number of data blocks. Data segments may be dynamically defined and their locations and sizes may vary from segment to segment. Data segments may be defined when data is written to the disk, or may be defined at a later point. A table associated with a cache controller may store information as to the physical location or address on a disk of the starting point and/or size of each data segment.

Abstract: A processor is provided. The processor includes at least two cores. The at least two cores have a first level cache memory and are multi-threaded. A crossbar is included. A plurality of cache bank memories in communication with the at least two cores through the crossbar is provided. Each of the plurality of cache bank memories communicates with a main memory interface. A plurality of input/output interface modules in communication with the main memory interface and providing a link to the at least two cores are included. The link bypasses the plurality of cache bank memories and the crossbar. Threading hardware configured to enable the at least two cores to switch from a first thread to a second thread in a manner hiding delays caused by cache accesses is included. A server and a method for determining when to switch threads in a multi-core multi-thread environment are included.

Abstract: Unobservable memory regions, referred to as stealth memory regions, are allocated or otherwise provided to store data whose secrecy is to be protected. The stealth memory is prevented from exposing information about its usage pattern to an attacker or adversary. In particular, the usage patterns may not be deduced via the side-channels.

Abstract: A computing system includes: first and second I/O interfaces that are associated with a server; and an I/O management unit that connects the server with the first and second I/O interfaces. The I/O management unit includes: an I/O buffer; an I/O mapping unit that stores an access request of the server to the first I/O interface in the I/O buffer in response to a change start request of the first I/O interface associated with the server to the second I/O interface; an I/O changing unit that associates the second I/O interface with the server; and an I/O synchronizing unit that converts the access request stored in the I/O buffer into an access request to the second I/O interface, in response to the completion of the association by the I/O changing unit, and executes the converted access request.

Abstract: A system and method for dynamically selecting the data fetch path for improving the performance of the system improves data access latency by dynamically adjusting data fetch paths based on application data fetch characteristics. The application data fetch characteristics are determined through the use of a hit/miss tracker. It reduces data access latency for applications that have a low data reuse rate (streaming audio, video, multimedia, games, etc.) which will improve overall application performance. It is dynamic in a sense that at any point in time when the cache hit rate becomes reasonable (defined parameter), the normal cache lookup operations will resume. The system utilizes a hit/miss tracker which tracks the hits/misses against a cache and, if the miss rate surpasses a prespecified rate or matches an application profile, the hit/miss tracker causes the cache to be bypassed and the data is pulled from main memory or another cache thereby improving overall application performance.

Abstract: The present disclosure relates to methods, devices and computer-readable medium for implementing a caching policy and/or a cache flushing policy in a peripheral non-volatile storage device operatively coupled to a host device. In some embodiments, data is stored to a cache area of a non-volatile memory within the peripheral non-volatile storage device in accordance with a historical rate at which other data was received by the peripheral storage device from the host device and/or a historical average time interval between successive host write requests received and/or an assessed rate at which data is required to be written to the non-volatile memory and/or a detecting by the peripheral non-volatile memory device that the host has read the storage ready/busy flag. In some embodiments, data is copied from a cache storage area of the non-volatile memory to a main storage area in accordance with the historical rate and/or the historical average time interval.

Abstract: An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.

Abstract: Techniques are generally described for a multi-core processor with a plurality of processor cores. At least one cache is accessible to at least two of the plurality of processor cores. The multi-core processor can be configured for separately allocating a memory space within the cache to the individual processor cores accessing the cache.

Abstract: A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.

Abstract: A method, system, and computer program product for prioritizing directory scans in cache by a processor is provided. While traversing a directory in the cache, one of attempting to acquire a lock for a directory entry and attempting to acquire access to a track in the directory entry is performed. If one of the lock is not obtained for the directory entry and the access to the track in the directory entry is not obtained, the directory entry is added to a reserved data space. Following completion of traversing the directory, a return is made to the reserved data space to process the directory entry and the track in the directory entry.

Abstract: A computer-implemented method for controlling initialization of a fingerprint cache for data deduplication associated with a single-instance-storage computing subsystem may comprise: 1) detecting a request to store a data selection to the single-instance-storage computing subsystem, 2) leveraging a client-side fingerprint cache associated with a previous storage of the data selection to the single-instance-storage computing subsystem to initialize a new client-side fingerprint cache, and 3) utilizing the new client-side fingerprint cache for data deduplication associated with the request to store the data selection to the single-instance-storage computing subsystem. Other exemplary methods of controlling initialization of a fingerprint cache for data deduplication, as well as corresponding exemplary systems and computer-readable-storage media, are also disclosed.

Abstract: A processing system may include a memory configured to store data in a plurality of pages, a TLB, and a memory cache including a plurality of cache lines. Each page in the memory may include a plurality of lines of memory. The memory cache may permit, when a virtual address is presented to the cache, a matching cache line to be identified from the plurality of cache lines, the matching cache line having a matching address that matches the virtual address. The memory cache may be configured to permit one or more page attributes of a page located at the matching address to be retrieved from the memory cache and not from the TLB, by further storing in each one of the cache lines a page attribute of the line of data stored in the cache line.

Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.

Abstract: The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory.

Abstract: In one embodiment, the present invention includes a method for receiving a snoop request, providing the snoop request to a coherency engine along a first path and providing the snoop request to a bypass logic along a bypass path, and generating a speculative invalid snoop response in the bypass logic and forwarding the speculative invalid snoop response to indicate that an address associated with the snoop response is not present in a cache memory. Other embodiments are described and claimed.

Abstract: A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.

Abstract: A data processing apparatus is provided wherein processing circuitry executes multiple program threads including at least one high priority thread and at least one lower priority thread. Instructions required by the threads are retrieved from a cache memory hierarchy comprising multiple cache levels. The cache memory hierarchy includes a bypass path for omitting a predetermined level of the cache memory hierarchy when performing a lookup procedure for a required instruction and for bypassing said predetermined level of the cache memory hierarchy when returning said required instruction to said processing circuitry. The bypass path is used by default when the requested instruction is for a lower priority thread.

Abstract: An outgoing message judging device judges if an outgoing message transmitted by a sending process is cacheable or not; An outgoing message queue queues the outgoing message, when the judging result indicates to be noncacheable. A returning message judging device judges if a returning message transmitted by a receiving process is cacheable or not; A returning message queue queues the returning message, when the judging result indicates to be noncacheable. A message cache unit stores the returning message in association with the outgoing message corresponding to the outgoing message when the judgment result is cacheable, or caches the returning message corresponding to the outgoing message to transmit the returning message to the returning message queue when the judgment result is cacheable.

Abstract: A system and method for an efficient implementation of a software-managed cache is presented. When an application thread executes on a simple processor, the application thread uses a conditional data select instruction for eliminating a conditional branch instruction when accessing a software-managed cache. An application thread issues a conditional data select instruction (DMA transfer) after a cache directory lookup, wherein the size of the requested data is dependent upon the outcome of the cache directory lookup. When the cache directory lookup results in a cache hit, the application thread requests a transfer of zero bits of data, which results in a DMA controller (DMAC) performing a no-op instruction. When the cache directory lookup results in a cache miss, the application thread requests a data block transfer the size of a corresponding cache line.

Abstract: A system comprises tag memories and data memories. Sources use the tag memories with the data memories as a cache. Arbitration of a cache request is replayed, based on an arbitration miss and way hit, without accessing the tag memories. A method comprises receiving a cache request sent by a source out of a plurality of sources. The sources use tag memories with data memories as a cache. The method further comprises arbitrating the cache request, and replaying arbitration, based on an arbitration miss and way hit, without accessing the tag memories.

Abstract: In one embodiment, the present invention includes a method for routing an early request for requested data on a bypass path around a transaction processing path of a first agent if the requested data is not present in a cache memory of the first agent, and opportunistically transmitting the early request from the first agent to a second agent based on load conditions of an interconnect between the first agent and the second agent. In this way, reduced memory latencies may be realized. Other embodiments are described and claimed.

Abstract: This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core bypasses immediate cache memory units with low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

Abstract: A method of obtaining data, comprising at least one sector, for use by at least a first thread wherein each processor cycle is allocated to at least one thread, includes the steps of: requesting data for at least a first thread; upon receipt of at least a first sector of the data, determining whether the at least first sector is aligned with the at least first thread, wherein a given sector is aligned with a given thread when a processor cycle in which the given sector will be written is allocated to the given thread; responsive to a determination that the at least first sector is aligned with the at least first thread, bypassing the at least first sector, wherein bypassing a sector comprises reading the sector while it is being written; and responsive to a determination that the at least first sector is not aligned with the at least first thread, delaying the writing of the at least first sector until the occurrence of a processor cycle allocated to the at least first thread by retaining the at least first s

Abstract: A first storage system is connected to a second storage system, and an external device within the first storage system is provided to a host as a device of the second storage system. The second storage system includes a cache control section having cache adaptors, each controlling a disk and a cache, a protocol conversion section including protocol adaptors that switch requests from the host to appropriate ones of the cache adaptors, a management adaptor, and an internal network that mutually connects the cache adaptors, the protocol adaptors and the management adaptor. The first storage system being connected to any of the protocol adaptors is connected to the second storage system. The second storage system executes a processing for the external device by the cache control section, or connects to the first storage system through the protocol conversion section without the cache control section executing processing for the external device.

Abstract: A computing system may comprise a processor and a memory controller hub coupled by an external bus such as the front side bus. The processor may also comprise a cache. The processor may operate in SMM and the memory coupled to the memory controller hub may comprise SMM spaces such as compatible, HSEG, and TSEG areas. A software-based attack may write malicious instructions into the cache at an address corresponding to the SMM spaces. The illegal processor memory accesses that occur entirely inside the processor caches due to the cache attack may be forced to occur on the external bus. The memory controller hub may be capable of handling the memory accesses occurring on the external bus thus, protecting the SMM spaces against cache attack.

Abstract: A technique for partially offloading, from a main cache in a storage server, the storage of cache tags for data blocks in a victim cache of the storage server, is described. The technique includes storing, in the main cache, a first subset of the cache tag information for each of the data blocks, and storing, in a victim cache of the storage server, a second subset of the cache tag information for each of the data blocks. This technique avoids the need to store the second subset of the cache tag information in the main cache.

Abstract: A method and apparatus used within memory and data processing that reduces the number of references allowed in processor cache by using active rows to reject references that are less frequently used from the cache. Comparators within a memory controller are used to generate a signal indicative of a row hit or miss, which signal is then applied to one or more demultiplexers to enable or disable transfer of a memory reference to processor cache locations. The cache may be level one (L1) or level two (L2) caches including data and or instructions or some combination of L1, L2, data, and instructions.

Abstract: Methods for reducing data cache access power in a processor. In an embodiment, a micro tag array is used to store base address or base register data bits, offset data bits, a carry bit, and way selection data bits associated with cache accesses. When a LOAD or a STORE instruction is fetched, at least a portion of the base address and at least a portion of the offset of the instruction are compared to data stored in the micro tag array. If a micro tag array hit occurs, the micro tag array generates a cache dataram enable signal. This signal activates only the cache dataram that stores the needed data.

Abstract: A method and system for gathering enriched web server activity data in a global communications network in which requested information files are cached at a plurality of network devices. With the prevalence of web caching on the Internet, the origin web servers do not serve the majority of requests for web site content. A single pixel clear Graphics Image Format (GIF) request is added to the HyperText Markup Language (HTML) source file for a web page. Appended to the GIF request is a Common Gateway Interface (CGI) string of data that contains enhanced web activity data information, including the number of images (“hits”) that have to be retrieved by a client browser to build the web page, and the referring identifier that resulted in access to the web page. The single pixel clear GIF request is not cacheable and results in the request being transmitted to the origin web server when the client browser interprets the HTML file.