Cache Status Data Bit Patents (Class 711/144)
  • Patent number: 10372624
    Abstract: Provided are techniques for destaging pinned retryable data in cache. A ranks scan structure is created with an indicator for each rank of multiple ranks that indicates whether pinned retryable data in a cache for that rank is destageable. A cache directory is partitioned into chunks, wherein each of the chunks includes one or more tracks from the cache. A number of tasks are determined for the scan of the cache. The number of tasks are executed to scan the cache to destage pinned retryable data that is indicated as ready to be destaged by the ranks scan structure, wherein each of the tasks selects an unprocessed chunk of the cache directory for processing until the chunks of the cache directory have been processed.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta
  • Patent number: 10353606
    Abstract: A host divides a dataset into stripes and sends the stripes to respective data chips of a distributed memory buffer system, where the data chips buffer the respective slices. Each data chip can buffer stripes from multiple datasets. Through the use of: (i) error detection methods; (ii) tagging the stripes for identification; and (iii) acknowledgement responses from the data chips, the host keeps track of the status of each slice at the data chips. If errors are detected for a given stripe, the host resends the stripe in the next store cycle, concurrently with stripes for the next dataset. Once all stripes have been received error-free across all the data chips, the host issues a store command which triggers the data chips to move the respective stripes from buffer to memory.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Susan M. Eickhoff, Steven R. Carlough, Patrick J. Meaney, Stephen J. Powell, Jie Zheng, Gary A. Van Huben
  • Patent number: 10324843
    Abstract: A method, computer program product, and computing system for receiving an indication of an intent to restore at least a portion of a data array based upon a historical record of the data array. One or more changes made to the content of that data array after the generation of the historical record may be identified, thus generating a differential record. One or more data entries within a cache memory system associated with the at least a portion of a data array may be invalidated based, at least in part, upon the differential record.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: June 18, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: David Erel, Assaf Natanzon
  • Patent number: 10275288
    Abstract: The invention concerns a processing system comprising: a compute node (20) having one or more processors and one or more memory devices storing software enabling virtual computing resources and virtual memory to be assigned to support a plurality of virtual machines (VM1); a reconfigurable circuit (301) comprising a dynamically reconfigurable portion (302) comprising one or more partitions (304) that are reconfigurable during runtime and implement at least one hardware accelerator (ACC #1 to #N) assigned to at least one of the plurality of virtual machines (VM); and a virtualization manager (306) providing an interface between the at least one hardware accelerator (ACC #1 to #N) and the compute node (202) and comprising a circuit (406) adapted to translate, for the at least one hardware accelerator, virtual memory addresses into corresponding physical memory addresses to permit communication between the one or more hardware accelerators and the plurality of virtual machines.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: April 30, 2019
    Assignee: Virtual Open Systems
    Inventors: Christian Pinto, Michele Paolino, Salvatore Daniele Raho
  • Patent number: 10241715
    Abstract: A method for rendering data invalid within a memory array is described. The method includes establishing governing metadata for a memory location within a memory array. The method also includes receiving a request to retrieve data from the memory location. The method also includes determining whether color metadata associated with the data matches the governing metadata. The method also includes returning the data when the color metadata matches the governing metadata. The method also includes returning invalidated data when the color metadata does not match the governing metadata.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: March 26, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Siamak Tavallaei, Russ W. Herrell
  • Patent number: 10243990
    Abstract: A system and method for detecting replay attacks on secure data are disclosed. A system on a chip (SOC) includes a security processor. Blocks of data corresponding to sensitive information are stored in off-chip memory. The security processor uses an integrity data structure, such as an integrity tree, for the blocks. The intermediate nodes of the integrity tree use nonces which have been generated independent of any value within a corresponding block. By using only the nonces to generate tags in the root at the top layer stored in on-chip memory and the nodes of the intermediate layers stored in off-chip memory, an amount of storage used is reduced for supporting the integrity tree. When the security processor detects events which create access requests for one or more blocks, the security processor uses the integrity tree to verify a replay attack has not occurred and corrupted data.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: March 26, 2019
    Assignee: Apple Inc.
    Inventors: Zhimin Chen, Timothy R. Paaske, Gilbert H. Herbeck
  • Patent number: 10235175
    Abstract: A processor of an aspect includes a plurality of logical processors. A first logical processor of the plurality is to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory. The processor also includes memory access synchronization relaxation logic that is to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Martin G. Dixon, William C. Rash, Yazmin A. Santiago
  • Patent number: 10235302
    Abstract: In an embodiment, a processor for invalidating cache entries comprises: at least one processing unit; a processor cache; and direct cache unit. The direct cache unit is to receive, from a first device, a direct read request for data in a first cache entry in the processor cache; determine whether the direct read request is an invalidating read request; in response to a determination that the direct read request is an invalidating read request: send the data in the first cache entry directly from the processor cache to the first device without accessing a main memory; and invalidate the first cache entry in the processor cache. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Samantha J. Edirisooriya, Geetani R. Edirisooriya
  • Patent number: 10230402
    Abstract: A data processing apparatus includes a memory, a processor which outputs write data when making a write request to the memory, and which inputs read data when making a read request to the memory, a parity generating circuit which generates a parity comprising a plurality of parity bits from the write data, the parity being written with the write data into the memory, and a parity check circuit which is coupled between the memory and the processor, and which detects a presence or absence of an error of one bit or two bits in the read data and the parity read from the memory, wherein the parity generating circuit generates the parity so that at least one of a first write data bit and a second write data bit included in the write data contributes to generation of at least two parity bits.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: March 12, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yukitoshi Tsuboi, Hideo Nagano
  • Patent number: 10230583
    Abstract: Techniques for simulation of objects in a multi-node environment are described herein. Ownership of objects in a simulation scenario is assigned to a plurality of nodes based on a first set of criteria. Simulation authority of the first object is assumed by a second node based on a second set of criteria. Simulation of the first object is performed by the second node without previous acknowledgment, by the first node, of the assumption of simulation authority. Ownership of the first object is maintained by the first node during the time that the second node has simulation authority of the first object.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: March 12, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Pablo Puo Hen Cheng, Jesse Aaron Van Beurden, Rosen Ognyanov Baklov, Igor Gorelik
  • Patent number: 10229127
    Abstract: In one embodiment, a computer-implemented method includes capturing a consistent state of data blocks in a namespace cache of a deduplicating storage system. The data blocks contains data for a file system namespace organized in a hierarchical data structure. Each leaf page of the hierarchical data structure contains one or more data blocks. The method further includes determining, for each data block, whether the data block has been written to base on the captured consistent state. For at least one of the written data blocks in the namespace cache, the method includes searching, in the hierarchical data structure, adjacent data blocks to find in the namespace cache one or more data blocks that have also been written to, and upon finding the one or more adjacent written data blocks, flushing the written data block and the found one or more adjacent written data blocks together into a common storage unit.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: March 12, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Pengju Shang, Pranay Singh, George Mathew
  • Patent number: 10203958
    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces addresses of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Stream metadata is stored in response to a stream store instruction. Stored stream metadata is restored to the stream engine in response to a stream restore instruction. An interrupt changes an open stream to a frozen state discarding stored stream data. A return from interrupt changes a frozen stream to an active state.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: February 12, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Joseph Zbiciak, Timothy D. Anderson
  • Patent number: 10169254
    Abstract: Embodiments of techniques and systems for increasing efficiencies in computing systems using virtual memory are described. In embodiments, instructions which are located in two memory pages in a virtual memory system, such that one of the pages does not permit execution of the instructions located therein, are identified and then executed under temporary permissions that permit execution of the identified instructions. In various embodiments, the temporary permissions may come from modified virtual memory page tables, temporary virtual memory page tables which allow for execution, and/or emulators which have root access. In embodiments, per-core virtual memory page tables may be provided to allow two cores of a computer processor to operate in accordance with different memory access permissions. In embodiments, a physical page permission table may be utilized to provide for maintenance and tracking of per-physical-page memory access permissions. Other embodiments may be described and claimed.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventors: Ramesh Thomas, Kuo-Lang Tseng, Ravi L. Sahita, David M. Durham, Madhukar Tallam
  • Patent number: 10146602
    Abstract: A host data processing system provides a virtual operating environment for a guest data processing system. A transaction is initiated for translation of a guest system memory address to a host system physical address in response to a transaction request from a device overseen by a guest system. For a stalled transaction incurring an error, the following are performed: (i) storing identification information relating to that transaction including data identifying the requesting device; (ii) providing translation error condition information to the overseeing guest system; and (iii) deferring handling of the stalled transaction until a subsequent command is received from that guest system. Initiation of a closure process for a guest system initiates cancellation of certain stalled transactions.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: December 4, 2018
    Assignee: ARM Limited
    Inventor: Matthew Lucien Evans
  • Patent number: 10133669
    Abstract: An example system on a chip (SoC) includes a cache, a processor, and a predictor circuit. The cache may store data. The processor may be coupled to the cache and store a first data set at a first location in the cache and receive a first request from an application to write a second data set to the cache. The predictor circuit may be coupled to the processor and determine that a second location where the second data set is to be written to in the cache is nonconsecutive to the first location, where the processor is to perform a request-for-ownership (RFO) operation for the second data set and write the second data set to the cache.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Pavel I. Kryukov, Stanislav Shwartsman, Joseph Nuzman, Alexandr Titov
  • Patent number: 10114747
    Abstract: Systems and methods for performing operations on memory of a computing device are disclosed. According to an aspect, a method includes storing update data on a first memory of a computing device, wherein the update data comprises data for updating a second memory on the computing device. The method also includes initiating an update mode on the second memory. Further, the method includes suspending an I/O operation of the second memory. The method also includes switching the computing device to a system management mode (SMM) while the second memory is in the update mode. Further, the method includes retrieving the update data from the first memory. The method also includes determining whether the update data is valid. The method also includes resuming the I/O operation of the second memory for updating the second memory based on the retrieved update data in response to determining that the update data is valid.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: October 30, 2018
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Shiva R. Dasari, Scott N. Dunham, Sumeet Kochar
  • Patent number: 10095633
    Abstract: A web server cache performs verification of cached computational results by storing a computed function result as a cached value in a cache, and upon receiving a subsequent invocation of the function, examining a duration of the value in the cache. The web server compares, if the duration exceeds a staleness detection threshold, a result of a subsequent execution of the function to the cached value in response to the subsequent invocation by recomputing, a result from execution of the function for validating the cached value, and flags an error if the duration exceeds the staleness detection threshold and the result differs from the cached value. Alternatively, the method returns, if the duration of the cache value is within the staleness detection threshold, the cache value as the result of the subsequent invocation.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: October 9, 2018
    Assignee: ARXAN TECHNOLOGIES, INC.
    Inventors: Frank Feng-Chun Chiang, Ashkan Nasseri
  • Patent number: 10095557
    Abstract: Processing logic and a method to provide single thread access to a specific memory region without suspending processing activity for all other cores and/or threads within or in association with a processor, computer system, or other processing apparatus. Single thread access may be provided through implementation of microcode which may control thread access to model specific registers (“MSRs”) within a processor. One MSR may provide a mutex, which a single thread may claim, and another MSR may provide a range of memory locations, which may be accessed by the thread that has claimed the mutex.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventor: Nicholas J. Adams
  • Patent number: 10078597
    Abstract: A processor including a memory that stores a system management mode (SMM) value indicative of whether the processor is in SMM, a translation address cache (TAC) that includes multiple entries for storing address translations, in which each entry includes an SMM identifier, hit logic that compares a lookup address with address translations stored in the TAC for determining a hit, in which the hit logic determines a hit only when a corresponding SMM identifier of an entry matches the SMM value, and entry logic that selects an entry of the TAC for storing a determined address translation and that programs an SMM identifier of the selected entry of the TAC to match the SMM value. The processor may include flush logic that distinguishes SMM entries, and processing logic that commands flushing upon entering and/or exiting SMM. Non-SMM entries may remain in the TAC when entering and exiting SMM.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: September 18, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: Viswanath Mohan
  • Patent number: 10019377
    Abstract: The described embodiments include a computing device with two or more types of processors and a memory that is shared between the two or more types of processors. The computing device performs operations for handling cache coherency between the two or more types of processors. During operation, the computing device sets a cache coherency indicator in metadata in a page table entry in a page table, the page table entry information about a page of data that is stored in the memory. The computing device then uses the cache coherency indicator to determine operations to be performed when accessing data in the page of data in the memory. For example, the computing device can use the coherency indicator to determine whether a coherency operation is to be performed when a processor of a given type accesses data in the page of data in the memory.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: July 10, 2018
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Arkaprava Basu, Bradford M. Beckmann, Shuai Che, Sooraj Puthoor
  • Patent number: 10007619
    Abstract: Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.
    Type: Grant
    Filed: September 20, 2015
    Date of Patent: June 26, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jason Edward Podaima, Paul Christopher John Wiercienski, Carlos Javier Moreira, Alexander Miretsky, Meghal Varia, Kyle John Ernewein, Manokanthan Somasundaram, Muhammad Umar Choudry, Serag Monier Gadelrab
  • Patent number: 9990257
    Abstract: One or more techniques and/or systems are provided for hosting a virtual machine from a snapshot. In particular, a snapshot of a virtual machine hosted on a primary computing device may be created. The virtual machine may be hosted on a secondary computing device using the snapshot, for example, when a failure of the virtual machine on the primary computing device occurs. If a virtual machine type (format) of the snapshot is not supported by the secondary computing device, then the virtual machine within the snapshot may be converted to a virtual machine type supported by the secondary computing device. In this way, the virtual machine may be operable and/or accessible on the secondary computing device despite the failure. Hosting the virtual machine on the secondary computing device provides, among other things, fault tolerance for the virtual machine and/or applications comprised therein.
    Type: Grant
    Filed: September 7, 2015
    Date of Patent: June 5, 2018
    Assignee: NetApp Inc.
    Inventors: Eric Paul Forgette, Deepak Kenchammana-Hosekote, Shravan Gaonkar, Arthur Franklin Lent
  • Patent number: 9983995
    Abstract: A cache and a method for operating a cache are disclosed. In an embodiment, the cache includes a cache controller, data cache and a delay write through cache (DWTC), wherein the data cache is separate and distinct from the DWTC, wherein cacheable write accesses are split into shareable cacheable write accesses and non-shareable cacheable write accesses, wherein the cacheable shareable write accesses are allocated only to the DWTC, and wherein the non-shareable cacheable write accesses are not allocated to the DWTC.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: May 29, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Sushma Wokhlu, Alan Gatherer, Ashish Rai Shrivastava
  • Patent number: 9971693
    Abstract: Various embodiments provide for a system that prefetches data from a main memory to a cache and then evicts unused data to a lower level cache. The prefetching system will prefetch data from a main memory to a cache, and data that is not immediately useable or is part of a data set which is too large to fit in the cache can be tagged for eviction to a lower level cache, which keeps the data available with a shorter latency than if the data had to be loaded from main memory again. This lowers the cost of prefetching useable data too far ahead and prevents cache trashing.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: May 15, 2018
    Assignee: Ampere Computing LLC
    Inventor: Kjeld Svendsen
  • Patent number: 9946648
    Abstract: A method includes linking together a set of cache lines, tracking historical changes to the cache coherency protocol states of the set of cache lines, and prefetching to a cache the set of cache lines based at least on the historical changes to the set of cache lines. A cache circuit includes one or more random access memories (RAMs) to store cache lines and cache coherency protocol states of the cache lines and a prefetch logic unit to link together a set of cache lines, to track historical changes to cache coherency protocol states of the set of cache lines, and to prefetch to the cache circuit the set of cache lines based at least on the historical changes to the set of cache lines.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: April 17, 2018
    Assignee: Marvell International Ltd.
    Inventor: Wei Zhang
  • Patent number: 9946656
    Abstract: A completion packet may be returned before a data packet is written to a memory, if a field of the data packet indicates the data packet was sent due to a cache capacity eviction. The completion packet is returned after the data packet is written to the memory, if the field indicates the data packet was sent due to a flush operation.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: April 17, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Derek Alan Sherlock
  • Patent number: 9940247
    Abstract: The present application describes embodiments of a method and apparatus for concurrently accessing dirty bits in a cache. One embodiment of the apparatus includes a cache configurable to store a plurality of lines. The lines are grouped into a plurality of subsets the plurality of lines. This embodiment of the apparatus also includes a plurality of dirty bits associated with the plurality of lines and first circuitry configurable to concurrently access the plurality of dirty bits associated with at least one of the plurality of subsets of lines.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: April 10, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventor: William L. Walker
  • Patent number: 9898398
    Abstract: Reusing data in a memory buffer. A method includes reading data into a first portion of memory of a buffer implemented in the memory. The method further includes invalidating the data and marking the first portion of memory as free such that the first portion of memory is marked as being usable for storing other data, but where the data is not yet overwritten. The method further includes reusing the data in the first portion of memory after the data has been invalidated and the first portion of the memory is marked as free.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: February 20, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Cristian Petculescu, Amir Netz
  • Patent number: 9891936
    Abstract: An apparatus and method for page level monitoring are described. For example, one embodiment of a method for monitoring memory pages comprises storing information related to each of a plurality of memory pages including an address identifying a location for a monitor variable for each of the plurality of memory pages in a data structure directly accessible only by a software layer operating at or above a first privilege level; detecting virtual-to-physical page mapping consistency changes or other page modifications to a particular memory page for which information is maintained in the data structure; responsively updating the monitor variable to reflect the consistency changes or page modifications; checking a first monitor variable associated with a first memory page prior to execution of first program code; and refraining from executing the first program code if the first monitor variable indicates consistency changes or page modifications to the first memory page.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Jiwei Oliver Lu, Koichi Yamada, James D. Beany, Palaniverlrajan Shanmugavelayutham, Bo Zhang
  • Patent number: 9891916
    Abstract: A hardware data prefetcher is comprised in a memory access agent, wherein the memory access agent is one of a plurality of memory access agents that share a memory. The hardware data prefetcher includes a prefetch trait that is initially either exclusive or shared. The hardware data prefetcher also includes a prefetch module that performs hardware prefetches from a memory block of the shared memory using the prefetch trait. The hardware data prefetcher also includes an update module that performs analysis of accesses to the memory block by the plurality of memory access agents and, based on the analysis, dynamically updates the prefetch trait to either exclusive or shared while the prefetch module performs hardware prefetches from the memory block using the prefetch trait.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: February 13, 2018
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Rodney E. Hooker, Albert J. Loper, John Michael Greer, Meera Ramani-Augustin
  • Patent number: 9892051
    Abstract: A method can include executing a store instruction that instructs storing of data at an address and, in response to the store instruction, inserting a preloading instruction after the store instruction but before a dependent load instruction to the address. Executing the store instruction can include invalidating a data entry of a cache array at an address of the cache array corresponding to the address and writing the data to a backing memory at an address of the backing memory corresponding to the address. The preloading instruction can cause filling the data entry of the cache array, at the address of the cache array corresponding to the address, with the data from the backing memory at the address of the backing memory corresponding to the address and validating the data entry of the cache array.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: February 13, 2018
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Sujat Jamil, R. Frank O'Bleness, Russell J. Robideau, Tom Hameenanttila, Joseph Delgross, David E. Miner
  • Patent number: 9886392
    Abstract: A method of enhancing a refresh PCI translation (RPCIT) operation to refresh a translation lookaside buffer (TLB) includes determining, by a computer processor, a request to perform at least one RPCIT instruction for purging at least one translation from the TLB. The method further includes purging, by the computer processor, the at least one translation from the TLB in response to executing the at least one RPCIT instruction. The computer processor selectively performs a synchronization operation prior to completing the at least one RPCIT instruction.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: February 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Thomas A. Gregg, Dan F. Greiner, Damian L. Osisek
  • Patent number: 9880942
    Abstract: A method of enhancing a refresh PCI translation (RPCIT) operation to refresh a translation lookaside buffer (TLB) includes determining, by a computer processor, a request to perform at least one RPCIT instruction for purging at least one translation from the TLB. The method further includes purging, by the computer processor, the at least one translation from the TLB in response to executing the at least one RPCIT instruction. The computer processor selectively performs a synchronization operation prior to completing the at least one RPCIT instruction.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: January 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Thomas A. Gregg, Dan F. Greiner, Damian L. Osisek
  • Patent number: 9864692
    Abstract: Managing cache evictions during transactional execution of a process. Based on initiating transactional execution of a memory data accessing instruction, memory data is fetched from a memory location, the memory data to be loaded as a new line into a cache entry of the cache. Based on determining that a threshold number of cache entries have been marked as read-set cache lines, determining whether a cache entry that is a read-set cache line can be replaced by identifying a cache entry that is a read-set cache line for the transaction that contains memory data from a memory address within a predetermined non-conflict address range. Then invalidating the identified cache entry of the transaction. Then loading the fetched memory data into the identified cache entry, and then marking the identified cache entry as a read-set cache line of the transaction.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Dan F. Greiner, Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9804801
    Abstract: A method of processing data in a memory system including a control unit and a hybrid memory device having a first memory and a second memory, includes; receiving first write data, storing the first write data in the first memory and assigning a first group state from among a plurality of group states to the stored first write data in response to first attribution information, completing a data processing operation in the memory system directed to the stored first write data that changes the attribution information associated with the stored first write data by monitoring of the first attribution information using an operating system running on the memory controller, and changing the first group state assigned to the stored first write data to a second group state from among the plurality of group states, the second group state having a different priority than a priority for the first group state.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangkwon Moon, Jin-Soo Kim, Young-Sik Lee, Jinkyu Jeong, Kyung Ho Kim
  • Patent number: 9773048
    Abstract: A method includes processing a transaction on an in memory database where data being processed has a validity time, updating a time dependent data view responsive to the transaction being processed to capture time validity information regarding the data, and storing the time validity information in a historization table to provide historical access to past time dependent data following expiration of the validity time.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: September 26, 2017
    Assignee: SAP SE
    Inventor: Siar Sarferaz
  • Patent number: 9766820
    Abstract: An arithmetic processing device which connects to a main memory, the arithmetic processor includes a cache memory which stores data, an arithmetic unit which performs an arithmetic operation for data stored in the cache memory, a first control device which controls the cache memory and outputs a first request which reads the data stored in the main memory, and a second control device which is connected to the main memory and transmits a plurality of second requests which are divided the first request output from the first control device, receives data corresponding to the plurality of second requests which is transmitted from the main memory and sends each of the data to the first control device.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: September 19, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yuta Toyoda, Koji Hosoe, Masatoshi Aihara, Akio Tokoyoda, Makoto Suga
  • Patent number: 9760488
    Abstract: A cache system is provided. The cache system includes a first cache and a second cache. The first cache is configured for storing a first status of a plurality of data. The second cache is configured for storing a table. The table includes the plurality of data arranged from a highest level to a lowest level. The cache system is configured to update the first status of the plurality of data in the first cache. The cache system is further configured to update the table in the second cache according to the first status of the plurality of data.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: September 12, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hung-Sheng Chang, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 9760486
    Abstract: Technologies are generally described herein for accelerating a cache state transfer in a multicore processor. The multicore processor may include first, second, and third tiles. The multicore processor may initiate migration of a thread executing on the first core at the first tile from the first tile to the second tile. The multicore processor may determine block addresses of blocks to be transferred from a first cache at the first tile to a second cache at the second tile, and identify that a directory at the third tile corresponds to the block addresses. The multicore processor may update the directory to reflect that the second cache shares the blocks. The multicore processor may transfer the blocks from the first cache in the first tile to the second cache in the second tile effective to complete the migration of the thread from the first tile to the second tile.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: September 12, 2017
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 9749190
    Abstract: A computer-implemented method is operable on a device having hardware including memory and at least one processor. The method includes maintaining invalidation information in a list at a service on the device, where the invalidation information includes a plurality of invalidation commands. At least some of the invalidation commands in the list are selectively combined to form at least one other invalidation command in the list.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: August 29, 2017
    Assignee: LEVEL 3 COMMUNICATIONS, LLC
    Inventors: Christopher Newton, Lewis Robert Varney, Laurence R. Lipstone, William Crowder, Andrew Swart
  • Patent number: 9710266
    Abstract: A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary; or it may be dynamically determined.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: July 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 9710267
    Abstract: A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary; or it may be dynamically determined.
    Type: Grant
    Filed: March 3, 2013
    Date of Patent: July 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 9697130
    Abstract: A cache automation module detects the deployment of storage resources in a virtual computing environment and, in response, automatically configures cache services for the detected storage resources. The automation module may detect new storage resources by monitoring storage operations and/or requests, by use of an interface provided by virtualization infrastructure, and/or the like. The cache automation module may deterministically identify storage resources that are to be cached and automatically caching services for the identified storage resources.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: July 4, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Jaidil Karippara, Pavan Pamula, Yuepeng Feng, Vikuto Atoka Sema
  • Patent number: 9665658
    Abstract: One embodiment provides an eviction system for dynamically-sized caching comprising a non-blocking data structure for maintaining one or more data nodes. Each data node corresponds to a data item in a cache. Each data node comprises information relating to a corresponding data item. The eviction system further comprises an eviction module configured for removing a data node from the data structure, and determining whether the data node is a candidate for eviction based on information included in the data node. If the data node is not a candidate for eviction, the eviction module inserts the data node back into the data structure; otherwise the eviction module evicts the data node and a corresponding data item from the system and the cache, respectively. Data nodes of the data structure circulate through the eviction module until a candidate for eviction is determined.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: May 30, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gage W. Eads, Juan A. Colmenares
  • Patent number: 9639276
    Abstract: A request is received over a link that requests a particular line in memory. A directory state record is identified in memory that identifies a directory state of the particular line. A type of the request is identified from the request. It is determined that the directory state of the particular line is to change from the particular state to a new state based on the directory state of the particular line and the type of the request. The directory state record is changed, in response to receipt of the request, to reflect the new state. A copy of the particular line is sent in response to the request.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventor: Robert G. Blankenship
  • Patent number: 9619396
    Abstract: A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: April 11, 2017
    Assignee: Intel Corporation
    Inventors: Robert G. Blankenship, Jeffrey D. Chamberlain, Yen-Cheng Liu, Vedaraman Geetha
  • Patent number: 9600438
    Abstract: A method and apparatus for controlling and coordinating a multi-component system. Each component in the system contains a computing device. Each computing device is controlled by software running on the computing device. A first portion of the software resident on each computing device is used to control operations needed to coordinate the activities of all the components in the system. This first portion is known as a “coordinating process.” A second portion of the software resident on each computing device is used to control local processes (local activities) specific to that component. Each component in the system is capable of hosting and running the coordinating process. The coordinating process continually cycles from component to component while it is running.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: March 21, 2017
    Assignee: Florida Institute for Human and Machine Cognition, Inc.
    Inventors: Kenneth M. Ford, Niranjan Suri
  • Patent number: 9569282
    Abstract: Fine-grained parallelism within isolated object graphs is used to provide safe concurrent operations within the isolated object graphs. One example provides an abstraction labeled IsolatedObjectGraph that encapsulates at least one object graph, but often two or more object graphs, rooted by an instance of a type member. By encapsulating the object graph, no references from outside of the object graph are allowed to objects inside of the object graph. Also, the encapsulated object graph does not contain references to objects outside of the graphs. The isolated object graphs provide for safe data parallel operations, including safe data parallel mutations such as for each loops. In an example, the ability to isolate the object graph is provided through type permissions.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: February 14, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: John J. Duffy, Niklas Gustafsson, Vance Morrison
  • Patent number: 9558147
    Abstract: A system and method for monitoring a plurality of data streams is disclosed. At a first processing stage, a first memory area is associated to an element of a plurality of data streams. Upon arrival of a frame associated with one of the plurality of data streams, a second memory area is associated to the arrived frame based on the element. In the second memory area, a data indicating an arrival of the arrived frame is recorded and on a successful recording, the frame is forwarded to a second processing stage. An independent process executes at a preselected time interval to erase contents of the first memory area.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: January 31, 2017
    Assignee: NXP B.V.
    Inventors: Nicola Concer, Sujan Pandey, Hubertus Gerardus Hendrikus Vermeulen
  • Patent number: 9501418
    Abstract: The present disclosure relates to caches, methods, and systems for using an invalidation data area. The cache can include a journal configured for tracking data blocks, and an invalidation data area configured for tracking invalidated data blocks associated with the data blocks tracked in the journal. The invalidation data area can be on a separate cache region from the journal. A method for invalidating a cache block can include determining a journal block tracking a memory address associated with a received write operation. The method can also include determining a mapped journal block based on the journal block and on an invalidation record. The method can also include determining whether write operations are outstanding. If so, the method can include aggregating the outstanding write operations and performing a single write operation based on the aggregated write operations.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: November 22, 2016
    Assignee: HGST Netherlands B.V.
    Inventor: Pulkit Misra