Coherency Patents (Class 711/141)
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Patent number: 12158845Abstract: Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.Type: GrantFiled: April 15, 2022Date of Patent: December 3, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Ganesh Balakrishnan
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Patent number: 12153952Abstract: A method for processing multiple transactions converted from a single transaction is provided, which is performed by a processor including at least one core and includes converting a first transaction conforming to an instruction according to an instruction set architecture (ISA) into a plurality of second transactions conforming to the register size of the core, and transferring, by the load-store unit (LSU) of the core, the plurality of second transactions to the cache, in which the LSU may be configured to further transfer, to the cache, conversion information indicating whether the plurality of second transactions are converted from the first transaction.Type: GrantFiled: April 22, 2024Date of Patent: November 26, 2024Assignee: MetisX CO., Ltd.Inventors: Kwang Sun Lee, Do Hun Kim, Kee Bum Shin
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Patent number: 12118230Abstract: Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums that allows an application of a computer system to create a series of one or more logs of writes to one or more memory locations of a memory device. The logs may comprise the values at the end of the log interval of the one or more memory locations that were written to during a log interval. In some examples, the logs do not include intermediate writes to the one or more memory locations (only the final value) and do not include values of memory locations that were not written to during the interval. After an event, software can apply these logs to a copy of the original memory region state to recover the contents of the locations at any of the logged points. These logs may be useful to recreate the state of the memory at various points during the application's execution.Type: GrantFiled: February 9, 2023Date of Patent: October 15, 2024Assignee: Micron Technology, Inc.Inventors: Bryan Hornung, Tony M. Brewer
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Patent number: 12106123Abstract: Plugins that are independently written are executed in a collaborative manner to analysis a log. A plugin executing with respect to a particular node of a hierarchical data structure determines values for a set of keys based on information of the particular node and/or any ancestor nodes, and information stored in a shared repository. The plugin stores the values for the keys as additional information of the particular hierarchical node and/or into the shared repository. The plugin does not access information of non-ancestor nodes when executing with respect to the particular hierarchical node. Each plugin writes into and retrieves from the shared repository using the shared naming convention, thereby sharing information. The sequence of execution of the plugins is not dependent on dependencies amongst the plugins. If a dependent plugin requiring an output from a requisite plugin is first executed, the dependent plugin is flagged as pending and subsequently re-executed.Type: GrantFiled: October 26, 2023Date of Patent: October 1, 2024Assignee: Oracle International CorporationInventors: Nagarajan Muthukrishnan, Ravi Shankar Thammaiah, Sumanta Kumar Chatterjee, Binoy Sukumaran
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Patent number: 12072804Abstract: A coherence protocol applied to memory pages maintains coherence between memory spaces on a plurality of nodes so that the threads of the runtime are operable on any of the nodes. The nodes operating according to the coherence protocol track a state and an epoch number for each memory page residing therein. The states include a modified state in which only one particular node has an up-to-date copy of the memory page, an exclusive state in which only one particular node owns the memory page, a shared state in which all nodes that have the memory page in the shared state have the same copy, and a lost state in which the memory page cannot be either read or written. The epoch number is a number that is incremented each time the page enters the modified state and is used to determine whether the page contains data that is stale.Type: GrantFiled: December 16, 2022Date of Patent: August 27, 2024Assignee: VMware LLCInventors: Aidan Cully, Duan Veljko, Husheng Zhou, Hyojong Kim
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Patent number: 12061555Abstract: A load/store circuit performs a first lookup of a load virtual address in a virtually-indexed, virtually-tagged first-level data cache (VIVTFLDC) that misses and generates a fill request that causes translation of the load virtual address into a load physical address, receives a response that indicates the load physical address is in a non-cacheable memory region and is without data from the load physical address, allocates a VIVTFLDC data-less entry that includes an indication that the data-less entry is associated with a non-cacheable memory region, performs a second lookup of the load virtual address in the VIVTFLDC and determines the load virtual address hits on the data-less entry, determines from the hit data-less entry it is associated with a non-cacheable memory region, and generates a read request to read data from a processor bus at the load physical address rather than providing data from the hit data-less entry.Type: GrantFiled: May 19, 2023Date of Patent: August 13, 2024Assignee: Ventana Micro Systems Inc.Inventors: John G. Favor, Srivatsan Srinivasan
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Patent number: 12056399Abstract: According to one embodiment, a controller of a memory system reorders a plurality of first write commands in an order in which writing within a first zone is executed sequentially from a next write location within the first zone. The controller transfers a plurality of write data associated with the plurality of first write commands reordered from a write buffer of a host to an internal buffer in a same order as the order of the plurality of first write commands reordered, and writes the plurality of write data transferred to the internal buffer to a first storage region managed as the first zone.Type: GrantFiled: May 31, 2023Date of Patent: August 6, 2024Assignee: KIOXIA CORPORATIONInventors: Shinichi Kanno, Koichi Nagai
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Patent number: 12056053Abstract: A method for establishing a connection between two nodes in a communication network without use of a centralized directory or mapping identifiers includes: receiving a lookup message from another node in the communication network that includes a lookup term; determining if a target node in a local directory cache can be identified that satisfies the lookup term; and, if such a node is identified, establishing a connection to the target node and forwarding the lookup message, or, if no such node is identified, forwarding the lookup message to other nodes in the network with which the node has an active communication connection.Type: GrantFiled: April 17, 2023Date of Patent: August 6, 2024Assignee: MASTERCARD INTERNATIONAL INCORPORATEDInventor: Stephen Higgins
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Patent number: 11989143Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.Type: GrantFiled: June 28, 2022Date of Patent: May 21, 2024Assignee: Avago Technologies International Sales Pte. LimitedInventors: Shreyas Shah, George Apostol, Jr., Nagarajan Subramaniyan, Jack Regula, Jeffrey S. Earl
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Patent number: 11977863Abstract: A system may determine one or more data sources which the system is configured to access. The system may provide a set of application programming interfaces (APIs) for interacting with data stored in one or more data sources. The APIs may be accessible to one or more web applications which the system is configured to serve. The system may determine that a web application has requested an operation for interacting with the data through one or more APIs in the set of APIs. The system may determine one or more responses based at least in part on the operation requested by the web application. The system may provide the response(s) to the web application.Type: GrantFiled: July 12, 2022Date of Patent: May 7, 2024Assignee: Palantir Technologies Inc.Inventors: Alexander Ryan, Allen Chang, William Bindi, Brian Lee, John Carrino, Julie Tibshirani, Timothy Wilson
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Patent number: 11954119Abstract: In an approach for dynamically selecting the application algorithm to be used for each change in a target database system, a processor provides at least two application algorithms for applying changes to a table in a target database system. A processor determines, for each application algorithm of the at least two application algorithms, a performance behavior of each application algorithm for sizes of changes that are applied to the table by the respective application algorithm. A processor receives a data change request for applying a change to the table. A processor determines a size of the change to the table. A processor selects one of the at least two application algorithms that provides a best performance for the size based on the performance behavior of each application algorithm. A processor applies the change to the table using the selected application algorithm that provides the best performance for the size.Type: GrantFiled: January 14, 2021Date of Patent: April 9, 2024Assignee: International Business Machines CorporationInventors: Knut Stolze, Felix Beier, Reinhold Geiselhart, Luis Eduardo Oliveira Lizardo
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Patent number: 11928024Abstract: A system and method corrects single bit errors in a memory by detecting a single bit error with a memory. The memory is accessed via data cache stages of a pipeline. Further, based on detecting the single bit error, the data cache stages of the pipeline are stopped from accepting new transactions. A value associated with each address of the memory is read based on stopping the new transactions from being accepted, and the detected single bit errors within the values are corrected.Type: GrantFiled: August 26, 2022Date of Patent: March 12, 2024Assignee: Synopsys, Inc.Inventor: Karthik Thucanakkenpalayam Sundararajan
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Patent number: 11907103Abstract: An appropriate test environment is selected while preventing test cases from being detained therein. A test environment determination device includes: an element selection unit that selects one or more test targets and one or more test environments for executing a test case based on target requirements described for specifications of an electronic control unit, which is a test target, and environment requirements described for specifications of a test environment for simulating an external environment of the test target; an environment operation information acquisition unit that acquires operation information on the test environments; and an environment selection unit that selects a combination of the selected test target and the selected test environment based on the acquired operation information.Type: GrantFiled: December 12, 2019Date of Patent: February 20, 2024Assignee: HITACHI ASTEMO, LTD.Inventors: Masashi Mizoguchi, Takahiro Iida, Toru Irie, Yoshimi Yamazaki
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Patent number: 11870846Abstract: Systems and methods of the disclosure include: publishing, by a first host computer system of a computing cluster comprising a plurality of host computer systems running a plurality of virtual machines, a list of memory page identifiers, wherein each memory page identifier is associated with a corresponding content identifier; receiving, from a second host computer system of the computing cluster, a memory page request comprising a first memory page identifier; and sending, to the first host computer system, a first memory page identified by the first memory page identifier.Type: GrantFiled: February 25, 2021Date of Patent: January 9, 2024Assignee: Red Hat, Inc.Inventors: Michael Tsirkin, David Alan Gilbert
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Patent number: 11822922Abstract: A processor may initialize a fetch of a first instruction. The processor may determine whether there is an icache miss for the first instruction. The processor may fetch the next instruction from a cache.Type: GrantFiled: December 31, 2021Date of Patent: November 21, 2023Assignee: International Business Machines CorporationInventors: Mohit Karve, Naga P. Gorti
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Patent number: 11816036Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.Type: GrantFiled: May 6, 2022Date of Patent: November 14, 2023Assignee: Intel CorporationInventors: Anil Vasudevan, Venkata Krishnan, Andrew J. Herdrich, Ren Wang, Robert G. Blankenship, Vedaraman Geetha, Shrikant M. Shah, Marshall A. Millier, Raanan Sade, Binh Q. Pham, Olivier Serres, Chyi-Chang Miao, Christopher B. Wilkerson
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Patent number: 11768743Abstract: A system and method include migrating, by a migration controller, a first entity of a first subset of entities from a source site to a target site in a virtual computing system based on an asynchronous mode of replication. The system and method also include replicating, by the migration controller, data of a second entity of a second subset of entities from the source site to the target site based on a synchronous mode of replication in parallel with the migration of the first entity for dynamically adjusting a recovery time objective parameter.Type: GrantFiled: July 29, 2020Date of Patent: September 26, 2023Assignee: Nutanix, Inc.Inventors: Kiran Tatiparthi, Ankush Jindal, Monil Devang Shah, Mukul Sharma, Shubham Gupta, Sharad Maheshwari, Kilol Surjan
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Patent number: 11726915Abstract: A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.Type: GrantFiled: March 17, 2020Date of Patent: August 15, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Yasuko Eckert, Maurice B. Steinman, Steven Raasch
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Patent number: 11675705Abstract: An indication to perform an eviction operation on a cache line in a cache can be received. A determination can be made as to whether at least one sector of the cache line is associated with invalid data. In response to determining that at least one sector of the cache line is associated with invalid data, a read operation can be performed to retrieve valid data associated with the at least one sector. The at least one sector of the cache line that is associated with the invalid data can be modified based on the valid data. Furthermore, the eviction operation can be performed on the cache line with the modified at least one sector.Type: GrantFiled: March 11, 2021Date of Patent: June 13, 2023Assignee: Micron Technology, Inc.Inventors: Dhawal Bavishi, Robert M. Walker
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Patent number: 11669452Abstract: A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.Type: GrantFiled: November 11, 2020Date of Patent: June 6, 2023Assignee: Nokia Solutions and Networks OyInventors: Andrea Enrici, Julien Lallet
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Patent number: 11656801Abstract: Methods, systems, and devices related to data relocation via a cache are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In some cases, the memory device may transfer data from a first address of the memory array to the signal development cache. The memory device may transfer the data stored in the signal development cache to a second address of the memory array based on a parameter associated with the first address of the memory array satisfying a criterion for performing data relocation.Type: GrantFiled: May 4, 2022Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventors: Shanky Kumar Jain, Dmitri A. Yudanov
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Patent number: 11645265Abstract: Techniques are described handling database transaction in a manner that is efficient and flexible. In some embodiments, a system receives, through a page of a user interface, a first request to change at least a first data object. The system generates, based on the first request, a first atomic transaction to modify the first data object in a database. Before the first atomic database transaction has committed to the database, the system receives, through the page of the user interface, a second request to change at least a second data object. The system generates, based on the second request, a second atomic transaction to modify the second object in the database. The system may execute the second atomic transaction independently of the first atomic transaction.Type: GrantFiled: November 4, 2019Date of Patent: May 9, 2023Assignee: Oracle International CorporationInventors: Madeleine Dawn Holmes, Surendra Nath V. N. R. K Nukala, Anveshan Reddy Kunduru, Chaitanyasri Molakalapalli
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Patent number: 11625179Abstract: A cache storage system indexing method is provided that indexes a data address in a cache storage system based on a data fingerprint of the cached data, wherein the data fingerprint is generated by a deduplication fingerprint function used for referencing deduplication of data in the cache storage system. A computer-implemented method of data operations to a cache storage system is also provided including: obtaining a data fingerprint for the data of the data operation, either by applying a deduplication fingerprinting function to data of a write operation or by accessing deduplication metadata for a read operation to obtain the data fingerprint generated by using a deduplication fingerprinting function used for deduplication of data in the cache storage system; and using an indexing service to the cache storage system having an address schema based on the data fingerprints of the data.Type: GrantFiled: February 22, 2021Date of Patent: April 11, 2023Assignee: International Business Machines CorporationInventors: Lee Jason Sanders, Ben Sasson, Gordon Douglas Hutchison
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Patent number: 11609859Abstract: Embodiments of the invention include a machine-readable medium having stored thereon at least one instruction, which if performed by a machine causes the machine to perform a method that includes decoding, with a node, an invalidate instruction; and executing, with the node, the invalidate instruction for invalidating a memory range specified across a fabric interconnect.Type: GrantFiled: November 17, 2020Date of Patent: March 21, 2023Assignee: Intel CorporationInventors: Karthik Kumar, Thomas Willhalm, Francesc Guim Bernat, Brian J. Slechta
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Patent number: 11593275Abstract: Operating system deactivation of write protection for a storage block is provided absent quiescing of processors in a multi-processor computing environment. The process includes receiving an address translation protection exception interrupt resulting from an attempted write access by a processor to a storage block, and determining by the operating system whether write protection for the storage block is active. Based on write protection for the storage block not being active, the operating system issues an instruction to clear or modify translation lookaside buffer entries of the processor associated with the storage block, absent waiting for an action by another processor of multiple processors of the computing environment, to facilitate write access to the storage block proceeding at the processor.Type: GrantFiled: June 1, 2021Date of Patent: February 28, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christine Michele Yost, Elpida Tzortzatos, Bruce Conrad Giamei, Timothy Slegel, Christian Borntraeger, Damian Osisek, Lisa Cranton Heller, Ute Gaertner
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Patent number: 11586541Abstract: One embodiment can provide a node controller in a multiprocessor system. The node controller can include a processor interface to interface with a processor, a memory interface to interface with a fabric-attached memory, a node-controller interface to interface with a remote node controller, and a cache-coherence logic to operate in a first mode or a second mode. The cache-coherence logic manages cache coherence for a local memory of the processor coupled to the processor interface when operating in the first mode, and the cache-coherence logic manages cache coherence for the fabric-attached memory coupled to the memory interface when operating in the second mode.Type: GrantFiled: July 31, 2020Date of Patent: February 21, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Derek Schumacher, Randy Passint, Thomas McGee, Michael Malewicki, Michael S. Woodacre
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Patent number: 11580035Abstract: A processor includes a register to store an encoded pointer to a variable in stack memory. The encoded pointer includes an encrypted portion and a fixed plaintext portion of a memory address corresponding to the variable. The processor further includes circuitry to, in response to a memory access request for associated with the variable, decrypt the encrypted portion of the encoded pointer to obtain first upper address bits of the memory address and a memory allocation size for a variable, decode the encoded pointer to obtain the memory address, verify the memory address is valid based, at least in part on the memory allocation size, and in response to determining that the memory address is valid, allow the memory access request.Type: GrantFiled: December 26, 2020Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: David M. Durham, Karanvir S. Grewal, Michael D. LeMay, Salmin Sultana, Andrew James Weiler
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Patent number: 11544181Abstract: A storage device includes a controller and nonvolatile memories. The controller receives write commands having virtual stream identifiers (IDs), receives discard commands having the virtual stream IDs, and determines a lifetime of write data to which each of the virtual stream IDs is assigned. The nonvolatile memories are accessed by the controller depending on physical stream IDs. The controller maps the virtual stream IDs and the physical stream IDs based on the lifetime of the write data.Type: GrantFiled: January 9, 2019Date of Patent: January 3, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Hwanjin Yong, Jin-Soo Kim
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Patent number: 11537427Abstract: A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.Type: GrantFiled: January 12, 2021Date of Patent: December 27, 2022Assignee: Imagination Technologies LimitedInventors: Mark Landers, Martin John Robinson
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Patent number: 11520733Abstract: Provided are systems and methods for linking source data fields to target inputs having a different data structure. In one example, the method may include receiving a request to load a data file from a source data structure to a target data structure, identifying a plurality of target inputs of the target data structure, wherein the plurality of target inputs include a format of the target data structure, and at least one of the target inputs has a format that is different from a format of a source data structure, dynamically linking the plurality of source data fields to the plurality of target inputs based on metadata of the plurality of source data fields, and loading the data file from the source data structure to the target data structure.Type: GrantFiled: March 2, 2021Date of Patent: December 6, 2022Assignee: SAP SEInventor: Bertram Beyer
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Patent number: 11513805Abstract: A computer architecture employs multiple special-purpose processors having different affinities for program execution to execute substantial portions of general-purpose programs to provide improved performance with respect to a general-purpose processor executing the general-purpose program alone.Type: GrantFiled: August 19, 2016Date of Patent: November 29, 2022Assignee: Wisconsin Alumni Research FoundationInventors: Karthikeyan Sankaralingam, Anthony Nowatzki
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Patent number: 11494224Abstract: An apparatus includes a CPU core, a first cache subsystem coupled to the CPU core, and a second memory coupled to the cache subsystem. The first cache subsystem includes a configuration register, a first memory, and a controller. The controller is configured to: receive a request directed to an address in the second memory and, in response to the configuration register having a first value, operate in a non-caching mode. In the non-caching mode, the controller is configured to provide the request to the second memory without caching data returned by the request in the first memory. In response to the configuration register having a second value, the controller is configured to operate in a caching mode. In the caching mode the controller is configured to provide the request to the second memory and cache data returned by the request in the first memory.Type: GrantFiled: May 22, 2020Date of Patent: November 8, 2022Assignee: Texas Instruments IncorporatedInventors: Abhijeet Ashok Chachad, Timothy David Anderson, David Matthew Thompson
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Patent number: 11487672Abstract: Aspects of the invention include computer-implemented methods, systems, and computer program products that access a multi-copy scope directory state of a cache memory that indicates a scope of sharing of a cache line in a cache memory system and determine a scope of sharing of the cache line in the cache memory system based on the multi-copy scope directory state, where the multi-copy scope directory state enumerates a plurality of scopes within the cache memory system. The scope of sharing is used to reduce a number of queries to one or more cache memories having a larger scope than a shared scope identified in the scope of sharing. The multi-copy scope directory state of the cache memory is updated based on detecting a change in shared scope of the cache line within the cache memory system.Type: GrantFiled: August 20, 2021Date of Patent: November 1, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chunggeon Rhee, Craig R. Walters, Ram Sai Manoj Bamdhamravuri, Timothy Bronson, Gregory William Alexander
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Patent number: 11467834Abstract: A system for computing. In some embodiments, the system includes: a memory, the memory including one or more function-in-memory circuits; and a cache coherent protocol interface circuit having a first interface and a second interface. A function-in-memory circuit of the one or more function-in-memory circuits may be configured to perform an operation on operands including a first operand retrieved from the memory, to form a result. The first interface of the cache coherent protocol interface circuit may be connected to the memory, and the second interface of the cache coherent protocol interface circuit may be configured as a cache coherent protocol interface on a bus interface.Type: GrantFiled: June 26, 2020Date of Patent: October 11, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Krishna T. Malladi, Andrew Chang
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Patent number: 11455107Abstract: A method is implemented for a memory sub-system that detects a sequential write pattern in a write sequence for a memory device in a set of commands received from a host, detects current bandwidth utilization deviating from a write bandwidth utilization performance target, in response to detecting the sequential write pattern, and adjusts write bandwidth utilization to conform to the write bandwidth utilization target, in response to detecting the current bandwidth utilization deviating from the write bandwidth utilization performance target.Type: GrantFiled: October 28, 2019Date of Patent: September 27, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Suresh Rajgopal, Ling Wang, Yue Wei, Vamsi Pavan Rayaprolu
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Patent number: 11449269Abstract: Apparatuses and methods can be related to implementing edge compute components in a memory array. Compute components can be implemented under a memory array. Implementing compute components under a memory array can limit control access to the compute components due to die space utilized by the compute components. A portion of the compute components (e.g., compute components on the edge) may have control access that is not available to the remainder of the compute components.Type: GrantFiled: July 22, 2020Date of Patent: September 20, 2022Assignee: Micron Technology, Inc.Inventors: Glen E. Hush, Richard C. Murphy, Honglin Sun
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Patent number: 11409286Abstract: Systems, methods, computer program products, and apparatuses for low latency, fully reconfigurable hardware logic for ensemble classification methods, such as random forests. An apparatus may comprise circuitry for an interconnect and circuitry for a random forest implemented in hardware. The random forest comprising a plurality of decision trees connected via the interconnect, each decision tree comprising a plurality of nodes connected via the interconnect. A first decision tree of the plurality of decision trees comprising a first node of the plurality of nodes to: receive a plurality of elements of feature data via the interconnect, select a first element of feature data, of the plurality of elements of feature data, based on a configuration of the first node, and generate an output based on the first element of feature data, an operation, and a reference value, the operation and reference value specified in the configuration of the first node.Type: GrantFiled: December 18, 2019Date of Patent: August 9, 2022Assignee: INTEL CORPORATIONInventors: Marcio Juliato, Christopher Gutierrez, Shabbir Ahmed, Manoj Sastry, Liuyang Yang, Xiruo Liu
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Patent number: 11403144Abstract: A method of providing a service to a requesting Infrastructure Element belonging to plurality of Infrastructure Elements interconnected as a data network is proposed. The method includes operating a computing system for receiving a service request requesting a service from the requesting Infrastructure Element. The service request includes an indication of one or more performance requirements. The method also includes converting the service request to a service graph, which includes at least one task to be accomplished by complying with the performance requirements to provide the service. At least one Infrastructure Element currently capable of accomplishing the task complying with the performance requirements is selected, and the selected Infrastructure Element for accomplishing the task is configured. The method further includes causing the selected Infrastructure Element to accomplish the task to provide the service to the requesting Infrastructure Element.Type: GrantFiled: July 9, 2015Date of Patent: August 2, 2022Assignee: TELECOM ITALIA S.p.A.Inventors: Luigi Artusio, Antonio Manzalini
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Patent number: 11386115Abstract: A transactional data storage engine may implement selectable storage endpoints. A selection of storage endpoints may be received at a transactional data storage engine. The selected storage endpoints may identify storage locations maintaining replicas of data for the transactional data storage engine. A storage engine configuration for the transactional data storage engine may be updated to include the storage endpoints so that access requests for the data may be sent to storage endpoints identified according to the storage engine configuration. In some embodiments, storage endpoints may identify strongly consistent or eventually consistent storage locations for performing reads of the data maintained for the transactional data storage engine.Type: GrantFiled: September 12, 2014Date of Patent: July 12, 2022Assignee: Amazon Technologies, Inc.Inventors: Srinivasan Sundar Raghavan, Swaminathan Sivasubramanian
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Patent number: 11366762Abstract: The present disclosure includes apparatuses and methods related to a memory system including a filter. An example apparatus can include a filter to store a number flags, wherein each of the number of flags corresponds to a cache entry and each of the number of flags identifies a portion of the memory device where data of a corresponding cache entry is stored in the memory device.Type: GrantFiled: August 16, 2019Date of Patent: June 21, 2022Assignee: Micron Technology, Inc.Inventor: Robert M. Walker
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Maintaining domain coherence states including domain state no-owned (DSN) in processor-based devices
Patent number: 11354239Abstract: Maintaining domain coherence states including Domain State No-Owned (DSN) in processor-based devices is disclosed. In this regard, a processor-based device provides multiple processing elements (PEs) organized into multiple domains, each containing one or more PEs and a local ordering point circuit (LOP). The processor-based device supports domain coherence states for coherence granules cached by the PEs within a given domain. The domain coherence states include a DSN domain coherence state, which indicates that a coherence granule is not cached within a shared modified state within any domain. In some embodiments, upon receiving a request for a read access to a coherence granule, a system ordering point circuit (SOP) determines that the coherence granule is cached in the DSN domain coherence state within a domain of the plurality of domains, and can safely read the coherence granule from the system memory to satisfy the read access if necessary.Type: GrantFiled: September 18, 2020Date of Patent: June 7, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Eric Francis Robinson, Kevin Neal Magill, Jason Panavich, Derek Bachand, Michael B. Mitchell, Michael P. Wilson -
Patent number: 11321495Abstract: Embodiments for mitigating security vulnerabilities in a heterogeneous computing system are provided. Anomalous cache coherence behavior may be dynamically detected between a host and one or more accelerators using a cache controller at a shared last level cache based upon a pair-based coherence messages functioning as a proxy for indicating one or more security attack protocols.Type: GrantFiled: April 1, 2020Date of Patent: May 3, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alper Buyuktosunoglu, Hyojin Sung
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Patent number: 11314644Abstract: A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.Type: GrantFiled: May 22, 2020Date of Patent: April 26, 2022Assignee: Texas Instruments IncorporatedInventors: Abhijeet Ashok Chachad, Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan
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Patent number: 11294710Abstract: A processing system suspends execution of a program thread based on an access latency required for a program thread to access memory. The processing system employs different memory modules having different memory technologies, located at different points in the processing system, and the like, or a combination thereof. The different memory modules therefore have different access latencies for memory transactions (e.g., memory reads and writes). When a program thread issues a memory transaction that results in an access to a memory module having a relatively long access latency (referred to as “slow” memory), the processor suspends execution of the program thread and releases processor resources used by the program thread. When the processor receives a response to the memory transaction from the memory module, the processor resumes execution of the suspended program thread.Type: GrantFiled: November 10, 2017Date of Patent: April 5, 2022Assignee: Advanced Micro Devices, Inc.Inventor: Douglas Benson Hunt
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Patent number: 11294445Abstract: An information processing apparatus includes a memory, a control unit to accept an access to the memory, a power supply circuit to supply a voltage to the memory and the control unit, a detection circuit to detect a drop in the voltage, a discharge circuit, and a delay circuit. The discharge circuit discharges a charge on a voltage supply line extending between the power supply circuit and the memory. The delay circuit delays receipt of a control signal by the discharge circuit for a predetermined period after the discharge circuit receives a charge discharge instruction from the control unit. The control signal is to control discharging the supply line charge. The discharge circuit discharges supply line charges per a control signal based on detection of a drop in the voltage by the detection circuit and based on the delay of the control signal delayed by the delay circuit.Type: GrantFiled: December 11, 2019Date of Patent: April 5, 2022Assignee: CANON KABUSHIKI KAISHAInventor: Kohei Asano
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Patent number: 11294809Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.Type: GrantFiled: August 28, 2018Date of Patent: April 5, 2022Assignee: Intel CorporationInventors: Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther, Buford M. Guy, Thomas R. Huff, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Ronak Singhal, Seyed Yahya Sotoudeh, Bret L. Toll, Lihu Rappoport, David Papworth, James D. Allen
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Patent number: 11288195Abstract: A data processing system comprises a requesting node; a home node to control coherency amongst data stored by the data processing system; and one or more further nodes, at least one of the further nodes having a memory; the requesting node being configured to issue a data handling transaction to the home node, the data handling transaction defining a data handling operation relating to a range of memory addresses, the requesting node being configured to maintain an address hazard at the requesting node inhibiting issue of another data handling transaction for that range of memory addresses until the requesting node is notified by the home node that the data handling transaction has completed; the home node being configured, in response to the data handling transaction, to issue one or more data handling instructions to cause one or more given nodes of the one or more further nodes to perform the data handling operation, the home node being configured to notify completion to the requesting node in response toType: GrantFiled: March 22, 2019Date of Patent: March 29, 2022Assignee: Arm LimitedInventor: Andrew David Tune
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Patent number: 11281618Abstract: A system is disclosed that includes a first communication circuit that communicates data over a first data port using a first communication protocol. The system also includes a second communication circuit that communicates data over a second data port using a second communication protocol. The second communication protocol processes read and write requests in an order that the read and write requests are received. A bridge circuit is configured to communicate data between the first data port of the first communication circuit and the second data port of the second communication circuit. The bridge circuit is configured to communicate non-posted writes to the second communication circuit via a buffer circuit and communicate posted writes to the second communication circuit via a communication path that bypasses the buffer circuit.Type: GrantFiled: October 31, 2014Date of Patent: March 22, 2022Assignee: XLNX, INC.Inventors: Sagheer Ahmad, Tomai Knopp
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Patent number: 11283682Abstract: Disclosed are systems, methods, and computer-readable media for assuring tenant forwarding in a network environment. Network assurance can be determined in layer 1, layer 2 and layer 3 of the networked environment including, internal-internal (e.g., inter-fabric) forwarding and internal-external (e.g., outside the fabric) forwarding in the networked environment. The network assurance can be performed using logical configurations, software configurations and/or hardware configurations.Type: GrantFiled: September 25, 2020Date of Patent: March 22, 2022Assignee: CISCO TECHNOLOGY, INC.Inventors: Sanchay Harneja, Sanjay Sundaresan
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Patent number: 11275574Abstract: The last successful device update can be recovered on a computing system. An update tool can be employed to detect whether an update package is installed successfully. When an update package is successfully installed, the update tool can define a last successful device update that associates the update package with the device that the update package targets. In contrast, when the update package does not install successfully, the update tool can access the last successful device update for the targeted device and use it to obtain and install the previous update package that the last successful device update represents. In this way, the related components for a device can be rolled back to a common state to prevent incompatibilities that may otherwise exist due to the failed installation.Type: GrantFiled: February 3, 2020Date of Patent: March 15, 2022Assignee: Dell Products L.P.Inventors: Vivekanandh Narayanasamy Rajagopalan, Trinto Thattil Nadakkalan Antony, Ambadas Devrao Jadhav