Coherency Patents (Class 711/141)
  • Patent number: 9996398
    Abstract: An application processor includes a first core and a second core. The first core is configured to implement a scheduler which monitors a workload of a task of the first core, and the first core is further configured to implement an idle checker which determines whether the second core is idle.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: June 12, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gyeong Taek Lee, Seung Kyu Kim, Kyung Min Park, Jong Lae Park, Ji Eun Park
  • Patent number: 9998378
    Abstract: A traffic control method and device are provided. The method includes receiving traffic monitoring information of a first service flow reported by a reaction point RP; when a congestion state of a first service flow of a congestion point CP satisfies a congestion condition, determining a reaction point RP needing traffic adjustment from a designated reaction point RP according to the received traffic monitoring information, and calculating, according to the traffic monitoring information, a new traffic value of a first service flow of each of the reaction point RP needing traffic adjustment; sending each calculated new traffic value of a first service flows to a corresponding reaction point RP needing traffic adjustment, so that the reaction point RP performs traffic control on the first service flow of the reaction point RP according to the new traffic value.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: June 12, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xing Hu, Xiaojun Shen, Zhiyun Chen
  • Patent number: 9990287
    Abstract: An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Shlomo Raikin, Raanan Sade, Robert Valentine, Julius Yuli Mandelblat, Ron Shalev, Larisa Novakovsky
  • Patent number: 9992299
    Abstract: Technologies for identifying a cache line of a network packet for eviction from an on-processor cache of a network device communicatively coupled to a network controller. The network device is configured to determine whether a cache line of the cache corresponding to the network packet is to be evicted from the cache based on a determination that the network packet is not needed subsequent to processing the network packet, and provide an indication that the cache line is to be evicted from the cache based on an eviction policy received from the network controller.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Ren Wang, Sameh Gobriel, Christian Maciocco, Tsung-Yuan C. Tai, Ben-Zion Friedman, Hang T. Nguyen, Namakkal N. Venkatesan, Michael A. O'Hanlon, Shrikant M. Shah, Sanjeev Jain
  • Patent number: 9983820
    Abstract: In an embodiment, a method for re-programming memory is disclosed. In the embodiment, the method involves selecting a memory page based on version information and re-programming the selected memory page using cyclic redundancy check (CRC) data for the memory page.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: May 29, 2018
    Assignee: NXP B.V.
    Inventors: Sönke Ostertun, Wolfgang Stidl, Raffaele Costa
  • Patent number: 9965889
    Abstract: A ray tracing core includes a ray generation unit and a plurality of T&I (Traversal & Intersection) units with MIMD (Multiple Instruction stream Multiple Data stream) architecture. The ray generation unit generates at least one eye ray based on an eye ray generation information. The eye ray generation information includes a screen coordinate value. Each of the plurality of T&I units receives the at least one eye ray and checks whether there exists a triangle intersected with the received at least one eye ray. The triangle configures a space.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: May 8, 2018
    Assignees: SILICONARTS, INC., INDUSTRY-ACADEMIA COOPERATION FOUNDATION OF SEJONG UNIVERSITY
    Inventors: Jin Suk Hur, Woo Chan Park
  • Patent number: 9965220
    Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: May 8, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Olivier Alavoine, Sejoong Lee, Tauseef Kazi, Simon Booth, Edoardo Regini, Renatas Jakushokas, Saurabh Patodia, Jeffrey Gemar, Haw-Jing Lo, Vinod Chamarty, Boris Andreev, Tao Shen, Aravind Bhaskara, Wenbiao Wang, Stephen Molloy
  • Patent number: 9940071
    Abstract: A memory system includes a non-volatile memory and a controller circuit. The controller circuit is configured to carry out an atomic write operation in the non-volatile memory in response to an atomic write command, and selectively carry out one of a first operation and a second operation corresponding to address mapping between a logical address and a physical address of the non-volatile memory, along with the atomic write operation. When the first operation is selected, the controller circuit starts to update the address mapping after receiving a notification that writing of all data of the atomic write operation has been completed. When the second operation is carried out, the controller circuit starts to update the address mapping before receiving the notification.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: April 10, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyuki Nemoto, Shunitsu Kohara, Kazuya Kitsunai, Satoshi Arai
  • Patent number: 9940236
    Abstract: A first pointer dereferencer receives a location of a portion of a first node of a data structure. The first node is to be stored in a first storage element. A first pointer is obtained from the first node of the data structure. A location of a portion of a second node of the data structure is determined based on the first pointer. The second node is to be stored in a second storage element. The location of the portion of the second node of the data structure is sent to a second pointer dereferencer that is to access the portion of the second node from the second storage element.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Mark A. Anders, Himanshu Kaul, Gregory K. Chen
  • Patent number: 9928119
    Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests of a plurality of concurrently executing hardware threads are received in a shared queue. The storage-modifying requests include a translation invalidation request of an initiating hardware thread. The translation invalidation request is removed from the shared queue and buffered in sidecar logic in one of a plurality of sidecars each associated with a respective one of the plurality of hardware threads. While the translation invalidation request is buffered in the sidecar, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Hugh Shen, Derek E. Williams
  • Patent number: 9910968
    Abstract: A content management system can detect file events that are suspected to be in error, and notify users having access to files affected by the detected file events of the detected events. The content management system can maintain a log of file events including a plurality of file identifiers. The file identifiers identify files that are associated with a namespace, a file event, and a user account responsible for the file event. An analytics module can analyze the log of file events and notify the user of a suspected error when it may be that the file events were inadvertent. A notification can include a link to restore (undo) the file events if the user confirms that the file events were in error.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: March 6, 2018
    Assignee: Dropbox, Inc.
    Inventors: Matt Eccleston, Stacey Sern, Marcio von Muhlen
  • Patent number: 9898404
    Abstract: An improved garbage collection (“GC”) process configured to recover new blocks from used storage space is disclosed. After initiating the GC process for a flash memory in accordance with at least one of predefined triggering events, a first valid page within a first block marked as an erasable block is identified. Upon determining a first signature representing the content of the first valid page according to a predefined signature generator, the process identifies a second valid page within a second block as a duplicated page of the first valid page in response to the first signature. The process subsequently associates the logical block address (“LBA”) of the first valid page to the second valid page. In an alternative embodiment, page compression and sequential order of page arrangement can also be implemented to further enhance efficiency of garbage collection.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: February 20, 2018
    Assignee: CNEX LABS
    Inventors: Yiren Ronnie Huang, Aaron Huang
  • Patent number: 9898418
    Abstract: A processor including a translation lookaside buffer (TLB), an instruction translator, and a memory subsystem. The TLB caches virtual to physical address translations. The instruction translator incorporates a microinstruction set for the processor that includes a single invalidate page instruction. The invalidate page instruction, when executed by the processor, causes the processor to perform a pseudo translation process in which a virtual address is submitted to the TLB to identify matching entries in the TLB that match the virtual address. The memory subsystem invalidates the matching entries in the TLB. The TLB may include a data TLB and an instruction TLB. The memory subsystem may include a tablewalk engine that performs a pseudo tablewalk to invalidate entries in the TLB and in one or more paging caches. The invalidate page instruction may specify invalidation of only those entries indicated as local.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: February 20, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: Colin Eddy
  • Patent number: 9892072
    Abstract: Interconnect circuitry for connecting transaction masters to transaction slaves includes response modification circuitry. The response modification circuitry includes shortlist buffer circuitry storing identification for modification target transaction responses. The response modification circuitry uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: February 13, 2018
    Assignee: ARM Limited
    Inventors: Andrew David Tune, Arthur Brian Laughton, Daniel Adam Sara, Sean James Salisbury, Peter Andrew Riocreux
  • Patent number: 9891938
    Abstract: The present disclosure is related to methods, systems, and machine-readable media for modifying an instance catalog to perform operation. A storage system can include a plurality of packfiles that store data. The storage system can include a plurality of streams that include a plurality of hashes that identify the plurality of packfiles. The storage system can include an instance catalog that includes an identification of the plurality of streams. The storage system can include an operation engine to perform a number of operations on the plurality of packfiles by modifying the instance catalog using the identification of the plurality of streams.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: February 13, 2018
    Assignee: VMware, Inc.
    Inventors: David W. Barry, Joanne Ren, Mike Zucca, Keith Farkas
  • Patent number: 9887924
    Abstract: Embodiments of the disclosure provide techniques for measuring congestion and controlling quality of service to a shared resource. A module that interfaces with the shared resource monitors the usage of the shared resource by accessing clients. Upon detecting that the rate of usage of the shared resource has exceeded a maximum rate supported by the shared resource, the module determines and transmits a congestion metric to clients that are currently attempting to access the shared resource. Clients, in turn determine a delay period based on the congestion metric prior to attempting another access of the shared resource.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: February 6, 2018
    Assignee: VMware, Inc.
    Inventors: William Earl, Christos Karamanolis
  • Patent number: 9886350
    Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
  • Patent number: 9880939
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a device controller, and a tag memory. The device controller stores a part of a logical-to-physical address translation table (L2P table) stored in the nonvolatile memory in a memory of a host as a cache. The tag memory includes a plurality of entries associated with a plurality of cache lines of the cache. Each entry includes a tag indicating which area of the L2P table is stored in a corresponding cache line, and a plurality of bitmap flags indicating whether a plurality of sub-lines included in the corresponding cache line are valid or not.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: January 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Konosuke Watanabe, Satoshi Kaburaki, Tetsuhiko Azuma
  • Patent number: 9880905
    Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
  • Patent number: 9880937
    Abstract: The present invention provides a dynamic set associative cache apparatus for a processor. When read access occurs, the apparatus first determines a valid/invalid bit of each cache block in a cache set to be accessed, and sets, according to the valid/invalid bit of each cache block, an enable/disable bit of a cache way in which the cache block is located; then, reads valid cache blocks, compares a tag section in a memory address with a tag block in each cache block that is read, and if there is a hit, reads data from a data block in a hit cache block according to an offset section of the memory address.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: January 30, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Lingjun Fan, Shibin Tang, Da Wang, Hao Zhang, Dongrui Fan
  • Patent number: 9858204
    Abstract: A cache device connected to a storage device and connected to a plurality of sources, including a cache unit that relays a read request and a read response between a source and a storage device, and a storage area control unit that stores the source as a first history in association with specification of first data in a read request, and, if the first data are not retained by the cache unit and a storage area sufficient for retaining the first data does not exist, selects data associated with a less number of the sources in the first history as second data in preference to data associated with a greater number of the sources out of the first data or data retained by the cache unit, and, if the second data differ from the first data, causes the cache unit to discard the second data and then store the first data.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: January 2, 2018
    Assignee: NEC Corporation
    Inventor: Youhei Kajimoto
  • Patent number: 9836400
    Abstract: In an embodiment, a first portion of a cache memory is associated with a first core. This first cache memory portion is of a distributed cache memory, and may be dynamically controlled to be one of a private cache memory for the first core and a shared cache memory shared by a plurality of cores (including the first core) according to an addressing mode, which itself is dynamically controllable. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: December 5, 2017
    Assignee: Intel Corporation
    Inventors: Kebing Wang, Zhaojuan Bian, Wei Zhou, Zhihong Wang
  • Patent number: 9836411
    Abstract: A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page table entries). A synchronization instruction is used that ensures after the instruction has completed that updates to the cached entries that occurred prior to the synchronization instruction are made visible in memory. Synchronization may be used to facilitate memory management operations, such as bulk operations used to change a large section of memory to read-only, operations to manage a free list of memory pages, and/or operations associated with terminating processes.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: December 5, 2017
    Assignee: International Business Machines Corporation
    Inventor: Michael K. Gschwind
  • Patent number: 9824009
    Abstract: Systems and methods for coherency maintenance are presented. The systems and methods include utilization of multiple information state tracking approaches or protocols at different memory or storage levels. In one embodiment, a first coherency maintenance approach (e.g., similar to a MESI protocol, etc.) can be implemented at one storage level while a second coherency maintenance approach (e.g., similar to a MOESI protocol, etc.) can be implemented at another storage level. Information at a particular storage level or tier can be tracked by a set of local state indications and a set of essence state indications. The essence state indication can be tracked “externally” from a storage layer or tier directory (e.g., in a directory of another cache level, in a hub between cache levels, etc.). One storage level can control operations based upon the local state indications and another storage level can control operations based in least in part upon an essence state indication.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: November 21, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Anurag Chaudhary, Guillermo Juan Rozas
  • Patent number: 9811463
    Abstract: An apparatus includes interface configured to receive input/output (I/O) traffic from a host computer via a dedicated I/O channel. The I/O traffic includes one or more I/O requests. The apparatus includes a network interface configured to receive network traffic from a second device via a network. The apparatus includes a cache memory configured to store data and a storage device configured to store second data. The apparatus further includes a processor coupled via a communication path to the storage device. The processor is configured to access the cache memory during processing of the I/O traffic or the network traffic. The processor is further configured to perform one or more access operations at the storage device based on the I/O traffic or the network traffic. The communication path is distinct from the I/O channel.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 7, 2017
    Assignee: LS CLOUD STORAGE TECHNOLOGIES, LLC
    Inventor: Ilya Gertner
  • Patent number: 9805048
    Abstract: Implementations described and claimed herein provide systems and methods for allocating and managing resources for a deduplication table. In one implementation, an upper limit to an amount of memory allocated to a deduplication table is established. The deduplication table has one or more checksum entries, and each checksum entry is associates a checksum with unique data. A new checksum entry corresponding to new unique data is prevented from being added to the deduplication table where adding the new checksum entry will cause the deduplication table to exceed a size limit. The new unique data has a checksum that is different from the checksums in the one or more checksum entries in the deduplication table.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: October 31, 2017
    Assignee: Oracle International Corporation
    Inventors: Lisa Week, Mark Maybee
  • Patent number: 9785589
    Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: October 10, 2017
    Assignee: Rambus Inc.
    Inventors: Jared LeVan Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W. Garlepp, Tsyr-Chyang Ho, Benedict Chung-Kwong Lau
  • Patent number: 9779092
    Abstract: A technique for maintaining consistency between a data object and references to the object in a file. An indication that a source object has changed is received. One or more of the changes made to the source object are identified. A file comprising one or more references related to the source object is analyzed to identify those references that may be inconsistent with the changes made to the source object.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: October 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Nigel Daniels, Doina L. Klinger
  • Patent number: 9772950
    Abstract: Technologies are generally described for methods and systems effective to maintain coherence in a multi-core processor on a die. In an example, a method for processing a request for a particular block in a particular region may include analyzing, by a first processor, a first cache to determine whether there is a block indicator in the first cache associated with the particular block. The method may further include when the first processor determines that the block indicator is not present in the first cache, analyzing, by the first processor, the first cache to determine whether there is a region indicator associated with the particular region. The method may further include when the first processor determines that the region indicator is not present in the first cache, the method further includes sending, by the first processor, the request to the directory in the tile.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: September 26, 2017
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 9760498
    Abstract: An electronic system for multiple agents, both coherent and non-coherent, to communicate with a hybrid cache, the hybrid cache to provide functionality associated with a cache for coherent agents in an outer shareable domain, and to provide functionality associated with a cache for non-coherent agents in a system shareable domain, the functionality provided by tag fields in cache lines stored in the hybrid cache. The tag fields are configured to indicate if a cache line of the hybrid cache belongs to at least one of a logical coherent cache or a logical system cache.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: September 12, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Laurent Rene Moll
  • Patent number: 9760430
    Abstract: A solid-state drive (SSD) may not include a dynamic random access memory (DRAM) but rather may utilize a host memory buffer of system random access memory (RAM). During a power failure data on dirty cache lines may be lost. A power protection caching policy may be implemented where an SSD controller is capable of accepting a flush cache signal, which may be a signal to a redefined pin of the SSD or a command, from a controller of the information handling system. The controller may utilize a slope detect mechanism and/or a power good detect mechanism to detect a power failure and if a power failure is detected to issue a flush cache signal the SSD controller to cause a flush of all dirty cache lines from the host memory buffer before the power failure results in inoperability of circuitry associated with the dirty cache lines.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: September 12, 2017
    Assignee: Dell Products L.P.
    Inventors: Munif Mohammed Farhan, Lawrence Edward Knepper
  • Patent number: 9747199
    Abstract: Data storage using application storage analytics that: (i) runs a set of application(s) that use a thin provision data storage device for data storage; (ii) determines a set of runtime behavior(s) of the set of applications(s) with respect to use of the thin provisioning data storage device for data storage; and (iii) calculates a runtime representation capacity based on a predetermined over-provisioning ratio and the set of runtime behavior(s).
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: August 29, 2017
    Assignee: International Business Machines Corporation
    Inventors: Sandeep R. Patil, Riyazahamad M. Shiraguppi, Gandhi Sivakumar, Matthew B. Trevathan
  • Patent number: 9740617
    Abstract: Methods and apparatuses to control cache line coherence are described. A hardware processor may include a first processor core with a cache to store a cache line, a second set of processor cores that each include a cache to store a copy of the cache line, and cache coherence logic to aggregate in a tag directory an acknowledgment message from each of the second set of processor cores in response to a request from the first processor core to modify the copy of the cache line in each of the second set of processor cores and send a consolidated acknowledgment message to the first processor core.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Samantika Sury, Simon Steely, Jr., William Hasenplaugh, Joel Emer, David Webb
  • Patent number: 9740629
    Abstract: According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation table (ERAT) for a computer memory can include receiving a first invalidation request. According to some embodiments, the method may also include determining that a first entry in the ERAT corresponds with the first invalidation request, wherein the ERAT has a plurality of entries, each entry in the plurality of entries having an indicator. In particular embodiments, the method may then determine that a first indicator associated with the first entry indicates that the first entry is not being used by any of a plurality of memory access entities (MAE), wherein a first MAE can concurrently use a same entry as a second MAE. The first entry may then be invalidated in response to determining that the first entry is not being used.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bartholomew Blaner, Jay G. Heaslip, Kenneth A. Lauricella, Jeffrey A. Stuecheli
  • Patent number: 9727464
    Abstract: A computer system comprising multiple nodes, each node comprising a plurality of processors and a local cache hierarchy, suppresses local cache coherency of a node operations or global cache coherency operations between nodes based on the coherency request being a global or local request, and the state of the cache line at the node.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Garrett Michael Drapala, William J Lewis, Pak-kin Mak, Robert J Sonnelitter, III
  • Patent number: 9727483
    Abstract: According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation table (ERAT) for a computer memory can include receiving a first invalidation request. According to some embodiments, the method may also include determining that a first entry in the ERAT corresponds with the first invalidation request, wherein the ERAT has a plurality of entries, each entry in the plurality of entries having an indicator. In particular embodiments, the method may then determine that a first indicator associated with the first entry indicates that the first entry is not being used by any of a plurality of memory access entities (MAE), wherein a first MAE can concurrently use a same entry as a second MAE. The first entry may then be invalidated in response to determining that the first entry is not being used.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bartholomew Blaner, Jay G. Heaslip, Kenneth A. Lauricella, Jeffrey A. Stuecheli
  • Patent number: 9727600
    Abstract: A data consistency management system may include a memory storing machine readable instructions to receive a query, and determine a suitability of the query for processing by a NoSQL data store, or a RDBMS. The memory may further include machine readable instructions to rank data tables based on a combination of read queries and query patterns suitable for the NoSQL data store. Based on the ranking, the memory may further include machine readable instructions to determine data tables that are to be managed by the NoSQL data store, or by the RDBMS, determine whether the query is for a data table managed by the NoSQL data store, and based on a determination that the query is for a data table managed by the NoSQL data store, translate the query to NoSQL API calls for using the NoSQL data store to respond to the query.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: August 8, 2017
    Assignee: ACCENTURE GLOBAL SERVICES LIMITED
    Inventors: Chen Fu, Sugi Venugeethan, Kunal Taneja
  • Patent number: 9720982
    Abstract: A method for natural language search for variables is provided. The method may include searching an index using key words from a user's natural language question and the context of the user's question. The index may reference variables and/or web service calls in a domain model. The method may also include saving documents obtained in response to the search. The method may also include mapping each of the documents as a node into an object graph. Each node may be associated with a parent node, except when the node is a root node. The method may also include identifying the root node of each document. The method may also include identifying the path of each node from the node to the node's root node. The method may also include identifying matching paths. Each matching path may provide an answer to the user's question.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: August 1, 2017
    Assignee: Bank of America Corporation
    Inventors: Viju Kothuvatiparambil, Ramakrishna R. Yannam
  • Patent number: 9720833
    Abstract: A computer system comprising multiple nodes, each node comprising a plurality of processors and a local cache hierarchy, suppresses local cache coherency of a node operations or global cache coherency operations between nodes based on the coherency request being a global or local request, and the state of the cache line at the node.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: August 1, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Garrett Michael Drapala, William J Lewis, Pak-kin Mak, Robert J Sonnelitter, III
  • Patent number: 9703712
    Abstract: A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Robert H. Beers, Ching-Tsun Chou, Robert J. Safranek, James Vash
  • Patent number: 9699017
    Abstract: A storage client and a quorum-based distributed storage system may implement dynamic utilization of bandwidth for a quorum-based distributed storage system. An update at a storage client may be received, and storage nodes of a protection group may be sent a write request indicating the update. In some embodiment, storage nodes that receive the write request may determine whether other storage nodes have not received the update and send the write request to be completed at those other storage nodes. In some embodiments, if a latency threshold is exceeded other storage nodes in the protection group not previously sent the write request may be identified and sent the write request. Based on acknowledgements received from storage nodes in the distributed storage system, it may be determined whether a write quorum requirement is met for a write request.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: July 4, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Anurag Windlass Gupta, Pradeep Jnana Madhavarapu, Samuel James McKelvie, Yan Valerie Leshinsky
  • Patent number: 9697124
    Abstract: A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: July 4, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Hee Jun Park, Krishna Vsssr Vanka, Sravan Kumar Ambapuram, Shirish Kumar Agarwal, Ashvinkumar Namjoshi, Harshad Bhutada
  • Patent number: 9691492
    Abstract: A predetermined pattern of bits is written to a non-volatile memory device prior to powering down the non-volatile memory device. A plurality of voltages are applied to the non-volatile memory device to determine which voltage of the plurality of voltages allows the predetermined pattern of bits to be read with a least amount of error. The determined voltage is set to be a demarcation voltage for reading from the non-volatile memory device.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: June 27, 2017
    Assignee: INTEL CORPORATION
    Inventors: Bruce Querbach, Zion S. Kwok, Christopher F. Connor, Philip Hillier, Jeffrey W. Ryden
  • Patent number: 9684595
    Abstract: A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a processor and selecting an inclusive policy as the inclusion policy for the cache subsystem in response to the cache ratio exceeding an inclusion threshold. The method may further include selecting a non-inclusive policy in response to the cache ratio not exceeding the inclusion threshold and, responsive to a cache transaction resulting in a cache miss, performing an inclusion operation that invokes the inclusion policy.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Larisa Novakovsky, Joseph Nuzman, Alexander Gendler
  • Patent number: 9672266
    Abstract: Methods of conducting database transactions. One such method comprises receiving data to be written to a database; identifying a set of shard replicas corresponding to the database to which the data is to be written; transmitting, to each of the replicas in the set, a request to write the data thereto; receiving votes back from the replicas in the set, each vote representing whether the respective replica commits to a writing of the data thereto; determining whether to commit to the writing of the data to the database according to whether a majority of the replicas of every shard having replicas in the set has transmitted a vote committing to the writing of the data thereto; and transmitting an outcome of the determining to each of the replicas in the set.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: June 6, 2017
    Assignee: Neo Technology, Inc.
    Inventors: James Webber, Ian S. Robinson, Mats Tobias Lindaaker, Alistair Philip Campbell Jones
  • Patent number: 9661561
    Abstract: In a wireless network discovery operation, before a WiFi station sends a network probe request in a WiFi network to request for network information it needs to connect to an access point, it first listens to communications on a current channel of the WiFi network for a preset period of time. When the WiFi station receives on the current channel a network probe request message sent by another WiFi station, it further delays sending the first network probe request by a second time period, in anticipation of some signals from the access point. If during the second time period a network discovery message from the access point, such as a probe response or a beacon message, is detected and that message contains the network information needed, the WiFi station cancels the sending of its probe request. Otherwise, the WiFi station sends its probe request after the second time period expires.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: May 23, 2017
    Assignee: HUAWEI DEVICE CO., LTD.
    Inventor: Guiming Shu
  • Patent number: 9652404
    Abstract: This invention optimizes non-shared accesses and avoids dependencies across coherent endpoints to ensure bandwidth across the system even when sharing. The coherence controller is distributed across all coherent endpoints. The coherence controller for each memory endpoint keeps a state around for each coherent access to ensure the proper ordering of events. The coherence controller of this invention uses First-In-First-Out allocation to ensure full utilization of the resources before stalling and simplicity of implementation. The coherence controller provides Snoop Command/Response ID Allocation per memory endpoint.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: May 16, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew D. Pierson, Kai Chirca
  • Patent number: 9632958
    Abstract: A system for migrating stash transactions includes first and second cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), a queue manager and an operating system (OS) scheduler. The I/O device generates a first stash transaction request for a first data frame. The queue manager stores the first stash transaction request. When the first core executes a first thread, the queue manager stashes the first data frame to the first core by way of the IOMMU. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers. The STMMU uses the pre-empt notifiers to update the IOMMU mapping table and generate a stash replay command. The queue manager receives the stash replay command and stashes the first data frame to the second core.
    Type: Grant
    Filed: July 6, 2014
    Date of Patent: April 25, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Yashpal Dutta, Himanshu Goel, Varun Sethi
  • Patent number: 9621668
    Abstract: The present application is directed towards invalidating (also referred to as poisoning) ASDR table entries that are determined to be inaccurate because of changes to a multi-node system. For example, when a node leaves or enters a multi-node system, the ownership of the entries in the ASDR table can change thus invalidating cached and replica entries. More specifically, the system and methods disclosed herein include searching an ASDR table for cached entries responsive to the system determining the multi-node system has changed. After finding a cached entry, the system may determine if the entry should be poisoned. The decision to poison the entry may be responsive to the creation time of the entry, the time when the change to the multi-node system occurred, and in the case of a replica, the owner of the replica's position in a replication chain relative to source of the replica.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: April 11, 2017
    Assignee: CITRIX SYSTEMS, INC.
    Inventors: Sandeep Kamath, Mahesh Arumugam, Anil Shetty, Gopinath Sikha, Jaidev Sridhar
  • Patent number: 9608842
    Abstract: An embodiment may include circuitry that may provide, at least in part, at least one indication that at least one portion of data is available for processing by at least one data processor. The at least one indication may be provided, at least in part, prior to the entirety of the at least one portion of the data being available for the processing by the at least one data processor. The at least one data processor may begin the processing in response, at least in part, to the at least one indication. Many alternatives, variations, and modifications are possible.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Ygdal Naouri, Ronen Chayat, Ben-Zion Friedman, Parthasarathy Sarangam, Anil Vasudevan, Alain Gravel