Coherency Patents (Class 711/141)
  • Patent number: 11907103
    Abstract: An appropriate test environment is selected while preventing test cases from being detained therein. A test environment determination device includes: an element selection unit that selects one or more test targets and one or more test environments for executing a test case based on target requirements described for specifications of an electronic control unit, which is a test target, and environment requirements described for specifications of a test environment for simulating an external environment of the test target; an environment operation information acquisition unit that acquires operation information on the test environments; and an environment selection unit that selects a combination of the selected test target and the selected test environment based on the acquired operation information.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: February 20, 2024
    Assignee: HITACHI ASTEMO, LTD.
    Inventors: Masashi Mizoguchi, Takahiro Iida, Toru Irie, Yoshimi Yamazaki
  • Patent number: 11870846
    Abstract: Systems and methods of the disclosure include: publishing, by a first host computer system of a computing cluster comprising a plurality of host computer systems running a plurality of virtual machines, a list of memory page identifiers, wherein each memory page identifier is associated with a corresponding content identifier; receiving, from a second host computer system of the computing cluster, a memory page request comprising a first memory page identifier; and sending, to the first host computer system, a first memory page identified by the first memory page identifier.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: January 9, 2024
    Assignee: Red Hat, Inc.
    Inventors: Michael Tsirkin, David Alan Gilbert
  • Patent number: 11822922
    Abstract: A processor may initialize a fetch of a first instruction. The processor may determine whether there is an icache miss for the first instruction. The processor may fetch the next instruction from a cache.
    Type: Grant
    Filed: December 31, 2021
    Date of Patent: November 21, 2023
    Assignee: International Business Machines Corporation
    Inventors: Mohit Karve, Naga P. Gorti
  • Patent number: 11816036
    Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: November 14, 2023
    Assignee: Intel Corporation
    Inventors: Anil Vasudevan, Venkata Krishnan, Andrew J. Herdrich, Ren Wang, Robert G. Blankenship, Vedaraman Geetha, Shrikant M. Shah, Marshall A. Millier, Raanan Sade, Binh Q. Pham, Olivier Serres, Chyi-Chang Miao, Christopher B. Wilkerson
  • Patent number: 11768743
    Abstract: A system and method include migrating, by a migration controller, a first entity of a first subset of entities from a source site to a target site in a virtual computing system based on an asynchronous mode of replication. The system and method also include replicating, by the migration controller, data of a second entity of a second subset of entities from the source site to the target site based on a synchronous mode of replication in parallel with the migration of the first entity for dynamically adjusting a recovery time objective parameter.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: September 26, 2023
    Assignee: Nutanix, Inc.
    Inventors: Kiran Tatiparthi, Ankush Jindal, Monil Devang Shah, Mukul Sharma, Shubham Gupta, Sharad Maheshwari, Kilol Surjan
  • Patent number: 11726915
    Abstract: A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 15, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yasuko Eckert, Maurice B. Steinman, Steven Raasch
  • Patent number: 11675705
    Abstract: An indication to perform an eviction operation on a cache line in a cache can be received. A determination can be made as to whether at least one sector of the cache line is associated with invalid data. In response to determining that at least one sector of the cache line is associated with invalid data, a read operation can be performed to retrieve valid data associated with the at least one sector. The at least one sector of the cache line that is associated with the invalid data can be modified based on the valid data. Furthermore, the eviction operation can be performed on the cache line with the modified at least one sector.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: June 13, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Dhawal Bavishi, Robert M. Walker
  • Patent number: 11669452
    Abstract: A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: June 6, 2023
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Andrea Enrici, Julien Lallet
  • Patent number: 11656801
    Abstract: Methods, systems, and devices related to data relocation via a cache are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In some cases, the memory device may transfer data from a first address of the memory array to the signal development cache. The memory device may transfer the data stored in the signal development cache to a second address of the memory array based on a parameter associated with the first address of the memory array satisfying a criterion for performing data relocation.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: May 23, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shanky Kumar Jain, Dmitri A. Yudanov
  • Patent number: 11645265
    Abstract: Techniques are described handling database transaction in a manner that is efficient and flexible. In some embodiments, a system receives, through a page of a user interface, a first request to change at least a first data object. The system generates, based on the first request, a first atomic transaction to modify the first data object in a database. Before the first atomic database transaction has committed to the database, the system receives, through the page of the user interface, a second request to change at least a second data object. The system generates, based on the second request, a second atomic transaction to modify the second object in the database. The system may execute the second atomic transaction independently of the first atomic transaction.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: May 9, 2023
    Assignee: Oracle International Corporation
    Inventors: Madeleine Dawn Holmes, Surendra Nath V. N. R. K Nukala, Anveshan Reddy Kunduru, Chaitanyasri Molakalapalli
  • Patent number: 11625179
    Abstract: A cache storage system indexing method is provided that indexes a data address in a cache storage system based on a data fingerprint of the cached data, wherein the data fingerprint is generated by a deduplication fingerprint function used for referencing deduplication of data in the cache storage system. A computer-implemented method of data operations to a cache storage system is also provided including: obtaining a data fingerprint for the data of the data operation, either by applying a deduplication fingerprinting function to data of a write operation or by accessing deduplication metadata for a read operation to obtain the data fingerprint generated by using a deduplication fingerprinting function used for deduplication of data in the cache storage system; and using an indexing service to the cache storage system having an address schema based on the data fingerprints of the data.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: April 11, 2023
    Assignee: International Business Machines Corporation
    Inventors: Lee Jason Sanders, Ben Sasson, Gordon Douglas Hutchison
  • Patent number: 11609859
    Abstract: Embodiments of the invention include a machine-readable medium having stored thereon at least one instruction, which if performed by a machine causes the machine to perform a method that includes decoding, with a node, an invalidate instruction; and executing, with the node, the invalidate instruction for invalidating a memory range specified across a fabric interconnect.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: March 21, 2023
    Assignee: Intel Corporation
    Inventors: Karthik Kumar, Thomas Willhalm, Francesc Guim Bernat, Brian J. Slechta
  • Patent number: 11593275
    Abstract: Operating system deactivation of write protection for a storage block is provided absent quiescing of processors in a multi-processor computing environment. The process includes receiving an address translation protection exception interrupt resulting from an attempted write access by a processor to a storage block, and determining by the operating system whether write protection for the storage block is active. Based on write protection for the storage block not being active, the operating system issues an instruction to clear or modify translation lookaside buffer entries of the processor associated with the storage block, absent waiting for an action by another processor of multiple processors of the computing environment, to facilitate write access to the storage block proceeding at the processor.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: February 28, 2023
    Inventors: Christine Michele Yost, Elpida Tzortzatos, Bruce Conrad Giamei, Timothy Slegel, Christian Borntraeger, Damian Osisek, Lisa Cranton Heller, Ute Gaertner
  • Patent number: 11586541
    Abstract: One embodiment can provide a node controller in a multiprocessor system. The node controller can include a processor interface to interface with a processor, a memory interface to interface with a fabric-attached memory, a node-controller interface to interface with a remote node controller, and a cache-coherence logic to operate in a first mode or a second mode. The cache-coherence logic manages cache coherence for a local memory of the processor coupled to the processor interface when operating in the first mode, and the cache-coherence logic manages cache coherence for the fabric-attached memory coupled to the memory interface when operating in the second mode.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: February 21, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Derek Schumacher, Randy Passint, Thomas McGee, Michael Malewicki, Michael S. Woodacre
  • Patent number: 11580035
    Abstract: A processor includes a register to store an encoded pointer to a variable in stack memory. The encoded pointer includes an encrypted portion and a fixed plaintext portion of a memory address corresponding to the variable. The processor further includes circuitry to, in response to a memory access request for associated with the variable, decrypt the encrypted portion of the encoded pointer to obtain first upper address bits of the memory address and a memory allocation size for a variable, decode the encoded pointer to obtain the memory address, verify the memory address is valid based, at least in part on the memory allocation size, and in response to determining that the memory address is valid, allow the memory access request.
    Type: Grant
    Filed: December 26, 2020
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: David M. Durham, Karanvir S. Grewal, Michael D. LeMay, Salmin Sultana, Andrew James Weiler
  • Patent number: 11544181
    Abstract: A storage device includes a controller and nonvolatile memories. The controller receives write commands having virtual stream identifiers (IDs), receives discard commands having the virtual stream IDs, and determines a lifetime of write data to which each of the virtual stream IDs is assigned. The nonvolatile memories are accessed by the controller depending on physical stream IDs. The controller maps the virtual stream IDs and the physical stream IDs based on the lifetime of the write data.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: January 3, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwanjin Yong, Jin-Soo Kim
  • Patent number: 11537427
    Abstract: A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: December 27, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Mark Landers, Martin John Robinson
  • Patent number: 11520733
    Abstract: Provided are systems and methods for linking source data fields to target inputs having a different data structure. In one example, the method may include receiving a request to load a data file from a source data structure to a target data structure, identifying a plurality of target inputs of the target data structure, wherein the plurality of target inputs include a format of the target data structure, and at least one of the target inputs has a format that is different from a format of a source data structure, dynamically linking the plurality of source data fields to the plurality of target inputs based on metadata of the plurality of source data fields, and loading the data file from the source data structure to the target data structure.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: December 6, 2022
    Assignee: SAP SE
    Inventor: Bertram Beyer
  • Patent number: 11513805
    Abstract: A computer architecture employs multiple special-purpose processors having different affinities for program execution to execute substantial portions of general-purpose programs to provide improved performance with respect to a general-purpose processor executing the general-purpose program alone.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: November 29, 2022
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Karthikeyan Sankaralingam, Anthony Nowatzki
  • Patent number: 11494224
    Abstract: An apparatus includes a CPU core, a first cache subsystem coupled to the CPU core, and a second memory coupled to the cache subsystem. The first cache subsystem includes a configuration register, a first memory, and a controller. The controller is configured to: receive a request directed to an address in the second memory and, in response to the configuration register having a first value, operate in a non-caching mode. In the non-caching mode, the controller is configured to provide the request to the second memory without caching data returned by the request in the first memory. In response to the configuration register having a second value, the controller is configured to operate in a caching mode. In the caching mode the controller is configured to provide the request to the second memory and cache data returned by the request in the first memory.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: November 8, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, Timothy David Anderson, David Matthew Thompson
  • Patent number: 11487672
    Abstract: Aspects of the invention include computer-implemented methods, systems, and computer program products that access a multi-copy scope directory state of a cache memory that indicates a scope of sharing of a cache line in a cache memory system and determine a scope of sharing of the cache line in the cache memory system based on the multi-copy scope directory state, where the multi-copy scope directory state enumerates a plurality of scopes within the cache memory system. The scope of sharing is used to reduce a number of queries to one or more cache memories having a larger scope than a shared scope identified in the scope of sharing. The multi-copy scope directory state of the cache memory is updated based on detecting a change in shared scope of the cache line within the cache memory system.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: November 1, 2022
    Inventors: Chunggeon Rhee, Craig R. Walters, Ram Sai Manoj Bamdhamravuri, Timothy Bronson, Gregory William Alexander
  • Patent number: 11467834
    Abstract: A system for computing. In some embodiments, the system includes: a memory, the memory including one or more function-in-memory circuits; and a cache coherent protocol interface circuit having a first interface and a second interface. A function-in-memory circuit of the one or more function-in-memory circuits may be configured to perform an operation on operands including a first operand retrieved from the memory, to form a result. The first interface of the cache coherent protocol interface circuit may be connected to the memory, and the second interface of the cache coherent protocol interface circuit may be configured as a cache coherent protocol interface on a bus interface.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: October 11, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Krishna T. Malladi, Andrew Chang
  • Patent number: 11455107
    Abstract: A method is implemented for a memory sub-system that detects a sequential write pattern in a write sequence for a memory device in a set of commands received from a host, detects current bandwidth utilization deviating from a write bandwidth utilization performance target, in response to detecting the sequential write pattern, and adjusts write bandwidth utilization to conform to the write bandwidth utilization target, in response to detecting the current bandwidth utilization deviating from the write bandwidth utilization performance target.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: September 27, 2022
    Inventors: Suresh Rajgopal, Ling Wang, Yue Wei, Vamsi Pavan Rayaprolu
  • Patent number: 11449269
    Abstract: Apparatuses and methods can be related to implementing edge compute components in a memory array. Compute components can be implemented under a memory array. Implementing compute components under a memory array can limit control access to the compute components due to die space utilized by the compute components. A portion of the compute components (e.g., compute components on the edge) may have control access that is not available to the remainder of the compute components.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: September 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Richard C. Murphy, Honglin Sun
  • Patent number: 11409286
    Abstract: Systems, methods, computer program products, and apparatuses for low latency, fully reconfigurable hardware logic for ensemble classification methods, such as random forests. An apparatus may comprise circuitry for an interconnect and circuitry for a random forest implemented in hardware. The random forest comprising a plurality of decision trees connected via the interconnect, each decision tree comprising a plurality of nodes connected via the interconnect. A first decision tree of the plurality of decision trees comprising a first node of the plurality of nodes to: receive a plurality of elements of feature data via the interconnect, select a first element of feature data, of the plurality of elements of feature data, based on a configuration of the first node, and generate an output based on the first element of feature data, an operation, and a reference value, the operation and reference value specified in the configuration of the first node.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: August 9, 2022
    Inventors: Marcio Juliato, Christopher Gutierrez, Shabbir Ahmed, Manoj Sastry, Liuyang Yang, Xiruo Liu
  • Patent number: 11403144
    Abstract: A method of providing a service to a requesting Infrastructure Element belonging to plurality of Infrastructure Elements interconnected as a data network is proposed. The method includes operating a computing system for receiving a service request requesting a service from the requesting Infrastructure Element. The service request includes an indication of one or more performance requirements. The method also includes converting the service request to a service graph, which includes at least one task to be accomplished by complying with the performance requirements to provide the service. At least one Infrastructure Element currently capable of accomplishing the task complying with the performance requirements is selected, and the selected Infrastructure Element for accomplishing the task is configured. The method further includes causing the selected Infrastructure Element to accomplish the task to provide the service to the requesting Infrastructure Element.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: August 2, 2022
    Assignee: TELECOM ITALIA S.p.A.
    Inventors: Luigi Artusio, Antonio Manzalini
  • Patent number: 11386115
    Abstract: A transactional data storage engine may implement selectable storage endpoints. A selection of storage endpoints may be received at a transactional data storage engine. The selected storage endpoints may identify storage locations maintaining replicas of data for the transactional data storage engine. A storage engine configuration for the transactional data storage engine may be updated to include the storage endpoints so that access requests for the data may be sent to storage endpoints identified according to the storage engine configuration. In some embodiments, storage endpoints may identify strongly consistent or eventually consistent storage locations for performing reads of the data maintained for the transactional data storage engine.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: July 12, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Srinivasan Sundar Raghavan, Swaminathan Sivasubramanian
  • Patent number: 11366762
    Abstract: The present disclosure includes apparatuses and methods related to a memory system including a filter. An example apparatus can include a filter to store a number flags, wherein each of the number of flags corresponds to a cache entry and each of the number of flags identifies a portion of the memory device where data of a corresponding cache entry is stored in the memory device.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Robert M. Walker
  • Patent number: 11354239
    Abstract: Maintaining domain coherence states including Domain State No-Owned (DSN) in processor-based devices is disclosed. In this regard, a processor-based device provides multiple processing elements (PEs) organized into multiple domains, each containing one or more PEs and a local ordering point circuit (LOP). The processor-based device supports domain coherence states for coherence granules cached by the PEs within a given domain. The domain coherence states include a DSN domain coherence state, which indicates that a coherence granule is not cached within a shared modified state within any domain. In some embodiments, upon receiving a request for a read access to a coherence granule, a system ordering point circuit (SOP) determines that the coherence granule is cached in the DSN domain coherence state within a domain of the plurality of domains, and can safely read the coherence granule from the system memory to satisfy the read access if necessary.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: June 7, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Eric Francis Robinson, Kevin Neal Magill, Jason Panavich, Derek Bachand, Michael B. Mitchell, Michael P. Wilson
  • Patent number: 11321495
    Abstract: Embodiments for mitigating security vulnerabilities in a heterogeneous computing system are provided. Anomalous cache coherence behavior may be dynamically detected between a host and one or more accelerators using a cache controller at a shared last level cache based upon a pair-based coherence messages functioning as a proxy for indicating one or more security attack protocols.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: May 3, 2022
    Inventors: Alper Buyuktosunoglu, Hyojin Sung
  • Patent number: 11314644
    Abstract: A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 26, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan
  • Patent number: 11294809
    Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventors: Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther, Buford M. Guy, Thomas R. Huff, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Ronak Singhal, Seyed Yahya Sotoudeh, Bret L. Toll, Lihu Rappoport, David Papworth, James D. Allen
  • Patent number: 11294710
    Abstract: A processing system suspends execution of a program thread based on an access latency required for a program thread to access memory. The processing system employs different memory modules having different memory technologies, located at different points in the processing system, and the like, or a combination thereof. The different memory modules therefore have different access latencies for memory transactions (e.g., memory reads and writes). When a program thread issues a memory transaction that results in an access to a memory module having a relatively long access latency (referred to as “slow” memory), the processor suspends execution of the program thread and releases processor resources used by the program thread. When the processor receives a response to the memory transaction from the memory module, the processor resumes execution of the suspended program thread.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: April 5, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Douglas Benson Hunt
  • Patent number: 11294445
    Abstract: An information processing apparatus includes a memory, a control unit to accept an access to the memory, a power supply circuit to supply a voltage to the memory and the control unit, a detection circuit to detect a drop in the voltage, a discharge circuit, and a delay circuit. The discharge circuit discharges a charge on a voltage supply line extending between the power supply circuit and the memory. The delay circuit delays receipt of a control signal by the discharge circuit for a predetermined period after the discharge circuit receives a charge discharge instruction from the control unit. The control signal is to control discharging the supply line charge. The discharge circuit discharges supply line charges per a control signal based on detection of a drop in the voltage by the detection circuit and based on the delay of the control signal delayed by the delay circuit.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: April 5, 2022
    Inventor: Kohei Asano
  • Patent number: 11288195
    Abstract: A data processing system comprises a requesting node; a home node to control coherency amongst data stored by the data processing system; and one or more further nodes, at least one of the further nodes having a memory; the requesting node being configured to issue a data handling transaction to the home node, the data handling transaction defining a data handling operation relating to a range of memory addresses, the requesting node being configured to maintain an address hazard at the requesting node inhibiting issue of another data handling transaction for that range of memory addresses until the requesting node is notified by the home node that the data handling transaction has completed; the home node being configured, in response to the data handling transaction, to issue one or more data handling instructions to cause one or more given nodes of the one or more further nodes to perform the data handling operation, the home node being configured to notify completion to the requesting node in response to
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: March 29, 2022
    Assignee: Arm Limited
    Inventor: Andrew David Tune
  • Patent number: 11281618
    Abstract: A system is disclosed that includes a first communication circuit that communicates data over a first data port using a first communication protocol. The system also includes a second communication circuit that communicates data over a second data port using a second communication protocol. The second communication protocol processes read and write requests in an order that the read and write requests are received. A bridge circuit is configured to communicate data between the first data port of the first communication circuit and the second data port of the second communication circuit. The bridge circuit is configured to communicate non-posted writes to the second communication circuit via a buffer circuit and communicate posted writes to the second communication circuit via a communication path that bypasses the buffer circuit.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: March 22, 2022
    Assignee: XLNX, INC.
    Inventors: Sagheer Ahmad, Tomai Knopp
  • Patent number: 11283682
    Abstract: Disclosed are systems, methods, and computer-readable media for assuring tenant forwarding in a network environment. Network assurance can be determined in layer 1, layer 2 and layer 3 of the networked environment including, internal-internal (e.g., inter-fabric) forwarding and internal-external (e.g., outside the fabric) forwarding in the networked environment. The network assurance can be performed using logical configurations, software configurations and/or hardware configurations.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: March 22, 2022
    Inventors: Sanchay Harneja, Sanjay Sundaresan
  • Patent number: 11275574
    Abstract: The last successful device update can be recovered on a computing system. An update tool can be employed to detect whether an update package is installed successfully. When an update package is successfully installed, the update tool can define a last successful device update that associates the update package with the device that the update package targets. In contrast, when the update package does not install successfully, the update tool can access the last successful device update for the targeted device and use it to obtain and install the previous update package that the last successful device update represents. In this way, the related components for a device can be rolled back to a common state to prevent incompatibilities that may otherwise exist due to the failed installation.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: March 15, 2022
    Assignee: Dell Products L.P.
    Inventors: Vivekanandh Narayanasamy Rajagopalan, Trinto Thattil Nadakkalan Antony, Ambadas Devrao Jadhav
  • Patent number: 11263155
    Abstract: A realm management unit (RMU) maintains an ownership table specifying ownership entries for corresponding memory regions defining ownership attributes specifying, from among a plurality of realms, an owner realm of the corresponding region. Each realm corresponds to at least a portion of at least one software process. The owner realm has a right to exclude other realms from accessing data stored in the corresponding region. Memory access is controlled based on the ownership table. In response to a region fuse command specifying a fuse target address indicative contiguous regions of memory to be fused into a fused group of regions, a region fuse operation updates the ownership table to indicate that the ownership attributes for the fused group of regions are represented by a single ownership entry. This provides architectural support for enabling improvement of TLB performance.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: March 1, 2022
    Assignee: Arm Limited
    Inventors: Jason Parker, Martin Weidmann
  • Patent number: 11226777
    Abstract: One or more techniques and/or systems are provided for cluster configuration information replication, managing cluster-wide service agents, and/or for cluster-wide outage detection. In an example of cluster configuration information replication, a replication workflow corresponding to a storage operation implemented for a storage object (e.g., renaming of a volume) of a first cluster may be transferred to a second storage cluster for selectively implementation. In an example of managing cluster-wide service agents, cluster-wide service agents are deployed to nodes of a cluster storage environment, where a master agent actively processes cluster service calls and standby agents passively wait for reassignment as a failover master in the event the master agent fails. In an example of cluster-wide outage detection, a cluster-wide outage may be determined for a cluster storage environment based upon a number of inaccessible nodes satisfying a cluster outage detection metric.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: January 18, 2022
    Assignee: NetApp, Inc.
    Inventors: Gregory Buzzard, Justin Travis Cady, Thomas Gilbert Snyder, Satya R. Venneti, Sakir Yucel
  • Patent number: 11221665
    Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: January 11, 2022
    Inventors: Oluleye Olorode, Mehrdad Nourani
  • Patent number: 11210222
    Abstract: An example method of maintaining cache coherency in a virtualized computing system includes: trapping access to a memory page by guest software in a virtual machine at a hypervisor managing the virtual machine, where the memory page is not mapped in a second stage page table managed by the hypervisor; performing cache coherency maintenance for instruction and data caches of a central processing unit (CPU) in the virtualized computing system in response to the trap; mapping the memory page in the second stage page table with execute permission; and resuming execution of the virtual machine.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: December 28, 2021
    Assignee: VMware, Inc.
    Inventors: Ye Li, Cyprien Laplace, Andrei Warkentin, Alexander Fainkichen, Regis Duchesne
  • Patent number: 11204891
    Abstract: A request to open a file from a plurality of files in a storage is received from an application. The storage is made up of an index partition, containing recordings of file system indexes, and a data partition, containing recordings of the indexes and the file system data body. A file descriptor is created with an update flag that references the file. A determination is made that the file is being updated by the application, and the update flag is set to a value representing that the file is being updated. A request to write an index of the file system is received. A determination is made whether a specific file from the plurality of files is being updated. The index is written to the storage with an extended attribute for the specific file indicating that the specific file was being updated at the time the index was written.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: December 21, 2021
    Assignee: International Business Machines Corporation
    Inventors: Atsushi Abe, Tohru Hasegawa, Hiroshi Itagaki
  • Patent number: 11188377
    Abstract: Apparatuses, methods of operating apparatuses, interconnects for connecting apparatuses to one another, and methods of operating the interconnects are disclosed. A master apparatus can issue an individual all-zero-data write transaction specifying a data storage location to the interconnect, which conveys the individual all-zero-data write transaction to a target device which writes all-zero-data at the data storage location. No write data is conveyed with the individual all-zero-data write transaction, so that the individual all-zero-data write transaction may be used to clear the data storage location without adding to congestion of a write data channel in the interconnect.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 30, 2021
    Assignee: Arm Limited
    Inventors: Jamshed Jalal, Mark David Werkheiser, Phanindra Kumar Mannava, Bruce James Mathewson
  • Patent number: 11188480
    Abstract: Systems and methods are provided for addressing die are inefficiencies associated with the use of redundant ternary content-addressable memory (TCAM) for facilitating error detection and correction. Only a portion of redundant TCAMs (or portions of the same TCAM) are reserved for modified coherency directory cache entries, while remaining portions are available for unmodified coherency directory cache entries. The amount of space reserved for redundant, modified coherency directory cache entries can be programmable and adaptable.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: November 30, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Frank R. Dropps, Thomas Edward McGee
  • Patent number: 11188431
    Abstract: Provided are a computer program product, system, and method for managing failover from a first processor node including a first cache to a second processor node including a second cache. Storage areas assigned to the first processor node are reassigned to the second processor node. For each track indicated in a cache list of tracks in the first cache for the reassigned storage areas, the first processor node adds a track identifier of the track and track format information indicating a layout and format of data in the track to a cache transfer list. The first processor node transfers the cache transfer list to the second processor node. The second processor node uses the track format information transferred with the cache transfer list to process read and write requests to tracks in the reassigned storage areas staged into the second cache.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 30, 2021
    Inventors: Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta
  • Patent number: 11182298
    Abstract: In one embodiment, an apparatus includes: a storage having a plurality of entries each to store address information of an instruction and a count value of a number of executions of the instruction during execution of code including the instruction; and at least one comparator circuit to compare a count value from one of the plurality of entries to a threshold value, where the instruction is a tagged instruction of the code, the tagged instruction tagged by a static compiler prior to execution of the code. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: November 23, 2021
    Inventor: Ramanathan Sethuraman
  • Patent number: 11176040
    Abstract: The present application presents a Uniform Memory Access (UMA) network including a cluster of UMA nodes each having at least one UMA memory unit and a server local to the at least one UMA memory unit. A respective UMA memory unit in a respective UMA node comprises persistent memory; non-persistent memory, a node control device operatively coupled to the persistent memory and the non-persistent memory, a local interface for interfacing with the local server in the respective UMA node, and a network interface for interfacing with the UMA network. The node control device is configured to translate between a local unified memory access (UMA) address space accessible by applications running on the local server and a global UMA address space that is mapped to a physical UMA address space. The physical UMA address space includes physical address spaces associated with different UMA nodes in the cluster of UMA nodes.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: November 16, 2021
    Assignee: Netlist, Inc.
    Inventors: Hyun Lee, Junkil Ryu
  • Patent number: 11170469
    Abstract: Methods, systems, and apparatus, including an apparatus for determining pixel coordinates for image transformation and memory addresses for storing the transformed image data. In some implementations, a system includes a processing unit configured to perform machine learning computations for images using a machine learning model and pixel values for the images, a storage medium configured to store the pixel values for the images, and a memory address computation unit that includes one or more hardware processors. The processor(s) are configured to receive image data for an image and determine that the dimensions of the image do not match the dimensions of the machine learning model. In response, the processor(s) determine pixel coordinates for a transformed version of the input image and, for each of the pixel coordinates, memory address(es), in the storage medium, for storing pixel value(s) that will be used to generate an input to the machine learning model.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: November 9, 2021
    Assignee: Google LLC
    Inventors: Carrell Daniel Killebrew, Ravi Narayanaswami, Dong Hyuk Woo
  • Patent number: 11169921
    Abstract: A system and method for cache coherency within multiprocessor environments is provided. Each node controller of a plurality of nodes within a multiprocessor system receives a cache coherency protocol request from local processor sockets and other node controller(s). A ternary content addressable memory (TCAM) accelerator in the node controller determines if the cache coherency protocol request comprises a snoop request and, if it is determined to be a snoop request, searching the TCAM based on an address within the cache coherency protocol request. In response to detecting only one match between an entry of the TCAM and the received snoop request, sending a response to the requesting local processor a response without having to access a coherency directory.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: November 9, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Frank R. Dropps