Coherency Patents (Class 711/141)
  • Patent number: 11494224
    Abstract: An apparatus includes a CPU core, a first cache subsystem coupled to the CPU core, and a second memory coupled to the cache subsystem. The first cache subsystem includes a configuration register, a first memory, and a controller. The controller is configured to: receive a request directed to an address in the second memory and, in response to the configuration register having a first value, operate in a non-caching mode. In the non-caching mode, the controller is configured to provide the request to the second memory without caching data returned by the request in the first memory. In response to the configuration register having a second value, the controller is configured to operate in a caching mode. In the caching mode the controller is configured to provide the request to the second memory and cache data returned by the request in the first memory.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: November 8, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, Timothy David Anderson, David Matthew Thompson
  • Patent number: 11487672
    Abstract: Aspects of the invention include computer-implemented methods, systems, and computer program products that access a multi-copy scope directory state of a cache memory that indicates a scope of sharing of a cache line in a cache memory system and determine a scope of sharing of the cache line in the cache memory system based on the multi-copy scope directory state, where the multi-copy scope directory state enumerates a plurality of scopes within the cache memory system. The scope of sharing is used to reduce a number of queries to one or more cache memories having a larger scope than a shared scope identified in the scope of sharing. The multi-copy scope directory state of the cache memory is updated based on detecting a change in shared scope of the cache line within the cache memory system.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: November 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chunggeon Rhee, Craig R. Walters, Ram Sai Manoj Bamdhamravuri, Timothy Bronson, Gregory William Alexander
  • Patent number: 11467834
    Abstract: A system for computing. In some embodiments, the system includes: a memory, the memory including one or more function-in-memory circuits; and a cache coherent protocol interface circuit having a first interface and a second interface. A function-in-memory circuit of the one or more function-in-memory circuits may be configured to perform an operation on operands including a first operand retrieved from the memory, to form a result. The first interface of the cache coherent protocol interface circuit may be connected to the memory, and the second interface of the cache coherent protocol interface circuit may be configured as a cache coherent protocol interface on a bus interface.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: October 11, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Krishna T. Malladi, Andrew Chang
  • Patent number: 11455107
    Abstract: A method is implemented for a memory sub-system that detects a sequential write pattern in a write sequence for a memory device in a set of commands received from a host, detects current bandwidth utilization deviating from a write bandwidth utilization performance target, in response to detecting the sequential write pattern, and adjusts write bandwidth utilization to conform to the write bandwidth utilization target, in response to detecting the current bandwidth utilization deviating from the write bandwidth utilization performance target.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: September 27, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Suresh Rajgopal, Ling Wang, Yue Wei, Vamsi Pavan Rayaprolu
  • Patent number: 11449269
    Abstract: Apparatuses and methods can be related to implementing edge compute components in a memory array. Compute components can be implemented under a memory array. Implementing compute components under a memory array can limit control access to the compute components due to die space utilized by the compute components. A portion of the compute components (e.g., compute components on the edge) may have control access that is not available to the remainder of the compute components.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: September 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Richard C. Murphy, Honglin Sun
  • Patent number: 11409286
    Abstract: Systems, methods, computer program products, and apparatuses for low latency, fully reconfigurable hardware logic for ensemble classification methods, such as random forests. An apparatus may comprise circuitry for an interconnect and circuitry for a random forest implemented in hardware. The random forest comprising a plurality of decision trees connected via the interconnect, each decision tree comprising a plurality of nodes connected via the interconnect. A first decision tree of the plurality of decision trees comprising a first node of the plurality of nodes to: receive a plurality of elements of feature data via the interconnect, select a first element of feature data, of the plurality of elements of feature data, based on a configuration of the first node, and generate an output based on the first element of feature data, an operation, and a reference value, the operation and reference value specified in the configuration of the first node.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: August 9, 2022
    Assignee: INTEL CORPORATION
    Inventors: Marcio Juliato, Christopher Gutierrez, Shabbir Ahmed, Manoj Sastry, Liuyang Yang, Xiruo Liu
  • Patent number: 11403144
    Abstract: A method of providing a service to a requesting Infrastructure Element belonging to plurality of Infrastructure Elements interconnected as a data network is proposed. The method includes operating a computing system for receiving a service request requesting a service from the requesting Infrastructure Element. The service request includes an indication of one or more performance requirements. The method also includes converting the service request to a service graph, which includes at least one task to be accomplished by complying with the performance requirements to provide the service. At least one Infrastructure Element currently capable of accomplishing the task complying with the performance requirements is selected, and the selected Infrastructure Element for accomplishing the task is configured. The method further includes causing the selected Infrastructure Element to accomplish the task to provide the service to the requesting Infrastructure Element.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: August 2, 2022
    Assignee: TELECOM ITALIA S.p.A.
    Inventors: Luigi Artusio, Antonio Manzalini
  • Patent number: 11386115
    Abstract: A transactional data storage engine may implement selectable storage endpoints. A selection of storage endpoints may be received at a transactional data storage engine. The selected storage endpoints may identify storage locations maintaining replicas of data for the transactional data storage engine. A storage engine configuration for the transactional data storage engine may be updated to include the storage endpoints so that access requests for the data may be sent to storage endpoints identified according to the storage engine configuration. In some embodiments, storage endpoints may identify strongly consistent or eventually consistent storage locations for performing reads of the data maintained for the transactional data storage engine.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: July 12, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Srinivasan Sundar Raghavan, Swaminathan Sivasubramanian
  • Patent number: 11366762
    Abstract: The present disclosure includes apparatuses and methods related to a memory system including a filter. An example apparatus can include a filter to store a number flags, wherein each of the number of flags corresponds to a cache entry and each of the number of flags identifies a portion of the memory device where data of a corresponding cache entry is stored in the memory device.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Robert M. Walker
  • Patent number: 11354239
    Abstract: Maintaining domain coherence states including Domain State No-Owned (DSN) in processor-based devices is disclosed. In this regard, a processor-based device provides multiple processing elements (PEs) organized into multiple domains, each containing one or more PEs and a local ordering point circuit (LOP). The processor-based device supports domain coherence states for coherence granules cached by the PEs within a given domain. The domain coherence states include a DSN domain coherence state, which indicates that a coherence granule is not cached within a shared modified state within any domain. In some embodiments, upon receiving a request for a read access to a coherence granule, a system ordering point circuit (SOP) determines that the coherence granule is cached in the DSN domain coherence state within a domain of the plurality of domains, and can safely read the coherence granule from the system memory to satisfy the read access if necessary.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: June 7, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Eric Francis Robinson, Kevin Neal Magill, Jason Panavich, Derek Bachand, Michael B. Mitchell, Michael P. Wilson
  • Patent number: 11321495
    Abstract: Embodiments for mitigating security vulnerabilities in a heterogeneous computing system are provided. Anomalous cache coherence behavior may be dynamically detected between a host and one or more accelerators using a cache controller at a shared last level cache based upon a pair-based coherence messages functioning as a proxy for indicating one or more security attack protocols.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: May 3, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alper Buyuktosunoglu, Hyojin Sung
  • Patent number: 11314644
    Abstract: A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 26, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan
  • Patent number: 11294445
    Abstract: An information processing apparatus includes a memory, a control unit to accept an access to the memory, a power supply circuit to supply a voltage to the memory and the control unit, a detection circuit to detect a drop in the voltage, a discharge circuit, and a delay circuit. The discharge circuit discharges a charge on a voltage supply line extending between the power supply circuit and the memory. The delay circuit delays receipt of a control signal by the discharge circuit for a predetermined period after the discharge circuit receives a charge discharge instruction from the control unit. The control signal is to control discharging the supply line charge. The discharge circuit discharges supply line charges per a control signal based on detection of a drop in the voltage by the detection circuit and based on the delay of the control signal delayed by the delay circuit.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: April 5, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Kohei Asano
  • Patent number: 11294809
    Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventors: Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther, Buford M. Guy, Thomas R. Huff, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Ronak Singhal, Seyed Yahya Sotoudeh, Bret L. Toll, Lihu Rappoport, David Papworth, James D. Allen
  • Patent number: 11294710
    Abstract: A processing system suspends execution of a program thread based on an access latency required for a program thread to access memory. The processing system employs different memory modules having different memory technologies, located at different points in the processing system, and the like, or a combination thereof. The different memory modules therefore have different access latencies for memory transactions (e.g., memory reads and writes). When a program thread issues a memory transaction that results in an access to a memory module having a relatively long access latency (referred to as “slow” memory), the processor suspends execution of the program thread and releases processor resources used by the program thread. When the processor receives a response to the memory transaction from the memory module, the processor resumes execution of the suspended program thread.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: April 5, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Douglas Benson Hunt
  • Patent number: 11288195
    Abstract: A data processing system comprises a requesting node; a home node to control coherency amongst data stored by the data processing system; and one or more further nodes, at least one of the further nodes having a memory; the requesting node being configured to issue a data handling transaction to the home node, the data handling transaction defining a data handling operation relating to a range of memory addresses, the requesting node being configured to maintain an address hazard at the requesting node inhibiting issue of another data handling transaction for that range of memory addresses until the requesting node is notified by the home node that the data handling transaction has completed; the home node being configured, in response to the data handling transaction, to issue one or more data handling instructions to cause one or more given nodes of the one or more further nodes to perform the data handling operation, the home node being configured to notify completion to the requesting node in response to
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: March 29, 2022
    Assignee: Arm Limited
    Inventor: Andrew David Tune
  • Patent number: 11281618
    Abstract: A system is disclosed that includes a first communication circuit that communicates data over a first data port using a first communication protocol. The system also includes a second communication circuit that communicates data over a second data port using a second communication protocol. The second communication protocol processes read and write requests in an order that the read and write requests are received. A bridge circuit is configured to communicate data between the first data port of the first communication circuit and the second data port of the second communication circuit. The bridge circuit is configured to communicate non-posted writes to the second communication circuit via a buffer circuit and communicate posted writes to the second communication circuit via a communication path that bypasses the buffer circuit.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: March 22, 2022
    Assignee: XLNX, INC.
    Inventors: Sagheer Ahmad, Tomai Knopp
  • Patent number: 11283682
    Abstract: Disclosed are systems, methods, and computer-readable media for assuring tenant forwarding in a network environment. Network assurance can be determined in layer 1, layer 2 and layer 3 of the networked environment including, internal-internal (e.g., inter-fabric) forwarding and internal-external (e.g., outside the fabric) forwarding in the networked environment. The network assurance can be performed using logical configurations, software configurations and/or hardware configurations.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: March 22, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Sanchay Harneja, Sanjay Sundaresan
  • Patent number: 11275574
    Abstract: The last successful device update can be recovered on a computing system. An update tool can be employed to detect whether an update package is installed successfully. When an update package is successfully installed, the update tool can define a last successful device update that associates the update package with the device that the update package targets. In contrast, when the update package does not install successfully, the update tool can access the last successful device update for the targeted device and use it to obtain and install the previous update package that the last successful device update represents. In this way, the related components for a device can be rolled back to a common state to prevent incompatibilities that may otherwise exist due to the failed installation.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: March 15, 2022
    Assignee: Dell Products L.P.
    Inventors: Vivekanandh Narayanasamy Rajagopalan, Trinto Thattil Nadakkalan Antony, Ambadas Devrao Jadhav
  • Patent number: 11263155
    Abstract: A realm management unit (RMU) maintains an ownership table specifying ownership entries for corresponding memory regions defining ownership attributes specifying, from among a plurality of realms, an owner realm of the corresponding region. Each realm corresponds to at least a portion of at least one software process. The owner realm has a right to exclude other realms from accessing data stored in the corresponding region. Memory access is controlled based on the ownership table. In response to a region fuse command specifying a fuse target address indicative contiguous regions of memory to be fused into a fused group of regions, a region fuse operation updates the ownership table to indicate that the ownership attributes for the fused group of regions are represented by a single ownership entry. This provides architectural support for enabling improvement of TLB performance.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: March 1, 2022
    Assignee: Arm Limited
    Inventors: Jason Parker, Martin Weidmann
  • Patent number: 11226777
    Abstract: One or more techniques and/or systems are provided for cluster configuration information replication, managing cluster-wide service agents, and/or for cluster-wide outage detection. In an example of cluster configuration information replication, a replication workflow corresponding to a storage operation implemented for a storage object (e.g., renaming of a volume) of a first cluster may be transferred to a second storage cluster for selectively implementation. In an example of managing cluster-wide service agents, cluster-wide service agents are deployed to nodes of a cluster storage environment, where a master agent actively processes cluster service calls and standby agents passively wait for reassignment as a failover master in the event the master agent fails. In an example of cluster-wide outage detection, a cluster-wide outage may be determined for a cluster storage environment based upon a number of inaccessible nodes satisfying a cluster outage detection metric.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: January 18, 2022
    Assignee: NetApp, Inc.
    Inventors: Gregory Buzzard, Justin Travis Cady, Thomas Gilbert Snyder, Satya R. Venneti, Sakir Yucel
  • Patent number: 11221665
    Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: January 11, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Oluleye Olorode, Mehrdad Nourani
  • Patent number: 11210222
    Abstract: An example method of maintaining cache coherency in a virtualized computing system includes: trapping access to a memory page by guest software in a virtual machine at a hypervisor managing the virtual machine, where the memory page is not mapped in a second stage page table managed by the hypervisor; performing cache coherency maintenance for instruction and data caches of a central processing unit (CPU) in the virtualized computing system in response to the trap; mapping the memory page in the second stage page table with execute permission; and resuming execution of the virtual machine.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: December 28, 2021
    Assignee: VMware, Inc.
    Inventors: Ye Li, Cyprien Laplace, Andrei Warkentin, Alexander Fainkichen, Regis Duchesne
  • Patent number: 11204891
    Abstract: A request to open a file from a plurality of files in a storage is received from an application. The storage is made up of an index partition, containing recordings of file system indexes, and a data partition, containing recordings of the indexes and the file system data body. A file descriptor is created with an update flag that references the file. A determination is made that the file is being updated by the application, and the update flag is set to a value representing that the file is being updated. A request to write an index of the file system is received. A determination is made whether a specific file from the plurality of files is being updated. The index is written to the storage with an extended attribute for the specific file indicating that the specific file was being updated at the time the index was written.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: December 21, 2021
    Assignee: International Business Machines Corporation
    Inventors: Atsushi Abe, Tohru Hasegawa, Hiroshi Itagaki
  • Patent number: 11188377
    Abstract: Apparatuses, methods of operating apparatuses, interconnects for connecting apparatuses to one another, and methods of operating the interconnects are disclosed. A master apparatus can issue an individual all-zero-data write transaction specifying a data storage location to the interconnect, which conveys the individual all-zero-data write transaction to a target device which writes all-zero-data at the data storage location. No write data is conveyed with the individual all-zero-data write transaction, so that the individual all-zero-data write transaction may be used to clear the data storage location without adding to congestion of a write data channel in the interconnect.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 30, 2021
    Assignee: Arm Limited
    Inventors: Jamshed Jalal, Mark David Werkheiser, Phanindra Kumar Mannava, Bruce James Mathewson
  • Patent number: 11188431
    Abstract: Provided are a computer program product, system, and method for managing failover from a first processor node including a first cache to a second processor node including a second cache. Storage areas assigned to the first processor node are reassigned to the second processor node. For each track indicated in a cache list of tracks in the first cache for the reassigned storage areas, the first processor node adds a track identifier of the track and track format information indicating a layout and format of data in the track to a cache transfer list. The first processor node transfers the cache transfer list to the second processor node. The second processor node uses the track format information transferred with the cache transfer list to process read and write requests to tracks in the reassigned storage areas staged into the second cache.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta
  • Patent number: 11188480
    Abstract: Systems and methods are provided for addressing die are inefficiencies associated with the use of redundant ternary content-addressable memory (TCAM) for facilitating error detection and correction. Only a portion of redundant TCAMs (or portions of the same TCAM) are reserved for modified coherency directory cache entries, while remaining portions are available for unmodified coherency directory cache entries. The amount of space reserved for redundant, modified coherency directory cache entries can be programmable and adaptable.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: November 30, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Frank R. Dropps, Thomas Edward McGee
  • Patent number: 11182298
    Abstract: In one embodiment, an apparatus includes: a storage having a plurality of entries each to store address information of an instruction and a count value of a number of executions of the instruction during execution of code including the instruction; and at least one comparator circuit to compare a count value from one of the plurality of entries to a threshold value, where the instruction is a tagged instruction of the code, the tagged instruction tagged by a static compiler prior to execution of the code. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: November 23, 2021
    Assignee: INTEL CORPORATION
    Inventor: Ramanathan Sethuraman
  • Patent number: 11176040
    Abstract: The present application presents a Uniform Memory Access (UMA) network including a cluster of UMA nodes each having at least one UMA memory unit and a server local to the at least one UMA memory unit. A respective UMA memory unit in a respective UMA node comprises persistent memory; non-persistent memory, a node control device operatively coupled to the persistent memory and the non-persistent memory, a local interface for interfacing with the local server in the respective UMA node, and a network interface for interfacing with the UMA network. The node control device is configured to translate between a local unified memory access (UMA) address space accessible by applications running on the local server and a global UMA address space that is mapped to a physical UMA address space. The physical UMA address space includes physical address spaces associated with different UMA nodes in the cluster of UMA nodes.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: November 16, 2021
    Assignee: Netlist, Inc.
    Inventors: Hyun Lee, Junkil Ryu
  • Patent number: 11169921
    Abstract: A system and method for cache coherency within multiprocessor environments is provided. Each node controller of a plurality of nodes within a multiprocessor system receives a cache coherency protocol request from local processor sockets and other node controller(s). A ternary content addressable memory (TCAM) accelerator in the node controller determines if the cache coherency protocol request comprises a snoop request and, if it is determined to be a snoop request, searching the TCAM based on an address within the cache coherency protocol request. In response to detecting only one match between an entry of the TCAM and the received snoop request, sending a response to the requesting local processor a response without having to access a coherency directory.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: November 9, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Frank R. Dropps
  • Patent number: 11170469
    Abstract: Methods, systems, and apparatus, including an apparatus for determining pixel coordinates for image transformation and memory addresses for storing the transformed image data. In some implementations, a system includes a processing unit configured to perform machine learning computations for images using a machine learning model and pixel values for the images, a storage medium configured to store the pixel values for the images, and a memory address computation unit that includes one or more hardware processors. The processor(s) are configured to receive image data for an image and determine that the dimensions of the image do not match the dimensions of the machine learning model. In response, the processor(s) determine pixel coordinates for a transformed version of the input image and, for each of the pixel coordinates, memory address(es), in the storage medium, for storing pixel value(s) that will be used to generate an input to the machine learning model.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: November 9, 2021
    Assignee: Google LLC
    Inventors: Carrell Daniel Killebrew, Ravi Narayanaswami, Dong Hyuk Woo
  • Patent number: 11161464
    Abstract: Generally, the present disclosure is directed to systems and methods for streaming processing within one or more systems of an autonomy computing system. When an update for a particular object or region of interest is received by a given system, the system can control transmission of data associated with the update as well as a determination of other aspects by the given system. For example, the system can determine based on a received update for a particular aspect and a priority classification and/or interaction classification determined for that aspect whether data associated with the update should be transmitted to a subsequent system before waiting for other updates to arrive.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: November 2, 2021
    Assignee: UATC, LLC
    Inventors: David McAllister Bradley, Galen Clark Haynes
  • Patent number: 11163573
    Abstract: A system includes a hierarchical metadata predictor and a processing circuit. The hierarchical metadata predictor includes a first-level metadata predictor and a second-level metadata predictor. The processing circuit is configured to perform a plurality of operations including storing new or updated metadata into the first-level metadata predictor and searching the first-level metadata predictor for a metadata prediction. Responsive to finding the metadata prediction in the first-level metadata predictor, the metadata prediction is output corresponding to an entry of the first-level metadata predictor that is a hit. One or more entries of the first-level metadata predictor that are non-hits are periodically written to the second-level metadata predictor. The first-level metadata predictor is updated based on locating the metadata prediction in the second-level metadata predictor.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James Bonanno, Varnika Atmakuri, Adam Collura, Brian Robert Prasky, Anthony Saporito, Suman Amugothu
  • Patent number: 11157409
    Abstract: A cache memory includes a data array, a directory of contents of the data array that specifies coherence state information, and snoop logic that processes operations snooped from a system fabric by reference to the data array and the directory. The snoop logic, responsive to snooping on the system fabric a request of a first flush/clean memory access operation that specifies a target address, determines whether or not the cache memory has coherence ownership of the target address. Based on determining the cache memory has coherence ownership of the target address, the snoop logic services the request and thereafter enters a referee mode. While in the referee mode, the snoop logic protects a memory block identified by the target address against conflicting memory access requests by the plurality of processor cores until conclusion of a second flush/clean memory access operation that specifies the target address.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: October 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Derek E. Williams, Guy L. Guthrie, Hugh Shen, Luke Murray
  • Patent number: 11157408
    Abstract: A cache memory includes a data array, a directory of contents of the data array that specifies coherence state information, and snoop logic that processes operations snooped from a system fabric by reference to the data array and the directory. The snoop logic, responsive to snooping on the system fabric a request of a flush or clean memory access operation of an initiating coherence participant, determines whether the directory indicates the cache memory has coherence ownership of a target address of the request. Based on determining the directory indicates the cache memory has coherence ownership of the target address, the snoop logic provides a coherence response to the request that causes coherence ownership of the target address to be transferred to the initiating coherence participant, such that the initiating coherence participant can protect the target address against conflicting requests.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: October 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Derek E. Williams, Guy L. Guthrie, Hugh Shen, Luke Murray
  • Patent number: 11126615
    Abstract: Systems for prosecuting Internet messaging campaigns. Two or more data sources are determined where at least one of the data sources comprise demographic attributes corresponding to shared IDs such as recipient IDs. A first join operation is performed over matching instances of the shared IDs in the two or more data sources. The first join operation results in a personalization table comprising rows having at least recipient IDs, respective external addresses, and at least one of the demographic attributes. The personalization table is transformed into a key-value data structure that is published to a caching subsystem. The caching subsystem is used to select a first set of recipients determined without performing a second join operation. Personalized messages to at least some of the first and second set of recipients are formed using the message template and the key-value data structures.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: September 21, 2021
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Jeffrey Taihana Tuatini, Bradley Harold Sergeant, Raghu Upadhyayula, Qing Zou
  • Patent number: 11119926
    Abstract: Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed. A system includes multiple processing nodes, with each processing node including a cache subsystem. The system also includes a cache directory to help manage cache coherency among the different cache subsystems of the system. In order to reduce the number of entries in the cache directory, the cache directory tracks coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Accordingly, the system includes a region-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the system. The cache directory includes a reference count in each entry to track the aggregate number of cache lines that are cached per region. If a reference count of a given entry goes to zero, the cache directory reclaims the given entry.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 14, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Ganesh Balakrishnan, Eric Christopher Morton, Elizabeth M. Cooper, Ravindra N. Bhargava
  • Patent number: 11113250
    Abstract: Techniques for activity tracking, data classification, and in-database archiving are described. Activity tracking refers to techniques that collect statistics related to user access patterns, such as the frequency or recency with which users access particular database elements. The statistics gathered through activity tracking can be supplied to data classification techniques to automatically classify the database elements or to assist users with manually classifying the database elements. Then, once the database elements have been classified, in-database archiving techniques can be employed to move database elements to different storage tiers based on the classifications. However, although the techniques related to activity tracking, data classification, and in-database archiving may be used together as described above; each technique may also be practiced separately.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: September 7, 2021
    Assignee: Oracle International Corporation
    Inventors: Liang Guo, Vivekanandhan Raja, Amit Ganesh, Joshua Gould
  • Patent number: 11106608
    Abstract: A processing unit includes a processor core that executes a store-conditional instruction that generates a store-conditional request specifying a store target address. The processing unit further includes a reservation register that records shared memory addresses for which the processor core has obtained reservations and a cache that services the store-conditional request by conditionally updating the shared memory with the store data based on the reservation register indicating a reservation for the store target address. The cache includes a blocking state machine configured to protect the store target address against access by any conflicting memory access request snooped on a system interconnect during a protection window extension following servicing of the store-conditional request.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: August 31, 2021
    Assignee: International Business Machines Corporation
    Inventors: Derek E. Williams, Guy L. Guthrie, Hugh Shen, Sanjeev Ghai
  • Patent number: 11099919
    Abstract: Methods testing a data coherency algorithm via a simulated multi-processor environment are provided, which include implementing: (i) a transactional footprint keeping the address of each cache line used by the processor core, (ii) a reference model operating on and keeping a set of timestamps for a cache line, the set including a construction date representing a global timestamp when new data arrives at a private cache hierarchy and an expiration date representing another global timestamp when a cross-invalidation hits the private cache hierarchy, (iii) a core observed timestamp representing a global timestamp of an oldest construction date of data used before, and (iv) interface events monitoring instruction sequences guaranteed by transactional execution to ensure atomicity of a transaction. Upon detecting a transaction end event and finding a cache line of the transactional footprint having an expiration date older than or equal to a core observed time, an error is reported.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: August 24, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christian Habermann, Gerrit Koch, Martin Recktenwald, Ralf Winkelmann
  • Patent number: 11100058
    Abstract: In accordance with an embodiment, described herein is a system and method for connection concentration in a database environment. A transparency engine provided between client applications and a database can include a connection pool (e.g., UCP connection pool). The transparency engine can operate as a proxy engine for the database and as a session abstraction layer for the client applications, to enable the client applications to utilize features provided by the connection pool without code changes. The transparency engine can receive application connections from the client applications, and concentrate the application connections on a smaller number of database connections maintained in the connection pool.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: August 24, 2021
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Pablo Silberkasten, Carol Colrain, Kevin Neel, Michael McMahon, Saurabh Verma, Jean De Lavarene
  • Patent number: 11093405
    Abstract: A network processor includes a memory subsystem serving a plurality of processor cores. The memory subsystem includes a hierarchy of caches. A mid-level instruction cache provides for caching instructions for multiple processor cores. Likewise, a mid-level data cache provides for caching data for multiple cores, and can optionally serve as a point of serialization of the memory subsystem. A low-level cache is partitionable into partitions that are subsets of both ways and sets, and each partition can serve an independent process and/or processor core.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: August 17, 2021
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Shubhendu S. Mukherjee, David H. Asher, Richard E. Kessler, Srilatha Manne
  • Patent number: 11093287
    Abstract: Data management for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow a device, such as an endpoint or client device, or another edge resource, to specify criteria for managing data originating from the device and stored in an edge resource, and extends the storage and memory controllers to manage data in accordance with the criteria, including removing stored data that no longer satisfies the criteria. The criteria includes a temporal hint to specify a time after which the data can be removed, a physical hint to specify a list of edge resources outside of which the data can be removed, an event-based hint to specify an event after which the data can be removed, and a quality of service condition to modify the time specified in the temporal hint based on a condition, such as memory and storage capacity of the edge resource in which the data is managed.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Ramanathan Sethuraman, Karthik Kumar, Mark A. Schmisseur, Brinda Ganesh
  • Patent number: 11073892
    Abstract: An apparatus to switch a central processing unit between operational modes includes, in one embodiment, a central processing unit (“CPU”) having at least a first operation mode and a second operation mode, where the second operation mode is a higher performance operation mode than the first operation mode. The apparatus also includes a switching unit that switches a state of the CPU to the second operation mode in response to starting one of an operating system or an application program based on a user operation in a state in which the first operation mode is set, and switches the state of the CPU to the first operation mode in response to a determination that a condition is met.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: July 27, 2021
    Assignee: Lenovo (Singapore) PTE. LTD.
    Inventors: Kazuhiro Kosugi, Takuroh Kamimura
  • Patent number: 11076020
    Abstract: A system and method dynamically transitions the file system role of compute nodes in a distributed clustered file system for an object that includes an embedded compute engine (a storlet). Embodiments of the invention overcome prior art problems of a storlet in a distributed storage system with a storlet engine having a dynamic role module which dynamically assigns or changes a file system role served by the node to a role which is more optimally suited for a computation operation in the storlet. The role assignment is made based on a classification of the computation operation and the appropriate filesystem role that matches computation operation. For example, a role could be assigned which helps reduce storage needs, communication resources, etc.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Duane M. Baldwin, Sasikanth Eda, John T. Olson, Sandeep R. Patil
  • Patent number: 11048630
    Abstract: A symmetrical multi-processing (SMP) node, a distributed SMP (DSMP) system comprising a plurality of SMP nodes, and a method implemented in the SMP node are disclosed. The SMP node comprises: a plurality of processors, a memory coupled to the plurality of processors, and a memory coherent proxy coupled to the plurality of processors through a coherent accelerator interface. The memory coherent proxy is configured to manage statuses of cache lines in the memory.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Zhen Peng Zuo, Peng Fei Gou, Yang Fan Liu, Yang Liu, Hua Xin Yao
  • Patent number: 11042515
    Abstract: Embodiments are directed towards managing and tracking item identification of a plurality of items to determine if an item is a new or existing item, where an existing item has been previously processed. In some embodiments, two or more item identifiers may be generated. In one embodiment, generating the two or more item identifiers may include analyzing the item using a small item size characteristic, a compressed item, or for an identifier collision. The two or more item identifiers may be employed to determine if the item is a new or existing item. In one embodiment, the two or more item identifiers may be compared to a record about an existing item to determine if the item is a new or existing item. If the item is an existing item, then the item may be further processed to determine if the existing item has actually changed.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: June 22, 2021
    Assignee: Splunk Inc.
    Inventors: Amritpal Singh Bath, Mitchell Neuman Blank, Vishal Patel, Stephen Phillip Sorkin
  • Patent number: 11030115
    Abstract: An apparatus for using a dataless cache entry includes a cache memory and a cache controller configured to identify a first cache entry in cache memory as a potential cache entry to be replaced according to a cache replacement algorithm, compare a data value of the first cache entry to a predefined value, and write a memory address tag and state bits of the first cache entry to a dataless cache entry in response to the data value of the first cache entry matching the predefined value, wherein the dataless cache entry in the cache memory stores a memory address tag and state bits associated with the memory address, wherein the dataless cache entry represents the predefined value, and wherein the dataless cache entry occupies fewer bits than the first cache entry.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 8, 2021
    Assignee: LENOVO Enterprise Solutions (Singapore) PTE. LTD
    Inventor: Daniel J Colglazier
  • Patent number: 11016913
    Abstract: In one embodiment, a cache coherent system includes one or more agents (e.g. coherent agents) that may cache data used by the system. The system may include a point of coherency in a memory controller in the system, and thus the agents may transmit read requests to the memory controller to coherently read data. The point of coherency may determine if the data is cached in another agent, and may transmit a copy back request to the other agent if the other agent has modified the data. The system may include an interconnect between the agents and the memory controller. At a point on the interconnect at which traffic from the agents converges, a copy back response may be converted to a fill for the requesting agent.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: May 25, 2021
    Assignee: Apple Inc.
    Inventors: Harshavardhan Kaushikkar, Christopher D. Shuler, Srinivasa Rangan Sridharan, Yu Zhang, Kaushik Kannan, Deniz Balkan
  • Patent number: 11016896
    Abstract: Maintaining multiple cache areas in a storage device having multiple processors includes loading data from a specific portion of non-volatile storage into a local cache slot in response to a specific processor of a first subset of the processors performing a read operation to the specific portion of non-volatile storage, where the local cache slot is accessible to the first subset of the processors and is inaccessible to a second subset of the processors that is different than the first subset of the processors and includes converting the local cache slot into a global cache slot in response to one of the processors performing a write operation to the specific portion of non-volatile storage, wherein the global cache area is accessible to the first subset of the processors and to the second subset of the processors. Different ones of the processors may be placed on different directors.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: May 25, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Venkata Khambam, Jeffrey R. Nelson, Brian Asselin, Rong Yu