Coherency Patents (Class 711/141)
  • Patent number: 10402273
    Abstract: The disclosed technology is generally directed to IoT device update failure recovery. In one example of the technology, after writing an updated release to memory, a determination is made whether the updated release is valid. The updated release includes a plurality of image binaries. If the updated release is determined to be valid, the updated release is made the current release. A determination is made as to whether the current release is stable. Upon determining that the current release is unstable, an auto-rollback is performed. Performing the auto-rollback includes, via at least one processor, automatically: obtaining an uncompressed backup of a previous release; making the uncompressed backup of the previous release the current release; and executing the uncompressed backup.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: September 3, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Reuben R. Olinsky, Edmund B. Nightingale
  • Patent number: 10402287
    Abstract: According to an example, data corruption and single point of failure is prevented in a fault-tolerant memory fabric with multiple redundancy controllers by granting, by a parity media controller, a lock of a stripe to a redundancy controller to perform a sequence on the stripe. The lock may be broken in response to determining a failure of the redundancy controller prior to completing the sequence. In response to breaking the lock, the parity cacheline of the stripe may be flagged as invalid. Also, a journal may be updated to document the breaking of the lock.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: September 3, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Derek Alan Sherlock, Harvey Ray, Chris Michael Brueggen
  • Patent number: 10394492
    Abstract: According to one embodiment, a system includes a media storage device, a processor, and logic integrated with and/or executable by the processor. The logic is configured to cause the processor to determine a write rate for the media storage device or a portion thereof based on one or more factors, the write rate ranging from zero to a maximum possible write rate for the media storage device or the portion thereof. The logic is also configured to cause the processor to receive a write request to write data to the media storage device or the portion thereof and write the data to the media storage device using the determined write rate. Other systems, methods, and computer program products for defending against ransomware attacks are presented according to more embodiments.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: August 27, 2019
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: John Michael Petersen, Gary David Cudak, Shareef Fathi Alshinnawi, Ajay Dholakia
  • Patent number: 10387310
    Abstract: A data processing system includes first and second coherency domains and employs a snoop-based coherence protocol. In response to receipt by the first coherency domain of a memory access request originating from a master in the second coherency domain, a plurality of coherence participants in the first coherency domain provides partial responses for the memory access request to an early combined response generator. Based on the partial responses, the early combined response generator generates and transmits, to a memory controller of a system memory in the first coherency domain, an early combined response of only the first coherency domain. Based on the early combined response, the memory controller transmits, to the master prior to receipt by the memory controller of a systemwide combined response for the memory access request, data associated with a target memory address and/or coherence permission for the target memory address.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric E. Retter, Michael S. Siegel, Jeffrey A. Stuecheli, Derek E. Williams
  • Patent number: 10380099
    Abstract: A computer-implemented method is provided for managing and sharing picture files. In one embodiment of the present invention, the method comprises providing a server platform and providing a datastore on the server platform for maintaining full resolution copies of the files shared between a plurality of sharing clients. A synchronization engine is provided on the server platform and is configured to send real-time updates to a plurality of sharing clients when at least one of the sharing clients updates or changes one of said files. A web interface may also be provided that allows a user to access files in the datastore through the use of a web browser.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: August 13, 2019
    Assignee: DROPBOX, INC.
    Inventors: Jack Benjamin Strong, Gibu Thomas
  • Patent number: 10379856
    Abstract: A data processing system implementing a weak memory model includes a plurality of processing units coupled to an interconnect fabric. In response execution of a multicopy atomic store instruction, an initiating processing unit broadcasts a store request on the interconnect fabric to obtain coherence ownership of a target cache line. The initiating processing unit posts a kill request to at least one of the plurality of processing units to request invalidation of a copy of the target cache line. In response to successful posting of the kill request, the initiating processing unit broadcasts a store complete request on the interconnect fabric to enforce completion of the invalidation of the copy of the target cache line. In response to the store complete request receiving a coherence response indicating success, the initiating processing unit permits an update to the target cache line requested by the multicopy atomic store instruction to be atomically visible.
    Type: Grant
    Filed: June 4, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Derek E. Williams
  • Patent number: 10372638
    Abstract: A method for modifying an address in a multi-processor system may include performing a first transaction to modify an address between a first processor and an interconnect agent associated with the first processor and storing data for the address on the interconnect agent. The method may further include performing a second transaction to modify an address between the interconnect agent and a memory associated with a second processor and storing the data in the memory.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: August 6, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Thomas E. McGee
  • Patent number: 10373285
    Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.
    Type: Grant
    Filed: April 9, 2017
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Altug Koker, James A. Valerio, David Puffer, Abhishek R. Appu, Stephen Junkins
  • Patent number: 10362143
    Abstract: A system and method dynamically transitions the file system role of compute nodes in a distributed clustered file system for an object that includes an embedded compute engine (a storlet). Embodiments of the invention overcome prior art problems of a storlet in a distributed storage system with a storlet engine having a dynamic role module which dynamically assigns or changes a file system role served by the node to a role which is more optimally suited for a computation operation in the storlet. The role assignment is made based on a classification of the computation operation and the appropriate filesystem role that matches computation operation. For example, a role could be assigned which helps reduce storage needs, communication resources, etc.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Duane M. Baldwin, Sasikanth Eda, John T. Olson, Sandeep R. Patil
  • Patent number: 10360054
    Abstract: File mapping and converting for dynamic disk personalization for multiple platforms are provided. A volatile file operation is detected in a first platform. The file supported by the first platform. A determination is made that the file is sharable with a second platform. The volatile operation is performed on the file in the first platform and the modified file is converted to a second file supported by the second platform. The modified file and second file are stored in a personalized disk for a user. The personalized disk is used to modify base images for VMs of the user when the user accesses the first platform or second platform. The modified file is available within the first platform and the second file is available within the second platform.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: July 23, 2019
    Assignee: Micro Focus Software Inc.
    Inventors: Nathaniel Brent Kranendonk, Jason Allen Sabin, Lloyd Leon Burch, Jeremy Ray Brown, Kal A. Larsen, Michael John Jorgensen
  • Patent number: 10353601
    Abstract: A memory system of a data processing system includes one or more storage devices and a data rearrangement engine for moving data between memory regions of the plurality of memory regions. The data rearrangement engine is configured to rearrange data stored at non-contiguous addresses in a source memory region into contiguous address in a destination region responsive to a rearrangement specified by a host processing unit of the data processing system. A description of the rearranged data is maintained in a metadata memory region. Rearranged data may be accessed by one or more host processing units. Write-back of data from the destination to the source region may be reduced by use of Bloom filter or the like.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: July 16, 2019
    Assignee: Arm Limited
    Inventor: Jonathan Curtis Beard
  • Patent number: 10346091
    Abstract: Methods and apparatus related to fabric resiliency support for atomic writes of many store operations to remote nodes are described. In one embodiment, non-volatile memory stores data corresponding to a plurality of write operations. A first node includes logic to perform one or more operations (in response to the plurality of write operations) to cause storage of the data at a second node atomically. The plurality of write operations are atomically bound to a transaction and the data is written to the non-volatile memory in response to release of the transaction. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Thomas Willhalm, Karthik Kumar, Martin P. Dimitrov, Raj K. Ramanujan
  • Patent number: 10346082
    Abstract: A storage system manages control information, which is information related to responses corresponding to prescribed types of commands, for each of a plurality of logical units associated with a logical device, said logical units being provided to one or more host systems. The prescribed types of commands indicating the logical units provided to a first host system, which is one of the one or more host systems, are received from the first host system by the storage system. Responses based on the control information corresponding to the logical units indicated by the received prescribed types of commands are returned to the first host system by the storage system as responses to the received prescribed types of commands.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: July 9, 2019
    Assignee: HITACHI LTD.
    Inventors: Azusa Jin, Hideo Saito, Shunji Kawamura, Kenji Muraoka, Kunihiko Nashimoto
  • Patent number: 10339060
    Abstract: System, method, and processor for enabling early deallocation of tracker entries which track memory accesses are described herein. One embodiment of a method includes: maintaining an RSF corresponding to a first processing unit of a plurality of processing units to track cache lines, wherein a cache line is tracked by the RSF if the cache line is stored in both a memory and one or more other processing unit, the memory is coupled to and shared by the plurality of processing units; receiving a request to access a target cache line from a processing core of the first processing unit; allocating a tracker entry corresponding to the request, the tracker entry used to track a status of the request; performing a lookup in the RSF for the target cache line; and deallocating the tracker entry responsive to a detection that the target cache line is not tracked the RSF.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Bahaa Fahim, Ashok Jagannathan, Jeffrey D. Chamberlain, Samuel D. Strom
  • Patent number: 10320904
    Abstract: A computer-implemented method is provided for managing and sharing picture files. In one embodiment of the present invention, the method comprises providing a server platform and providing a datastore on the server platform for maintaining full resolution copies of the files shared between a plurality of sharing clients. A synchronization engine is provided on the server platform and is configured to send real-time updates to a plurality of sharing clients when at least one of the sharing clients updates or changes one of said files. A web interface may also be provided that allows a user to access files in the datastore through the use of a web browser.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: June 11, 2019
    Assignee: DROPBOX, INC.
    Inventors: Jack Benjamin Strong, Gibu Thomas
  • Patent number: 10303602
    Abstract: A processing system includes at least one central processing unit (CPU) core, at least one graphics processing unit (GPU) core, a main memory, and a coherence directory for maintaining cache coherence. The at least one CPU core receives a CPU cache flush command to flush cache lines stored in cache memory of the at least one CPU core prior to launching a GPU kernel. The coherence directory transfers data associated with a memory access request by the at least one GPU core from the main memory without issuing coherence probes to caches of the at least one CPU core.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 28, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Onur Kayiran, Gabriel H. Loh, Yasuko Eckert
  • Patent number: 10289553
    Abstract: Disclosed aspects relate to accelerator sharing among a plurality of processors through a plurality of coherent proxies. The cache lines in a cache associated with the accelerator are allocated to one of the plurality of coherent proxies. In a cache directory for the cache lines used by the accelerator, the status of the cache lines and the identification information of the coherent proxies to which the cache lines are allocated are provided. Each coherent proxy maintains a shadow directory of the cache directory for the cache lines allocated to it. In response to receiving an operation request, a coherent proxy corresponding to the request is determined. The accelerator communicates with the determined coherent proxy for the request.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Peng Fei Bg Gou, Yang Liu, Yang Fan El Liu, Yong Lu
  • Patent number: 10282299
    Abstract: Partition information includes entries that each include an entity identifier and associated cache configuration information. A controller manages memory requests originating from processor cores, including: comparing at least a portion of an address included in a memory request with tags stored in a cache to determine whether the memory request results in a hit or a miss, and comparing an entity identifier included in the memory request with stored entity identifiers to determine a matched entry. The cache configuration information associated with the entity identifier in a matched entry is updated based at least in part on a hit or miss result. The associated cache configuration information includes cache usage information that tracks usage of the cache by an entity associated with the particular entity identifier, and partition descriptors that each define a different group of one or more of the regions.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: May 7, 2019
    Assignee: Cavium, LLC
    Inventors: Shubhendu Sekhar Mukherjee, David Asher, Wilson P. Snyder, II
  • Patent number: 10261904
    Abstract: Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Chunhui Zhang, George Z. Chrysos, Edward T. Grochowski, Ramacharan Sundararaman, Chung-Lun Chan, Federico Ardanaz
  • Patent number: 10255118
    Abstract: A system and method of allocating resources among cores in a multi-core system is disclosed. The system and method determine cores that are able to process tasks to be performed, and use history of usage information to select a core to process the tasks. The system may be a heterogeneous multi-core processing system, and may include a system on chip (SoC).
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: April 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki Soo Yu, Kyung Il Sun, Chang Hwan Youn
  • Patent number: 10254990
    Abstract: Method, system and product for direct access to de-duplicated data units in memory-based file systems. The method comprising: updating a page entry in a page table of a process to include a direct access pointer to a de-duplicated data unit retained by the memory-based file system, wherein the page entry is set to be write protected; detecting a page fault occurring due to the process performing a store instruction to the de-duplicated data unit; and in response to said detecting: allocating a new data unit; copying content of the de-duplicated data unit to the new data unit; and replacing the direct access pointer to the de-duplicated data unit with a direct access pointer to the new data unit.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: April 9, 2019
    Assignee: NETAPP, INC.
    Inventors: Amit Golander, Yigal Korman, Boaz Harrosh
  • Patent number: 10255305
    Abstract: Technologies for object-based data consistency in a fabric architecture includes a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to receive an object read request that includes an object identifier and a data consistency threshold from one of the computing nodes. The network switch is additionally configured to perform a lookup for a value of an object in the cache memory as a function of the object identifier and determine whether a condition of the value of the object violates the data consistency threshold in response to a determination that the lookup successfully returned the value of the object. The network switch is further configured to transmit the value of the object to the computing node in response to a determination that the condition of the value of the object does not violate the data consistency threshold. Other embodiments are described herein.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Thomas Willhalm, Karthik Kumar, Raj K. Ramanujan, Daniel Rivas Barragan
  • Patent number: 10255182
    Abstract: A method of managing a cache includes storing first data of an upper level cache in a lower level cache, predicting a reuse distance level of second data having a same signature as the first data based on access information about the first data, and storing the second data in one of the lower level cache and a main memory based on the predicted reuse distance level of the second data.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: April 9, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Namhyung Kim, Junwhan Ahn, Kiyoung Choi, Woong Seo
  • Patent number: 10248325
    Abstract: Memory is to store cache lines, where the cache lines include data and directory information to indicate a directory state of the corresponding cache line. A command is received from a processor over a link, the command including an address. The address is determined to correspond to a particular cache line and the particular cache line is identified to have a particular directory state from the corresponding directory information of the particular cache line. A type of the command is identified and a determination is made that that the directory state of the particular cache line is to change from the particular state to a new state based on the type of the command. The directory information of the particular cache line is changed to reflect the new state and a response is generated to the command.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventor: Robert G. Blankenship
  • Patent number: 10241945
    Abstract: In a data processing system implementing a weak memory model, a lower level cache receives, from a processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed. The lower level cache also receives, from the processor core, a barrier request that requests enforcement of ordering of memory access requests prior to the barrier request with respect to memory access requests after the barrier request. Prior to completion of processing of the barrier request by the lower level cache, the lower level cache speculatively issues a request on the interconnect fabric to obtain a copy of a data granule specified by a memory access request among the pluralities of requests that follows the barrier request in program order.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Derek E. Williams
  • Patent number: 10229024
    Abstract: An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Mohan J. Kumar, Balint Fleischer
  • Patent number: 10223186
    Abstract: A coherency error detection and reporting mechanism monitors for coherency errors in a processor and between processors. When a requestor broadcasts a memory address in a command and a coherency error is detected, information regarding the command that caused the coherency error is logged, and the coherency error is reported a system error handler. The information logged for the coherency error may include the address of the coherency error, the requestor, the command, the response to the command, the scope of the coherency error, the error type, etc. Logging information relating to the coherency error provides more information to a person analyzing the processor for failures to more easily track down the cause of coherency errors.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: John T. Hollaway, Jr., Charles F. Marino, Michael S. Siegel
  • Patent number: 10223266
    Abstract: A load store unit (LSU) in a processor core detects that new data produced by the processor core is ready to be drained to an L2 cache. In response to the LSU detecting that an earlier version of the new data is not stored in L1 cache, a memory controller sends the new data as L1 cache missed data to a store queue (STQ), where the STQ makes data available for deallocation from the STQ to the L2 cache. In response to determining that there is no newer data waiting to be stored in the STQ, or no cache line invalidate to the line containing the store data in the STQ that misses the cache, the memory controller maintains the new data in the STQ with a zombie stat bit that indicates that the new data is a zombie store entry that can be utilized by the processor core.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robert A. Cordes, Hung Q. Le, Brian W. Thompto
  • Patent number: 10216781
    Abstract: Techniques are described for maintaining coherency of a portion of a database object populated in the volatile memories of multiple nodes in a database cluster. The techniques involve maintaining a local invalidation bitmap for chunks of data stored in memory in each particular node in the cluster by tracking locks granted by a lock manager. During a pre-loading operation, each given node requests a set of shared locks associated with the chunks of data to be store in the given node's memory. When a request to release one of these shared locks occurs, the in-memory copy of those data items may be invalidated in the node releasing its shared lock.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: February 26, 2019
    Assignee: Oracle International Corporation
    Inventors: Sanket Hase, Neil MacNaughton, Vivekanandhan Raja, Atrayee Mullick, Vineet Marwah, Amit Ganesh
  • Patent number: 10216580
    Abstract: Methods, system and computer program product for backup and restore mainframe data onto an object storage, the methods comprising a backup operation and a restore operation, the backup operation comprising: receiving a request for backing up a data set; splitting the data set into chunks, each chunk having a predetermined size; creating a mapping object; repeating for each chunk: allocating a sender thread to the chunk; transmitting using an object storage API, the chunk having the predetermined size as an object, to the object storage by the sender thread; and updating the mapping object with details of the chunk; subject to the data set being fully split and no more chunks to be transmitted, transmitting the mapping object to the object storage by the sender thread; and writing an identifier of the data set and meta data of the mapping object to a database.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: February 26, 2019
    Assignee: MODEL9 SOFTWARE LTD.
    Inventors: Gil Peleg, Yuval Kashtan, Tomer Zelberzvig, Dori Polotsky, Offer Baruch
  • Patent number: 10216662
    Abstract: Embodiments of systems, apparatuses, and methods for remote action handling are describe. In an embodiment, a hardware apparatus comprises: a first register to store a memory address of a payload corresponding to an action to be performed associated with a remote action request (RAR) interrupt, a second register to store a memory address of an action list accessible by a plurality of processors, and a remote action handler circuit to identify a received RAR interrupt, perform an action of the received RAR interrupt, and signal acknowledgment to an initiating processor upon completion of the action.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: Michael Mishaeli, Ido Ouziel, Baruch Chaikin, Yoav Zach
  • Patent number: 10216633
    Abstract: There is provided a data processing device including an output port to transmit a request value to an interconnect arranged to implement a coherency protocol, to indicate a request to be subjected to the coherency protocol. An input port receives an acknowledgement value from the interconnect in response to the request value and coherency administration circuitry defines behavior rules for the data processing device in accordance with the coherency protocol and in dependence on the request value and the acknowledgement value. Storage circuitry administers data in accordance with the behavior rules. There is also provided an interconnect including an input port to receive a request value, issued by a data processing device having storage circuitry, to indicate a request for the data processing to be subjected to a coherency protocol.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: February 26, 2019
    Assignee: Arm Limited
    Inventors: Dominic William Brown, Ashley John Crawford
  • Patent number: 10216519
    Abstract: A data processing system implementing a weak memory model includes a plurality of processing units coupled to an interconnect fabric. In response execution of a multicopy atomic store instruction, an initiating processing unit broadcasts a store request on the interconnect fabric to obtain coherence ownership of a target cache line. The initiating processing unit posts a kill request to at least one of the plurality of processing units to request invalidation of a copy of the target cache line. In response to successful posting of the kill request, the initiating processing unit broadcasts a store complete request on the interconnect fabric to enforce completion of the invalidation of the copy of the target cache line. In response to the store complete request receiving a coherence response indicating success, the initiating processing unit permits an update to the target cache line requested by the multicopy atomic store instruction to be atomically visible.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Derek E. Williams
  • Patent number: 10216413
    Abstract: Techniques are provided by which memory pages may be migrated among PPU memories in a multi-PPU system. According to the techniques, a UVM driver determines that a particular memory page should change ownership state and/or be migrated between one PPU memory and another PPU memory. In response to this determination, the UVM driver initiates a peer transition sequence to cause the ownership state and/or location of the memory page to change. Various peer transition sequences involve modifying mappings for one or more PPU, and copying a memory page from one PPU memory to another PPU memory. Several steps in peer transition sequences may be performed in parallel for increased processing speed.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: February 26, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., John Mashey, Mark Hairgrove, Chenghuan Jia, Cameron Buschardt, Lucien Dunning, Brian Fahs
  • Patent number: 10216692
    Abstract: A multiprocessor system on a chip (MPSoC) implements parallel processing and include a plurality of cores with inter-core communication. This communication is implemented by an on-chip switch fabric in communication with each core, or by shared memory in communication with each core. In another embodiment, a parallel processing system is implemented as a Howard Cascade and uses shared memory for implementing inter-chip communication. The parallel processing system includes a plurality of chips, each formed as an MPSoC, and implements communication between the chips using shared memory.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: February 26, 2019
    Assignee: Massively Parallel Technologies, Inc.
    Inventor: Kevin D. Howard
  • Patent number: 10210091
    Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a no-locality hint vector memory access instruction. The no-locality hint vector memory access instruction to indicate a packed data register of the plurality of packed data registers that is to have a source packed memory indices. The source packed memory indices to have a plurality of memory indices. The no-locality hint vector memory access instruction is to provide a no-locality hint to the processor for data elements that are to be accessed with the memory indices. The processor also includes an execution unit coupled with the decode unit and the plurality of packed data registers. The execution unit, in response to the no-locality hint vector memory access instruction, is to access the data elements at memory locations that are based on the memory indices.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: February 19, 2019
    Assignee: Intel Corporation
    Inventor: Christopher J. Hughes
  • Patent number: 10205673
    Abstract: Disclosed is a data caching method, comprising: according to an input port number of a cell, storing the cell in a corresponding first-in first-out queue; determining that a cell to be dequeued can be dequeued in the current Kth cycle, scheduling for the cell to be dequeued to be dequeued, acquiring the actual value of the number of splicing units occupied by the cell to be dequeued, and storing the cell to be dequeued in a register the same number of bits wide as a bus in a cell splicing manner, wherein determining that the cell to be dequeued can be dequeued is conducted in accordance with the fact that a first back pressure count value of the (K?1)th cycle is less than or equal to a first preset threshold value, and the first back pressure count value of the (K?1)th cycle is obtained in accordance with an estimated value of the number of the splicing units occupied when the previous cell to be dequeued is dequeued, the number of splicing units capable of being transmitted by the bus in each cycle, and a fi
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: February 12, 2019
    Assignee: Sanechips Technology Co. Ltd.
    Inventors: Jiao Zhao, Mingliang Lai, Haoxuan Tian, Yanrui Chang
  • Patent number: 10204049
    Abstract: Methods and apparatus relating to improving the value of F-state by increasing a local caching agent's data forwarding are described. In one embodiment, the opportunity for forwarding from a local caching agent is improved by allowing the local caching agent to keep an F-state copy of the line while sending an S-state copy to the requestor (e.g., in response to a non-ownership read operation). Other embodiments are also disclosed.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Vedaraman Geetha, Jeffrey D. Chamberlain, Sailesh Kottapalli, Ganesh Kumar, Henk G. Neefs, Neil J. Achtman, Bongjin Jung
  • Patent number: 10198261
    Abstract: A method of performing memory synchronization operations is provided that includes receiving, at a programmable cache controller in communication with one or more caches, an instruction in a first language to perform a memory synchronization operation of synchronizing a plurality of instruction sequences executing on a processor, mapping the received instruction in the first language to one or more selected cache operations in a second language executable by the cache controller and executing the one or more cache operations to perform the memory synchronization operation. The method further comprises receiving a second mapping that provides mapping instructions to map the received instruction to one or more other cache operations, mapping the received instruction to one or more other cache operations and executing the one or more other cache operations to perform the memory synchronization operation.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: February 5, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shuai Che, Marc S. Orr, Bradford M. Beckmann
  • Patent number: 10186302
    Abstract: A semiconductor system includes a controller. The controller is configured to have a write buffer that stores first write data outputted from a host before the first write data is written into a memory circuit. The controller is configured to write the first write data stored in the write buffer into the memory circuit under a first condition and configured to double-write the first write data stored in the write buffer into the memory circuit under a second condition.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: January 22, 2019
    Assignee: SK hynix Inc.
    Inventors: Soojin Kim, Sangwon Lee
  • Patent number: 10185639
    Abstract: An example computer-implemented method for performing failover operations in a data storage system is described herein. The data storage system can include a first storage controller and a second storage controller for processing input/output (“I/O”) operations for the data storage system. The method can include, in response to a failure of the first storage controller, performing failover operations with the second storage controller, and processing the I/O operations with the second storage controller. The failover operations can include preparing a disk subsystem layer for I/O operations, preparing a device manager layer for the I/O operations, and preparing a network layer for the I/O operations. The disk subsystem, device manager, and network layers can be prepared for the I/O operations without dependencies. In particular, preparation of the network layer is not dependent on preparation of the disk subsystem layer or the device manager layer.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: January 22, 2019
    Assignee: AMERICAN MEGATRENDS, INC.
    Inventors: Paresh Chatterjee, Vijayarankan Muthirisavenugopal, Jomy Jose Maliakal, Sharon Samuel Enoch
  • Patent number: 10180796
    Abstract: A memory system includes: a plurality of first memory devices directly or indirectly coupled to one another, each first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a multi-processor including a plurality of processors, each processor executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: January 15, 2019
    Assignee: SK Hynix Inc.
    Inventors: Chang-Hyun Kim, Min-Chang Kim, Do-Yun Lee, Yong-Woo Lee, Jae-Jin Lee, Hoe-Kwon Jung
  • Patent number: 10175992
    Abstract: Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Leon Polishuk, Pavel Konev, Larisa Novakovsky, Julius Mandelblat
  • Patent number: 10169236
    Abstract: A cache coherency controller comprises a directory indicating, for memory addresses cached by one or more of a group of one or more cache memories connectable in a coherent cache structure, which of the cache memories are caching those memory addresses; and control circuitry configured to detect a directory entry relating to a memory address to be accessed so as to coordinate, amongst the cache memories, an access to a memory address by one of the cache memories or a coherent agent in instances when the directory entry indicates that another of the cache memories is caching that memory address; the control circuitry being responsive to status data indicating whether each cache memory in the group is currently subject to cache coherency control so as to take into account, in the detection of the directory entry relating to the memory address to be accessed, only those cache memories in the group which are currently subject to cache coherency control.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: January 1, 2019
    Assignee: ARM Limited
    Inventors: Sean James Salisbury, Andrew David Tune
  • Patent number: 10157139
    Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing asynchronous cache maintenance operations on a computing device, including activating a first asynchronous cache maintenance operation, determining whether an active address of a memory access request to a cache is in a first range of addresses of the first active asynchronous cache maintenance operation, and queuing the first active asynchronous cache maintenance operation as the first asynchronous cache maintenance operation in a fixup queue in response to determining that the active address is in the first range of addresses.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: December 18, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Andrew Edmund Turner
  • Patent number: 10154092
    Abstract: A network of PCs includes an I/O channel adapter and network adapter, and is configured for management of a distributed cache memory stored in the plurality of PCs interconnected by the network. The use of standard PCs reduces the cost of the data storage system. The use of the network of PCs permits building large, high-performance, data storage systems.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: December 11, 2018
    Assignee: LS CLOUD STORAGE TECHNOLOGIES, LLC
    Inventor: Ilya Gertner
  • Patent number: 10148318
    Abstract: A method and a system for communicating personal health data in a Near Field Communication (NFC) environment are provided. An NFC manager sets control information in an NFC Data Exchange Format (NDEF) for providing synchronized communication of personal health data between the NFC manager and an NFC agent. The control information may include a direction flag, a state flag, sequence identifier field, and request/response flag. The NFC manager writes the NDEF format including the control information and payload data into an NFC tag associated with the NFC agent. Subsequently, the NFC manager reads the NDEF record stored in the NFC tag and determines whether the NDEF record is written into the NFC tag by the NFC agent based on the control information in the read NDEF format. Accordingly, the NFC manager repeats the above mentioned steps if the NDEF record includes payload data of the NFC agent.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: December 4, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jayabharath Reddy Badvel, Thenmozhi Arunan, Eun-Tae Won
  • Patent number: 10133641
    Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
  • Patent number: 10126964
    Abstract: Apparatus and method for managing map data in a data storage device. A programmable processor issues a find command to locate and place a requested map page of a map structure into a first cache to service a received host command. A non-programmable hardware circuit searches a forward table to determine whether the requested map page is in a second cache, and if so, loads the map page to the first cache. If not, the hardware circuit requests the requested map page from a back end processor which retrieves the requested map page from a non-volatile memory (NVM), such as a flash memory array. The hardware circuit searches a reverse table and the first cache to select a candidate location in the second cache for the retrieved requested map page from the NVM, and directs the storage of a copy of the requested map page at the candidate location.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: November 13, 2018
    Assignee: Seagate Technology LLC
    Inventors: Jeffrey Munsil, Jackson Ellis, Ryan J. Goss
  • Patent number: 10082968
    Abstract: A data storage system and associated method are provided wherein a policy engine continuously collects qualitative information about a network load to the data storage system in order to dynamically characterize the load and continuously correlates the load characterization to the content of a command queue of transfer requests for writeback commands and host read commands, selectively limiting the content with respect to writeback commands to only those transfer requests for writeback data that are selected on a physical zone basis of a plurality of predefined physical zones of a storage media.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: September 25, 2018
    Assignee: Seagate Technology LLC
    Inventors: Clark Edward Lubbers, Robert Michael Lester