Abstract: An example method is provided to maintain state information of a virtual machine in a virtualized computing environment through a self-triggered approach. The method may comprise detecting, by a first host from a cluster in the virtualized computing environment, that the first host is disconnected from a network connecting the first host to a distributed storage system accessible by the cluster. The method may also comprise suspending, by the first host, a virtual machine supported by the first host and storing state information associated with the virtual machine. The method may further comprise selecting a second host from the cluster and migrating the suspended virtual machine to the second host such that the suspended virtual machine is able to resume from suspension on the second host based on the stored state information.

Abstract: A GPU comprises: a GPR comprising registers; an L1 cache coupled to the GPR and configured to implement a pixel mapping by: segregating pixels of an image into regions, the regions comprise a first region and a second region, the first region comprises first pixels, and the second region comprises second pixels, loading the first pixels into the GPR in a horizontal manner, and loading the second pixels into the GPR in a vertical manner; and an ALU configured to read the first pixels and the second pixels independently of a shared memory.

Abstract: A method for supporting a plurality of requests for access to a data cache memory (“cache”) is disclosed. The method comprises accessing a first set of requests to access the cache, wherein the cache comprises a plurality of blocks. Further, responsive to the first set of requests to access the cache, the method comprises accessing a tag memory that maintains a plurality of copies of tags for each entry in the cache and identifying tags that correspond to individual requests of the first set. The method also comprises performing arbitration in a same clock cycle as the accessing and identifying of tags, wherein the arbitration comprises: (a) identifying a second set of requests to access the cache from the first set, wherein the second set accesses a same block within the cache; and (b) selecting each request from the second set to receive data from the same block.

Abstract: A link controller, method, and data processing platform are provided with dual-protocol capability. The link controller includes a physical layer circuit for providing a data lane over a communication link, a first data link layer controller which operates according to a first protocol, and a second data link layer controller which operates according to a second protocol. A multiplexer/demultiplexer selectively connects both data link layer controllers to the physical layer circuit. A link training and status state machine (LTSSM) selectively controls the physical layer circuit to transmit and receive first training ordered sets over the data lane, and inside the training ordered sets, transmit and receive alternative protocol negotiation information over the data lane. In response to receiving the alternative protocol negotiation information, the LTSSM causes the multiplexer/demultiplexer to selectively connect the physical layer circuit to the second data link layer controller.

Abstract: An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.

Abstract: This application provides a drive circuit of a display device and a driving method for the display device. The display device includes a driver module and a display panel. The drive circuit includes: N single-ended to differential modules, connected to N signal output lines of the driver module and 2N scanning lines of the display panel and connected to a clock signal. Each single-ended to differential module is correspondingly connected to one signal output line and two scanning lines. The N single-ended to differential modules are configured to: output, to the 2N scanning lines according to the clock signal, scanning signals output by the N signal output lines, and charge the 2N scanning lines by using the N signal output lines, where N?1, and N is a positive integer.

Abstract: An example of a system includes a plurality of non-volatile memory dies, a memory bus coupled to the plurality of non-volatile memory dies, and one or more control circuits coupled to the plurality of non-volatile memory dies through the memory bus. The one or more control circuits include a plurality of die-specific request queues configured in a one-to-one correspondence with the plurality of non-volatile memory dies. The one or more control circuits are configured to add die-specific atomic requests to individual die-specific request queues of the plurality of die-specific request queues independently of each other in response to die-specific triggering events.

Abstract: Self-timed processing systems and methods of operating self-timed processing systems are disclosed. A self-timed processing system includes an asynchronous null convention logic (NCL) processor, a memory that accepts input signals on an active edge of a memory clock signal, and logic to combine a first acknowledge signal and a second acknowledge signal to generate the memory clock signal. The first acknowledge signal indicates input signals are ready to be accepted by the memory. The second acknowledge signal indicates data signals previously output from the memory have been accepted by the processor.

Abstract: Embodiments are described for dynamically spawning and/or decommissioning backup proxy nodes in a virtual infrastructure. A backup server can include a polling agent that polls the virtual infrastructure to determine a list of virtual machines whose data is to be backed up, and a list if virtual proxy nodes that facilitate backups of virtual machine data. A proxy map can be generated that describes the mapping of virtual machines to backup proxy nodes in the virtual infrastructure. Rules can be applied to the proxy map to determine whether a new proxy node should be spawned or an existing proxy node should be decommissioned. A new virtual proxy can be generated by accessing a database of preconfigured template virtual proxies to quickly generate the new virtual proxy. One or more virtual machines can be remapped to the newly created virtual proxy to ensure optimal throughput of backup data.

Abstract: A method for executing a computer program, the method implemented by a processor comprising a plural number of computing units and an interconnect connected to the computing units, wherein each computing unit comprises a processing unit and a memory having at least two memory ports, each port assignable to one or more respective regions of the memory, wherein the method comprises at each computing unit: performing an initial step of the program to write: an initial output value to an output region of the memory, and an initial input value to an input region of the memory; and performing a subsequent step of the program by: in a compute phase: assigning one of the two ports to both the input region and the output region; executing code sequences on the processing unit to compute an output set of one or more new output values, and writing the output set to the output region, the output set computed from the initial output and initial input values, each of which is retrieved via said one port in the compute phas

Abstract: A processing apparatus is described. The apparatus includes a plurality of execution threads having a first thread space configuration including a first plurality of rows of execution threads to process data in parallel, wherein each thread in a row is dependent on a top neighbor thread in a preceding row, partition logic to partition the plurality of execution threads into a plurality of banks, wherein each bank includes one or more of the first plurality of rows of execution threads and transform logic to transform the first thread space configuration to a second thread space configuration including a second plurality of rows of execution threads to enable the plurality of execution threads in each of the plurality of banks to operate in parallel.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for accessing non-volatile memory. An apparatus includes one or more memory die. A memory die includes an array of non-volatile memory cells, a set of ports, and an on-die controller. The set of ports includes a first port and a second port. The first port includes a first plurality of electrical contacts and the second port includes a second plurality of electrical contacts. The on-die controller communicates via the set of ports to receive command and address information and to transfer data for a data operation on the array of non-volatile memory cells. The on-die controller uses the first port and the second port in a first mode and uses the first port without the second port in a second mode. The second mode provides compatibility with an interface of a legacy type of memory die.

Abstract: A method of scheduling a system-on-chip (SoC) by a scheduler, located between a plurality of masters and a slave, includes receiving a plurality of access requests from the plurality of masters, setting the plurality of access requests in a plurality of registers, and scheduling the plurality of access requests based on the plurality of access requests.

Abstract: A memory circuit includes a plurality of banks and a controller, each bank of the plurality of banks includes a plurality of segments, and each segment of the plurality of segments includes a plurality of bit lines and a plurality of word lines. A word line switch corresponding to a word line of a segment of the memory circuit is turned on and data are written into memory cells of the segment coupled to a plurality of bit lines of the segment and corresponding to the word line in turn after the controller enables an active command corresponding to the word line. When the controller enables at least one copy row write command, the data are simultaneously written into memory cells sharing a plurality of sense amplifiers with the plurality of bit lines of the segment and corresponding to at least one another word line.

Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

Abstract: Memory devices and systems in which array data lines of a local data bus are shared between two or more memory bank groups in a memory array. In one embodiment, a memory device is provided, comprising a memory array, I/O gating circuitry, and a local data bus. The local data bus can include a plurality of array data lines shared between two or more memory bank groups of the memory array. The local data bus can electrically couple and transfer data between the two or more memory bank groups and the I/O gating circuitry. In some embodiments, one or more data latches can be electrically coupled to the local data bus to (i) transfer data off the local data bus to free the plurality of data lines for subsequent data transfers and/or (ii) match varying data propagation timings on the local data with column generations of the memory bank groups.

Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.

Abstract: A computing system is configured to maintain equivalency of independent queues located in different coupling facilities. The computer system includes a first coupling facility and a second coupling facility. The first coupling facility receives a plurality of different commands instructing the first coupling facility to load data into a first structure. The first coupling facility generates a first command data block including first data corresponding to a received first command and a first sequence value indicating a sequence at which the first data was loaded into the first structure with respect to remaining data corresponding to the plurality of commands. A second coupling facility includes a second structure and a second queue. The second coupling facility receives the first command data block from a first queue of the first coupling facility and loads the first data from the second queue into the second structure based on the first sequence value.

Abstract: A system includes a cut-through bridge including a plurality of stages within a controller for communication packet transmission to transfer data and one or more control signals successively between the stages. The system also includes a control signal interceptor within the controller operable to intercept control signals between a first stage and a second stage of the cut-through bridge. The control signal interceptor is further operable to generate a forced valid control signal for each of the control signals regardless of an error condition of the control signals. The control signal interceptor outputs the forced valid control signal for each of the control signals to the second stage of the cut-through bridge. The forced valid control signal for each of the control signals is propagated through one or more successive stages of the cut-through bridge to an end stage to prevent an invalid state at the end stage.

Abstract: Systems, methods, and instrumentalities are disclosed for escape color coding for palette coding mode. A video bitstream may be received. The video bitstream may comprise a quantization parameter (QP) and/or a quantized escape color value that corresponds to an escape color pixel. A scaled escape color value may be generated by scaling the quantized escape color value by a scaling factor. A left-shift parameter may be determined based on the QP. A left-shifted escape color value may be generated by left-shifting the scaled escape color value based on the left-shift parameter. A right-shifted escape color value may be generated by right-shifting the left-shifted escape color value based on a constant parameter. A reconstructed escape color value may be determined based on the right-shifted escape color value. The device may decode the video bitstream based on the reconstructed escape color value.

Abstract: A multi-port memory device in communication with a controller includes a memory array for storing data provided by the controller, a first port coupled to the controller via a first controller channel, a second port coupled to the controller via a second controller channel, a processor, and a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to: enable data transfer through the first port and/or the second port in response to a first control signal received from the first controller channel and/or a second control signal received from second controller channel, decode at least one of the received first and second control signals to identify a data operation to perform, the identified data operation including a read or write operation from or to the memory array, and execute the identified data operation.

Abstract: A method of request scheduling in a computing environment comprises the following steps. One or more requests to at least one of read data from and write data to one or more storage devices in the computing environment are obtained from a host device. The one or more requests are aligned corresponding to a segment size for which one or more data services in the computing environment are configured to process data. The one or more aligned requests are dispatched to the one or more data services prior to sending the one or more requests to the one or more storage devices.

Abstract: The present disclosure relates to a structure which includes a dual write bit switch device which includes a plurality of bit switch devices positioned at different positions of a memory cell array, and which is configured to enable write operations at a specified number of cells per bit line of the memory cell array.

Abstract: A memory device may include one or more memory banks that store digital data. The memory device includes first tri-state driver circuitry that provides a first signal to a first data read/write (DRW) line coupled between write driver circuitry and one or more DQ pads. The first signal is indicative of either a high state or a medium state. The memory device includes second tri-state driver circuitry that provides a second signal to a second data read/write (DRW) line coupled between the write driver circuitry and the one or more DQ pads. The second signal is indicative of either a medium state or a low state. A voltage level of the medium state is between a voltage level of the high state and a voltage level of the low state.

Abstract: A graphics processing unit is disclosed, the graphics processing unit having a processor having one or more SIMD processing units, and a local data share corresponding to one of the one or more SIMD processing units, the local data share comprising one or more low latency accessible memory regions for each group of threads assigned to one or more execution wavefronts, and a global data share comprising one or more low latency memory regions for each group of threads.

Abstract: A semiconductor memory device includes first and second memory cell arrays, and first and second control circuits configured to execute an operation on the first and second memory cell arrays. The first control circuit executes an operation on the first memory cell array responsive to a first command set that is received by the semiconductor memory device. The second control circuit executes an operation on the second memory cell array responsive to second and third command sets that are received by the semiconductor memory device while the first control circuit is executing the operation on the first memory cell array.

Abstract: An electronic apparatus may be provided that includes a processor to perform operations, and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme. Each memory bank may include at least two elements per bank word.

Abstract: A memory-control integrated circuit includes internal data conductors, steering circuitry and distinct first and second data interfaces, the first data interface having twice as many input/output (I/O) transceivers as the second data interface. In a first memory system configuration in which only the first data interface is coupled to a memory module, the steering circuitry couples all the internal data conductors exclusively to the I/O transceivers of the first data interface. In a second memory system configuration in which the first and second data interfaces are coupled to respective memory modules, the steering circuitry couples a first half of the internal data conductors exclusively to the I/O transceivers of the second data interface while a second half of the internal data conductors remains exclusively coupled to half the I/O transceivers of the first data interface.

Abstract: A memory system may include: a memory device including a plurality of pages having a plurality of memory cells coupled to a plurality of word lines and suitable for storing read data and write data requested from a host, a plurality of memory blocks each including the pages, a plurality of planes each including the memory blocks, and a plurality of memory chips each including the planes; and a controller suitable for searching map data of the read data corresponding to a read command received from the host on a basis of a plurality of segments, triggering memory chips corresponding to the map data searched through the searches of the respective segments, reading data stored in the triggered memory chips, and transferring the read data to the host.

Abstract: A method for decentralized resource allocation in an integrated circuit. The method includes receiving a plurality of requests from a plurality of resource consumers of a plurality of partitionable engines to access a plurality resources, wherein the resources are spread across the plurality of engines and are accessed via a global interconnect structure. At each resource, a number of requests for access to said each resource are added. At said each resource, the number of requests are compared against a threshold limiter. At said each resource, a subsequent request that is received that exceeds the threshold limiter is canceled. Subsequently, requests that are not canceled within a current clock cycle are implemented.

Abstract: A process control system coordinates with an associated asset management system to implement a plant safety mechanism and, in particular, to prevent unintended changes to, or otherwise undesired operation of, one or more process control equipment resources in a process plant. A maintenance technician uses the asset management system to request access to one or more of the process control equipment resources. A process operator receives the request via the process control system and grants or denies the request. Process control equipment resources for which a process operator grants a request are inoperable, in part or in whole, by the process control system. Upon completion of the maintenance task, the maintenance technician requests to return control of the process control equipment resource to the process operator. The return is complete when the process operator acknowledges the return of the resource to the process control system.

Abstract: One or more techniques and/or systems are provided for dynamic data access configuration. For example, a mapping may be maintained for compute nodes of a distributed processing system. The mapping may comprise access permission assignments of at least some compute nodes to shared data segments (e.g., read access and/or write access permissions). The mapping may be updated based upon configuration changes for the distributed processing system (e.g., addition of a new compute node, failure of a compute node, granting or removal of access to a shared data segment for an existing compute node, etc.). The updated mapping may be applied to the distributed processing system during operation of the distributed processing system (e.g., access may be granted to original instances of shared data segments based upon the configuration change; compute nodes and/or the distributed processing system may be kept online and operational while applying the configuration change; etc.).

Abstract: A memory device can be used with a shared routing resource that provides access to the memory device. The memory device can include a random access memory (RAM) circuit that includes a plurality of ports configured to provide access to the RAM circuit by the shared routing resource. A memory partition register circuit can be configured to store a plurality of addresses specifying respective context partitions within the RAM circuit. A plurality of pointer register circuits that can each be associated with a corresponding port of the plurality of ports and can be configured to store a respective set of pointers that specify a location in the RAM circuit relative to a respective context partition. Addressing logic that can be configured to provide access to the RAM circuit using the respective set of pointers for each port.

Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

Abstract: A system and method for optimizing a system design that includes two or more components, where at least one component is to be implemented using a constrained resource. From an initial schedule, the resource having a longest span time between a start busy time slot and an end busy time slot is identified. The schedule for the other resources is then also extended to the span time. The resulting design can be made synchronous by inserting up-sampler and down-sampler function blocks before and after any strongly connected components.

Abstract: A link layer of a serial protocol is modified to perform early primitive detection. An early primitive detector unit compares an undecoded bit sequence to that corresponding to a particular primitive. A primitive notification is generated in response to identifying a match. Latency is reduced compared with performing link layer decoding and then identifying primitives.

Abstract: A memory appliance system is described and includes a plurality of memory devices storing data in a plurality of containers and a controller. The containers include metadata, relationship information associating a respective container with related containers, and a payload. The controller is configured to perform data operations on the payload of one of the containers, and based on the relationship information associating the respective container with related containers and the payload of related containers.

Abstract: In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory controller that includes a logic circuit configured to generate a select signal for selecting between first and second ports of a memory as a function of first and second port signals. Additionally, the memory controller includes a switch configured to connect and disconnect the first and the second port signals. In another aspect of the disclosure, the apparatus is a storage apparatus that includes a memory and a memory controller. The memory controller includes a latch configured to latch a first port selection signal to produce a first port signal and latch a second port selection signal to produce a second port signal. The memory controller also includes a switch configured to connect and disconnect the first and the second port signals and a logic circuit configured to generate a select signal.

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

Abstract: The method includes, at a first clock cycle:—obtaining (202) new requests by the processing stage;—supplying (210) by the processing stage at least one of the new requests;—placing on standby (212) by the processing stage at least one further new request, hereinafter referred to as a standby request. The method further includes, at a second clock cycle following the first clock cycle:—obtaining (202) at least one new request by the processing stage;—selecting (208) by the processing stage, from the standby request(s) and the new request(s), at least one request;—la supplying (210) the selected request(s) by the processing stage.

Abstract: For efficient reclamation of pre-allocated direct memory access (DMA) memory in a computing environment, hot-add random access memory (RAM) is emulated for a general purpose use by reclamation of pre-allocated DMA memory reserved at boot time for responding to an emergency by notifying a non-kernel use device user that the non-kernel use device has a smaller window, stopping and remapping to the smaller window, and notifying a kernel that new memory has been added, wherein the new memory is a region left after the remap.

Abstract: Disclosed in some examples is an improved computing architecture, which includes multiple processor cores and I/O devices communicating with multiple memory banks using a High Speed Interconnect Unit (HSU). The HSU quickly routes (e.g., in one clock cycle) a memory access request from an I/O device or a processor core to a particular memory bank over one of a number of independent memory routes, each memory route servicing a particular memory bank. The routing is based upon the values of preselected bit positions (“preselected bits”) in the requested memory address, the preselected bits being chosen so as to maximize the distribution of memory accesses of the entire system across all available memory banks (and by extension distributing the memory accesses across the available memory routes).

Abstract: A storage device includes a memory controller suitable for outputting a program command or a read command; and a memory device suitable for performing a program operation in response to the program command, and immediately performing a read operation when the read command is received during the program operation.

Abstract: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Abstract: A register file device includes: a multi-port latch; and a write circuit that generates a signal to be written in the multi-port latch, the write circuit generating the signal on the basis of a plurality of data groups each including a write control signal, a write address, and a piece of write data, wherein the write circuit includes: a detection circuit that detects at least two write control signals occurred simultaneously among write control signals, and a changing circuit that changes write data corresponding to one of the write control signal to become same as write data corresponding to another of the write control signal.

Abstract: A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.

Abstract: A method for managing a request for an outbound connection is provided. The method includes the step of receiving the request for the outbound connection. The request includes a specified connection speed. The method also includes the step of comparing the request for the outbound connection to a plurality of outbound connection options. A further step of the method includes selecting an outbound connection from the plurality of outbound connection options. The selected outbound connection has a connection speed at least equal to the specified connection speed. The selected outbound connection also has the lowest connection speed of the outbound connection options having a connection speed at least equal to the specified connection speed.

Abstract: In a method relating generally to starting a plurality of transmitters, a sequence is initiated for each of the plurality of transmitters having corresponding data buffers. Latency is set for each of the data buffers responsive to execution of the sequence. The sequence includes: obtaining a read address associated with a read clock signal; obtaining a write address associated with a write clock signal; determining a difference between the read address and the write address; asserting a flag signal associated with the difference; and adjusting the read clock signal to change the difference to locate a change of state location for the flag signal to set the latency for a data buffer of the data buffers.

Abstract: A data processor includes a memory accessing agent and a memory controller. The memory accessing agent generates a plurality of accesses to a memory. The memory controller is coupled to the memory accessing agent and schedules the plurality of memory accesses in an order based on characteristics of the memory. The characteristics of the memory include a row cycle page time (tRCPAGE) indicative of an acceptable number of activate commands to a row in the memory within a predetermined time window.

Abstract: A controller as an embodiment of the present disclosure controls a timing of transmitting an access request that has been received from an initiator (or its transmission interval). The controller includes: transmitting and receiving circuitry configured to receive an access request related to burst accesses from a first initiator that is connected via a first bus to, and adjacent to, the transmitting and receiving circuitry and configured to transmit the access request to a second bus implemented as a network; and a transmission interval controller configured to control the timing of transmitting the access request that has been received from the first initiator according to density of the burst accesses during a period in which the burst accesses continue and an access load on the second bus.