Multiport Memory Patents (Class 711/149)
  • Publication number: 20150032975
    Abstract: A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.
    Type: Application
    Filed: October 16, 2014
    Publication date: January 29, 2015
    Inventors: Alan Ruberg, Seung-Jong Lee, Hyung Rok Lee, Daeyun Shim, Dongyun Lee, Sungjoon Kim, Anu Murthy
  • Publication number: 20150026397
    Abstract: Exemplary embodiments include a memory module including a plurality of connectors, at least one memory, at least one transmitter and at least one receiver. The connectors are configured to fit with a form factor of a memory socket on a server board. The memory is coupled with the connectors. The transmitter(s) are coupled with the memory. The transmitter(s) are configured to send a first plurality of signals from the memory module such that the first plurality of signals bypass the connectors. The receiver(s) are coupled with the memory. The receiver(s) are configured to receive a second plurality of signals to the memory module such that the second plurality of signals bypass the plurality of connectors.
    Type: Application
    Filed: November 21, 2013
    Publication date: January 22, 2015
    Applicant: Samsung Electronics, Ltd.
    Inventor: Zhan (John) Ping
  • Publication number: 20150026418
    Abstract: A system and method for serial interface topologies is disclosed. A serial interface topology includes a replication device configured to receive control information from a controller interface. The replication device is configured to transmit two or more copies of substantially replicated control information to a device control interface. A data interface is configured to provide differential, point-to-point communication of data with the device controller interface.
    Type: Application
    Filed: October 7, 2014
    Publication date: January 22, 2015
    Inventor: William F. Sauber
  • Patent number: 8937965
    Abstract: A switch unit, which is connected to one or more computers and one or more storage systems, comprises an update function for updating transfer management information (a routing table, for example). The storage system has a function for adding a virtual port to a physical port. The storage system migrates the virtual port addition destination from a first physical port to a second physical port and transmits a request of a predetermined type which includes identification information on the virtual port of the migration target to the switch unit. The transfer management information is updated by the update function of the switch unit so that the transfer destination which corresponds with the migration target virtual port is the switch port connected to the second physical port.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: January 20, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Norio Shimozono, Shintaro Ito
  • Patent number: 8935486
    Abstract: Memory access in a digital signal processing system is described. In one example, the digital signal processing system comprises a multi-port memory that is constructed from a memory interface connected to a number of single-port memory devices. The memory interface provides access ports that processors can use to access data stored on the single-port memory devices using a single address space. A processor can be connected to several access ports, and use these to request access to data at several different memory addresses at the same time. The digital signal processing system is configured such that the total number of single-port memory devices connected to the memory interface is a prime number greater than or equal to three. Because a prime number of memory devices are used, the likelihood of the data for the different memory addresses being on the same single-port memory device is minimised, increasing memory access speed.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: January 13, 2015
    Assignee: Imagination Technologies, Limited
    Inventors: Adrian John Anderson, Gary Christopher Wass
  • Patent number: 8930641
    Abstract: An integrated circuit may have a memory controller that interfaces between master processing modules and system memory. A scheduling module may be used to handle memory access requests received from multiple master modules. The scheduling module may arrange the received memory access requests in an order for fulfillment with system memory. A bypass module may be used to provide a low latency bypass path that allows memory access requests to bypass the scheduling module. The bypass module may include an eligibility detection module that identifies memory access requests eligible for scheduler bypassing, a port selection module that provides a low latency bypass path for the eligible memory access requests, multiplexing circuitry that selects between memory access requests provided from the low latency bypass path and from the output of the scheduling module, and a masking module that prevents redundant fulfillment of memory access requests.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: January 6, 2015
    Assignee: Altera Corporation
    Inventors: Ravish Kapasi, Jeffrey Schulz, Ching-Chi Chang, Caroline Ssu-Min Chen
  • Patent number: 8930595
    Abstract: Described is a data switching device comprising a plurality of input ports, a plurality of output ports, a plurality of first conductive connectors, a plurality of second conductive connectors, a plurality of crosspoint regions, and a memory device at each crosspoint region. The first conductive connectors are in communication with the input ports. The second conductive connectors are in communication with the output ports. Each crosspoint region includes a first conductive connector and a second conductive connector. The memory device is coupled between the first conductive connector and the second conductive connector for exchanging data between the input ports and the output ports.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: January 6, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventor: David E. Mayhew
  • Patent number: 8930642
    Abstract: Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of which are non-native to each port. The memory device may include a configuration register that stores configuration data indicative of the mapping of the memory banks to the ports. In response to the configuration data, for example, a steering logic may couple each of the ports either to one or all of the native memory banks or to one or all of the non-native memory banks.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: January 6, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Robert Walker, Dan Skinner
  • Patent number: 8930643
    Abstract: Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: January 6, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Dan Skinner, J. Thomas Pawlowski
  • Patent number: 8918594
    Abstract: Apparatus and methods disclose techniques to control access to a memory array. The memory array can be accessed by either a first interface or a second interface. A switch register grants privilege levels, which control access. For example, a high privilege level can grant access and a low privilege level can deny access. A status register indicates when an interface with a high privilege level is busy accessing the memory array.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: December 23, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Giulio Albini, Emanuele Confalonieri, Francesco Mastroianni
  • Patent number: 8918615
    Abstract: An embodiment of this invention is an information storage system comprising a plurality of storage systems connected to be able to communicate. Each of the plurality of storage systems includes default storage system identification information which is the same to the plurality of storage systems, common volume identification information for uniquely identifying volumes provided by the plurality of storage systems to a host computer among the plurality of storage systems, and a controller configured to return the default storage system identification information to the host computer in response to a request from the host computer and to process a read or write request to a volume accompanying the common volume identification information from the host computer.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: December 23, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Akihisa Nagami, Koh Nakamichi, Yasunori Kaneda, Hirokazu Ikeda, Masayuki Yamamoto
  • Patent number: 8914649
    Abstract: A computing device (101, 400, 500) has a processor (401) and at least one peripheral device port (106, 107, 108, 109, 410-1 to 410-5). The processor (401) is configured to selectively power the at least one peripheral device port (106, 107, 108, 109, 410-1 to 410-5) when the processor (401) is in a sleep state (302, 303, 304, 305, 306) according to at least one setting stored by firmware (405) of the processor (401).
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: December 16, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chi W. So, Binh T. Truong, Luke Mulcahy
  • Publication number: 20140359199
    Abstract: A multi-processor computer architecture incorporating distributed multi-ported common memory modules wherein each of the memory modules comprises a control block functioning as a cross-bar router in conjunction with one or more associated memory banks or other data storage devices. Each memory module has multiple I/O ports and the ability to relay requests to other memory modules if the desired memory location is not found on the first module. A computer system in accordance with the invention may comprise memory module cards along with processor cards interconnected using a baseboard or backplane having a toroidal interconnect architecture between the cards.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Applicant: SRC Computers, LLC.
    Inventors: Jon M. Huppenthal, Timothy J. Tewalt, Lee A. Burton, David E. Caliga
  • Publication number: 20140351526
    Abstract: Techniques are disclosed relating to processing data in a storage controller. In one embodiment, a method includes receiving data at a storage controller of a storage device. The method further includes processing data units of the data in parallel via a plurality of write pipelines in the storage controller. The method further includes writing the data units to a storage medium of the storage device. In some embodiments, the method may include inserting header information into the data for a plurality of data units before processing, and the header information may include sequence information. In some embodiments, writing the data units may include writing according to a sequence determined prior to processing the data units.
    Type: Application
    Filed: April 16, 2014
    Publication date: November 27, 2014
    Applicant: Fusion-io, Inc.
    Inventor: James G. Peterson
  • Patent number: 8892825
    Abstract: A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: November 18, 2014
    Assignee: Silicon Image, Inc.
    Inventors: Alan Ruberg, Seung-jong Lee, Hyung Rok Lee, Daeyun Shim, Dongyun Lee, Sungjoon Kim, Anu Murthy
  • Patent number: 8878860
    Abstract: An embodiment of the present invention is a technique to control memory access. An address pre-swizzle circuit conditions address bits provided by a processor according to access control signals. A data steering circuit connects to N sub-channels of memory to dynamically steer data for a memory access type including tiled and untiled memory accesses according to the access control signals, the conditioned address bits, and sub-channel identifiers associated with the N sub-channels. The tiled memory access includes horizontally and vertically tiled memory accesses. An address post-swizzle circuit generates sub-channel address bits to the N sub-channels using the conditioned address bits and according to the access control signals and the sub-channel identifiers.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: November 4, 2014
    Assignee: Intel Corporation
    Inventors: James Akiyama, William H. Clifford
  • Patent number: 8880812
    Abstract: A serial attached small computer systems interface (SAS) module includes a first port with (i) a first physical layer device and (ii) a first port control module. The first physical layer device communicates with a plurality of initiators. The first port control module comprises a first world wide number (WWN) table. The first WWN table comprises connection rates of the plurality of initiators during communication with the first physical layer device. Each of the connection rates is a last connection rate of a respective one of the plurality of initiators.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: November 4, 2014
    Assignee: Marvell International Ltd.
    Inventors: James A. Walch, Leon A. Krantz
  • Publication number: 20140310482
    Abstract: A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by storing a second encoded copy of data in a multi-port XOR memory bank.
    Type: Application
    Filed: August 5, 2013
    Publication date: October 16, 2014
    Applicant: Memoir Systems, Inc.
    Inventors: Sundar Iyer, Shang-Tse Chuang
  • Patent number: 8862831
    Abstract: A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: October 14, 2014
    Assignee: Intel Corporation
    Inventors: Yang Ni, Rajkishore Barik, Ali-Reza Adl-Tabatabai, Tatiana Shpeisman, Jayanth N. Rao, Ben J. Ashbaugh, Tomasz Janczak
  • Patent number: 8856491
    Abstract: A computing device is provided and includes a memory module, a sweep engine, a root snapshot module, and a trace engine. The memory module has a memory implemented as at least one hardware circuit. The memory module uses a dual-ported memory configuration. The sweep engine includes a stack pointer. The sweep engine is configured to send a garbage collection signal if the stack pointer falls below a specified level. The sweep engine is in communication with the memory module to reclaim memory. The root snapshot engine is configured to take a snapshot of roots from at least one mutator if the garbage collection signal is received from the sweep engine. The trace engine receives roots from the root snapshot engine and is in communication with the memory module to receive data.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: David F. Bacon, Perry S. Cheng, Sunil K. Shukla
  • Patent number: 8856262
    Abstract: Data including information regarding a display of the host device may be received. A display of a client device may correspond to the display of the host device. Information regarding the display of the host device may be received and evaluated identify the images in the display. The identified images may be stored in memory and associated with a uniform resource locator (URL). A bitstream describing the display may be generated in which each image is referenced using the associated URL. The bitstream may then be provided to a client device, where rendering of the bitstream results in a display corresponding to the host device. Rendering the display may include retrieving the images associated with the URLs in the bitstream.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: October 7, 2014
    Assignee: hopTo Inc.
    Inventor: Eldad Eilam
  • Patent number: 8850128
    Abstract: A method for implementing data storage and a dual port, dual element storage device are provided. A storage device includes a predefined form factor including a first port and a second port, and a first storage element and a second storage element. A controller coupled between the first port and second port, and the first storage element and second storage element controls access and provides two separate data paths to the first storage element and second storage element.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: September 30, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Frank R. Chu, Spencer W. Ng, Motoyasu Tsunoda, Marco Sanvido
  • Publication number: 20140289482
    Abstract: Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.
    Type: Application
    Filed: June 9, 2014
    Publication date: September 25, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Dan Skinner, J. Thomas Pawlowski
  • Publication number: 20140281283
    Abstract: Efficient techniques using a multi-port shared non-volatile memory are described that reduce latency in memory accesses from dedicated function specific processors, such as a modem control processor. The modem processor preempts a host processor that is accessing data from a multi-port shared non-volatile memory flash device allowing the modem processor to quickly access data in the flash device. The preemption process uses a doorbell interrupt initiated by a processor that seeks access and interrupts the processor being preempted. After preemption, the host processor may resume or restart the data access. Access control by the processors utilizes a hardware semaphore atomic control mechanism. Power control of the shared non-volatile memory modules includes at least one inactivity timer to indicate when a supply voltage to the shared non-volatile memory modules can be safely reduced or turned off. Power may be restarted by any of the processors sharing the memory, allowing fast access to the data.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Assaf Shacham, Amit Gil, Erez Tsidon, Yanru Li, Azzedine Touzni
  • Publication number: 20140281285
    Abstract: A register file device includes: a multi-port latch; and a write circuit that generates a signal to be written in the multi-port latch, the write circuit generating the signal on the basis of a plurality of data groups each including a write control signal, a write address, and a piece of write data, wherein the write circuit includes: a detection circuit that detects at least two write control signals occurred simultaneously among write control signals, and a changing circuit that changes write data corresponding to one of the write control signal to become same as write data corresponding to another of the write control signal.
    Type: Application
    Filed: January 29, 2014
    Publication date: September 18, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Tomohiro Tanaka
  • Publication number: 20140281284
    Abstract: A method includes receiving a multi-port read request for retrieval of data stored in three memories, each comprising two memory modules and a parity module. The multi-port read request is associated with first data stored at a first memory address, second data stored at a second memory address, and third data stored at a third memory address. When the first memory address, the second memory address, and the third memory address are associated with a first memory module, first data is retrieved from the first memory module, second data is reconstructed using data from a second memory module and a first parity module, and third data is reconstructed using data from a fourth memory module and a seventh memory module. The first data, the second data, and the third data are provided in response to the multi-port read request.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Stefan G. Block, Ting Zhou, Mikhail I. Grinchuk, Anatoli A. Bolotov, Lav D. Ivanovic
  • Publication number: 20140281114
    Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.
    Type: Application
    Filed: February 18, 2014
    Publication date: September 18, 2014
    Applicant: Synopsys, Inc.
    Inventor: David Latta
  • Publication number: 20140258644
    Abstract: A transactional memory (TM) receives an Atomic Metering Command (AMC) across a bus from a processor. The command includes a memory address and a meter pair indicator value. In response to the AMC, the TM pulls an input value (IV). The TM uses the memory address to read a word including multiple credit values from a memory unit. Circuitry within the TM selects a pair of credit values, subtracts the IV from each of the pair of credit values thereby generating a pair of decremented credit values, compares the pair of decremented credit values with a threshold value, respectively, thereby generating a pair of indicator values, performs a lookup based upon the pair of indicator values and the meter pair indicator value, and outputs a selector value and a result value that represents a meter color. The selector value determines the credit values written back to the memory unit.
    Type: Application
    Filed: May 24, 2014
    Publication date: September 11, 2014
    Applicant: Netronome Systems, Inc.
    Inventor: Gavin J. Stark
  • Patent number: 8832388
    Abstract: A technology can be provided for managing shared memory used by a plurality of compute nodes. An example system can include a shared globally addressable memory to enable access to shared data by the plurality of compute nodes. A memory interface can process memory requests sent to the shared globally addressable memory from the plurality of processors. A memory write module can be included for the memory interface to allocate memory locations in the shared globally addressable memory and write read-only data to the globally addressable memory from a writing compute node. In addition, a read module for the memory interface can map read-only data in the globally addressable shared memory as read-only for subsequent accesses by the plurality of compute nodes.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: September 9, 2014
    Assignee: Microsoft Corporation
    Inventors: Jonathan Ross, Jork Loeser
  • Patent number: 8825632
    Abstract: A method of interrogation or modification of a database having a plurality of tables each with fields and relationships between the fields of various tables, the method including: filling in a single privileged table; filling in at least one field in another table for which data are sought or to be modified; filling in at least one filter pertaining to a field of another table allowing the selection of the data sought or to be modified; identifying in the database, using the input fields and the fields appearing in the input filters, the tables containing these fields; identifying in the database, using the input fields and the fields appearing in the input filters, the relationships between these fields of various tables; reformulating a query to the database by stating in full the fields, the identified tables, joins representative; and applying the query to the database.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: September 2, 2014
    Inventors: Marc Vogel, Dan Vogel
  • Patent number: 8825966
    Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface are some operations performed by the controller. The controller determines a width for a Data bus while assigning a target device address to each of the memory devices.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: September 2, 2014
    Assignee: MOSAID Technologies Incorporated
    Inventor: Peter Gillingham
  • Patent number: 8806150
    Abstract: A computer system in which one or more host computers 30 having a FC (Fiber Channel) node port and one or more storage apparatuses 40 having a FC node port are coupled via a FC fabric. The storage apparatus acquires first information related to access control for controlling access to a relevant storage apparatus by the host computer. The storage apparatus, based on the first information, creates second information for defining the host computer that is able to access the relevant storage apparatus, and registers this second information in the fabric.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: August 12, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Akio Nakajima
  • Publication number: 20140215164
    Abstract: The present disclosure describes techniques and apparatuses for multiport memory architecture. In some aspects serial data is received from a data port and converted to n-bit-wide words of data. The n-bit-wide words of data are then buffered as a k-word-long block of parallel data into a line of a multiline buffer as a block of k*n bits of data. The block of k*n bits of data is then transmitted to a multiport memory via a write bus effective to write the block of k*n bits of data to the multiport memory.
    Type: Application
    Filed: March 31, 2014
    Publication date: July 31, 2014
    Applicant: Marvell World Trade Ltd.
    Inventors: Winston Lee, Sehat Sutardja, Donald Pannell
  • Patent number: 8782350
    Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: July 15, 2014
    Assignee: Netlist, Inc.
    Inventors: Hyun Lee, Jayesh R. Bhakta, Jeffrey C. Solomon, Mario Jesus Martinez, Chi-She Chen
  • Patent number: 8782646
    Abstract: In a NUMA-topology computer system that includes multiple nodes and multiple logical partitions, some of which may be dedicated and others of which are shared, NUMA optimizations are enabled in shared logical partitions. This is done by specifying a home node parameter in each virtual processor assigned to a logical partition. When a task is created by an operating system in a shared logical partition, a home node is assigned to the task, and the operating system attempts to assign the task to a virtual processor that has a home node that matches the home node for the task. The partition manager then attempts to assign virtual processors to their corresponding home nodes. If this can be done, NUMA optimizations may be performed without the risk of reducing the performance of the shared logical partition.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: July 15, 2014
    Assignee: International Business Machnies Corporation
    Inventors: Vaijayanthimala K. Anand, Mark R. Funk, Steven R. Kunkel, Mysore S. Srinivas, Randal C. Swanberg, Ronald D. Young
  • Patent number: 8775744
    Abstract: A switching frame buffer is described in which data units within a sequence of time slots, of a frame, may be simultaneously input and output at ports of the switching frame buffer. In one implementation, a write port may receive data units within a single cycle of the switch. A number of memories may be provided, where first selected ones of the memories constitute memory groups and second selected ones of the memories constitute a memory subsets, each of the memory groups including a corresponding one of the memory subsets. The write port may supply each of a number of copies of the data units to a corresponding one of the memory subsets. Multiplexers may be associated with the groups of the memories and a read port may receive one of the copies of a number of the data units from different ones of the multiplexers.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: July 8, 2014
    Inventors: Chung Kuang Chin, Shankar Venkataraman, Swaroop Raghunatha
  • Patent number: 8769213
    Abstract: Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: July 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Dan Skinner, J. Thomas Pawlowski
  • Patent number: 8769214
    Abstract: A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: July 1, 2014
    Assignee: QST Holdings LLC
    Inventors: Frederick Curtis Furtek, Paul L. Master
  • Patent number: 8762653
    Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: June 24, 2014
    Assignee: Apple Inc.
    Inventors: Sukalpa Biswas, Hao Chen, Ruchi Wadhawan
  • Patent number: 8762620
    Abstract: A storage controller containing multiple processors. The processors are divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In one embodiment, the storage controller operates with a flash memory module, and includes multiple parallel pipelines that allow plural host commands to be handled simultaneously.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: June 24, 2014
    Assignee: Sandisk Enterprise IP LLC
    Inventors: Douglas A. Prins, Aaron K. Olbrich
  • Publication number: 20140164673
    Abstract: A memory controller connected with a storage medium via a plurality of channels is provided which includes a signal processing block including a plurality of signal processing engines; and a decoding scheduler configured to control a data path such that at least one activated signal processing engine of the plurality of signal processing engines is connected with the plurality of channels, respectively.
    Type: Application
    Filed: December 11, 2013
    Publication date: June 12, 2014
    Inventors: Seonghoon WOO, Haksun KIM, Euihyeok KWON, Jaegeun PARK
  • Patent number: 8745335
    Abstract: Memory arbiter with latency guarantees for multiple ports. A method of controlling access to an electronic memory includes measuring a latency value indicative of a time difference between origination of an access request from a port of a plurality of ports and a response from the electronic memory. The method also includes calculating a difference between the latency value for the port and a target value associated with the port. The method further includes calculating a running sum of differences for the port covering each of a plurality of access requests. Further, the method includes determining a delta of a priority value for the port based on the running sum of differences. Moreover, the method includes prioritizing the access by the plurality of ports according to associated priority values.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: June 3, 2014
    Assignee: Synopsys, Inc.
    Inventors: Pieter Van Der Wolf, Marc Jeroen Geuzebroek, Johannes Boonstra
  • Publication number: 20140149631
    Abstract: A memory module includes memory devices arranged in ranks and columns and designated in first and second groupings, the first grouping includes memory devices arranged in only a first rank nearest a memory controller and directly connected to the memory controller, the memory devices in the second grouping are indirectly connected to the memory controller via a corresponding memory device in the first grouping arranged in a same column, and each memory device selectively provides either self-data retrieved from a constituent memory core or other-data retrieved from a memory core of another memory device during the read operation.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 29, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JEONG-KYOUM KIM, IN-DAL SONG, JUNG-HWAN CHOI
  • Publication number: 20140143511
    Abstract: An interface conversion device, applicable to a storage device, includes a first connection port, a second connection port, a measuring unit and a processing unit. The first connection port transmits a first signal and a power signal via a first communication interface. The second connection port transmits a second signal and the power signal to the storage device via a second communication interface. The first communication interface and the second communication interface are different from each other. The measuring unit receives the power signal from the first connection port to measure the power signal and produce a measurement signal. The measuring unit outputs the power signal to the second connection port. The processing unit receives and converts the first signal into the second signal and outputs the second signal via the second connection port. The processing unit receives the measurement signal to calculate a power consumption value.
    Type: Application
    Filed: March 18, 2013
    Publication date: May 22, 2014
    Applicants: INVENTEC CORPORATION, INVENTEC (PUDONG) TECHNOLOGY CORPORATION
    Inventors: Ying-Fan Chiang, Chun-Hao Chu, Chun-Yuan Chen
  • Patent number: 8732384
    Abstract: A device and methods are provided for accessing memory. In one embodiment, a method includes receiving a request for data stored in a device, checking a local memory for data based on the request to determine if one or more blocks of data associated with the request are stored in the local memory, and generating a memory access request for one or more blocks of data stored in a memory of the device based when one or more blocks of data are not stored in the local memory. In one embodiment, data stored in memory of the device may be arranged in a configuration to include a plurality of memory access units each having adjacent lines of pixel data to define a single line of memory within the memory access units. Memory access units may be configured based on memory type and may reduce the number of undesired pixels read.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: May 20, 2014
    Assignee: CSR Technology Inc.
    Inventors: Eran Scharam, Costia Parfenyev, Liron Ain-Kedem, Ophir Turbovich, Tuval Berler
  • Patent number: 8732400
    Abstract: Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: May 20, 2014
    Assignee: ARM Limited
    Inventors: Peter Andrew Riocreux, Bruce James Mathewson, Christopher William Laycock, Richard Roy Grisenthwaite
  • Patent number: 8726064
    Abstract: An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.
    Type: Grant
    Filed: April 17, 2006
    Date of Patent: May 13, 2014
    Assignee: Violin Memory Inc.
    Inventor: Jon C. R. Bennett
  • Patent number: 8711652
    Abstract: A plurality of masters arbitrate for access to a shared memory device, such as a SDRAM (synchronous dynamic random access memory), amongst themselves using software and arbitration interfaces. The masters generate additional commands upon arbitration, such as MRS and PALL commands, for prevention of collision of commands, refresh starvation, and/or a missing pre-charge operation in the shared memory device.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Min Lee, Sung-Jae Byun, Han-Gu Sohn, Gyoo-Cheol Hwang
  • Publication number: 20140115277
    Abstract: Exemplary embodiments provide a technique to offload storage workload. In one aspect, a computer comprises: a memory; and a controller operable to manage a relationship among port information of an initiator port, information of a logical volume storing data from the initiator port, and port information of a target port to be used for storing data from the initiator port to the logical volume, and to cause another computer to process a storage function of a storage system including the logical volume and the target port by creating a virtual machine for executing the storage function and by configuring the relationship on said another computer, said another computer sending the data to the logical volume of the storage system after executing the storage function. In specific embodiments, by executing the storage function on said another computer, the workload of executing the storage function on the storage system is eliminated.
    Type: Application
    Filed: October 23, 2012
    Publication date: April 24, 2014
    Inventors: Masayuki SAKATA, Akio NAKAJIMA, Akira DEGUCHI
  • Patent number: 8700866
    Abstract: A data transfer apparatus includes: a first port and a second port that communicate data; a memory unit that stores the data; and a securing unit that secures, when a first time period starting from transmission of data up to reception of a response to transmitted data at the first port is longer than a second time period starting from transmission of data up to reception of a response to transmitted data at the second port, a first memory space that is used in data transfer in the first port so as for the first memory space to have a larger size than a size of a second memory space used in data transfer in the second port.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: April 15, 2014
    Assignee: Ricoh Company, Limited
    Inventor: Junichi Ikeda