Abstract: A device having a shared memory and a method for providing access status information by the shared memory are disclosed. A digital processing device includes n processors and a shared memory. The shared memory is coupled to each processor though a separate bus, its storage area includes m common sections, and generates and outputs access status information related to whether an arbitrary processor is accessing at least one of the common sections. With the present invention, a control sequence of each processor can be simplified at a maximum by allowing the shared memory to generate and output access status information related to the common sections.

Abstract: A processor may include a writeback configured to perform a first writeback operation to store corresponding writeback data back to a lower-level memory upon eviction of the writeback data, and a writeback buffer configured to store the writeback data after the writeback data has been evicted from the writeback cache and before the writeback data has been sent to the lower-level memory. After the writeback data has been sent from the writeback buffer to the lower-level memory, and before the lower-level memory has acknowledged completion of the first writeback operation, the writeback cache may perform a second writeback operation to store different writeback data in the writeback buffer in response to eviction of the different writeback data, such that a total size of the writeback data for the concurrently outstanding writeback operations exceeds a total size of writeback data that the writeback buffer is capable of concurrently storing.

Abstract: An apparatus and method for detecting a data race of a multithread system is provided. A thread may be divided into an open sub region or a closed sub region according to a vector clock and an execution state. In order to detect a data race before the execution is terminated, when an open sub region is converted to a closed sub region, a memory access event corresponding to the closed sub region is investigated and a memory access event having no parallel relation with an open sub region is deleted among memory access events having been subject to the investigation.

Abstract: In a multi-threaded computer system that uses transactional memory, object fields accessed by only one thread are accessed by regular non-transactional read and write operations. When an object may be visible to more than one thread, access by non-transactional code is prevented and all accesses to the fields of that object are performed using transactional code. In one embodiment, the current visibility of an object is stored in the object itself. This stored visibility can be checked at runtime by code that accesses the object fields or code can be generated to check the visibility prior to access during compilation.

Abstract: A computing system uses specialized “Set Associative Transaction Tables” and additional “Summary Transaction Tables” to speed the processing of common transactional memory conflict cases and those which employ assist threads using an Address History Table and processes memory transactions with a Transaction Table in memory for parallel processing of multiple threads of execution by support of which an application need not be aware. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system.

Abstract: A concurrent and asynchronous system may be managed by monitoring the performance of a plurality of operations that access a designated region of memory. In that region of memory, an occurrence of a potentially non-deterministic event can be detected when at least one of the operations is a write operation. The occurrence of the potentially non-deterministic event may then be recorded.

Abstract: An apparatus and method of time keeping for a non-real-time OS is provided. The apparatus includes a processor and a Field Programmable Gate Array (FPGA). The processor requests performance of a Dual-Port Random Access Memory (DPRAM) read/write (R/W) operation in a DPRAM R/W time interval in a Time Division Multiple Access (TDMA) scheme using a system clock. Upon receipt of the DPRAM R/W operation performance request from the processor, the FPGA compares the operation performance request time with an access time table defining a DPRAM R/W time interval for each processor, generated in the TDMA scheme using the system clock. The FPGA performs the operation requested by the processor when the operation performance request has been made in the DPRAM R/W time interval of the processor.

Abstract: Concurrent threads in a multithreaded processor share access to a memory, with any location in the shared memory being accessible by any thread. In one embodiment, the shared memory has multiple independently-addressable memory banks, and one location per bank can be accessed in parallel. Parallel processing engines executing the threads generate a group of parallel memory access requests. Address conflict logic determines whether the requests can be satisfied in parallel (e.g., based on bank access constraints) and serializes the requests to the extent needed to avoid conflicts. In some embodiments, data read from one address in the shared memory can be broadcast to multiple processing engines.

Abstract: A multi-function peripheral (MFP) device having enhanced security for processed data is disclosed. The MFP includes both a non-volatile memory and a volatile memory. The MFP also includes a user interface configured to allow a user to prevent data from being stored on the non-volatile memory. The MFP further includes a processor or a switch configured to disable access to the non-volatile memory. The MFP blocks data from being stored on its non-volatile memory upon a user's selection via the user interface. The data is only temporarily stored on the volatile memory, and is erased after processing. This configuration prevents others from having access to the data.

Abstract: In traditional transactional locking systems, such as Transactional Locking with Read-Write locks (TLRW), threads may frequently update lock metadata, causing system performance degradation. A system and method for implementing transactional locking using reader-lists (TLRL) may associate a respective reader-list with each stripe of data in a shared memory system. Before reading a given stripe as part of a transaction, a thread may add itself to the stripe's reader-list, if the thread is not already on the reader-list. A thread may leave itself on a reader-list after finishing the transaction. Before a thread modifies a stripe, the modifying thread may acquire a write-lock for the stripe. The writer thread may indicate to each reader thread on the stripe's reader-list that if the reader thread is executing a transaction, the reader thread should abort. The indication may include setting an invalidation flag for the reader. The writer thread may clear the reader-list of a stripe it modified.

Abstract: Included are embodiments for a method for servicing memory read requests. At least one embodiment of a method includes receiving read requests from the I/O device; testing predetermined fields from the read requests to predict a type of read request; and when the type of request is predicted to be a data read request, then route the read request to a first queue. Additionally, some embodiments include when the type of request is predicted to be a control read request, then route the read request to a second queue, wherein the second queue has a higher priority than the first queue; determining which of the first queue and second queue to read; retrieving at least one of the read requests from the determined queue; and processing the retrieved read request.

Abstract: In an embodiment, a method and computer product is presented for executing a command in a replicated environment comprising a replication appliance and a production site, the method comprising: intercepting the command at a splitter; wherein the command comprises a atomic test and set request.

Abstract: A cache memory that includes: (i) an arbitrator, connected to multiple access generator, the arbitrator is adapted to receive different types of access requests from the multiple access generators and to select a single access request per arbitration cycle; (ii) a sequence of pipeline stages, the sequence comprises an input pipeline stage that is connected to the arbiter; and (iii) multiple cache resources, connected to the sequence of pipeline stages; wherein each cache resource can be read only by a small portion of the sequence of pipeline stages and can be written to only by a small portion of the sequence of pipeline stages.

Abstract: A memory controller implemented within a programmable integrated circuit can include a user interface having a command register and a plurality of data First-In-First-Out (FIFO) memories, wherein the command register can receive an address of a data FIFO memory of the plurality of data FIFO memories. A core controller coupled to the user interface can, responsive to an instruction from the user interface, generate control signals that initiate an operation within a memory device coupled to the core controller. A physical layer coupling with the core controller, the user interface, and the memory device can, responsive to a read operation of the memory device, store data received from the memory device within the selected data FIFO memory according to the address received in the command register.

Abstract: A technique for accessing a memory array includes receiving, from multiple requesters, memory access requests directed to a single port of the memory array. The memory access requests associated with each of the multiple requesters are serviced, based on a priority assigned to each of the multiple requesters, while maintaining a fixed timing for the memory access requests.

Abstract: The present invention provides an apparatus and method that increases the utilization by processors on shared resources. It provides the minimum latency in a multiprocessor system during usage right exchange between multi-processors on a shared resource. The apparatus provides a timed mailbox including a timer. The timed mailbox is at least associated with a first processor and a second processor. The second processor starts to utilize a shared resource to perform a task. According to a predetermined clock cycle number, the timed mailbox issues a signal in advance to notify the first processor of the availability of the shared resource to be utilized by the first processor.

Abstract: A shared memory system for a multicore computer system utilizing an interconnection network that furnishes tens of processing cores or more with the ability to refer concurrently to random addresses in a shared memory space with efficiency comparable to the typical efficiency achieved when referring to private memories. The network is essentially a lean and light-weight combinational circuit, although it may also contain non-deep pipelining. The network is generally composed of a sub-network for writing and a separate multicasting sub-network for reading, whose topologies are based on multiple logarithmic multistage networks, e.g. Baseline Networks, connected in parallel. The shared memory system computes paths between processing cores and memory banks anew at every clock cycle, without rearrangement.

Abstract: A method and an apparatus for accessing data of a message memory of a communication module by inputting or outputting data into or from the message memory, the message memory being connected to a buffer memory assemblage and the data being transferred to the message memory or from the message memory, the buffer memory assemblage having an input buffer memory in the first transfer direction and an output buffer memory in the second transfer direction; and the input buffer memory and the output buffer memory each being divided into a partial buffer memory and a shadow memory, the following steps being performed in each transfer direction: inputting data into the respective partial buffer memory, and transposing access to the partial buffer memory and shadow memory, so that subsequent data can be inputted into the shadow memory while the previously inputted data are already being outputted from the partial buffer memory in the stipulated transfer direction.

Abstract: A computing system processes memory transactions for parallel processing of multiple threads of execution by support of which an application need not be aware. The computing system transactional memory support provides a Transaction Table in memory and performs fast detection of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system. A transaction program employs a plurality of Set Associative Transaction Tables, one for each microprocessor, and Load and Store Summary Tables in memory for fast processing of common conflict.

Abstract: A multiple computer system is disclosed in which n computers (M1, M2 . . . Mn) each run a different portion of a single application program written to execute only on a single computer. The local memory of each computer is maintained substantially the same by updating all computers with every change made to addressed memory locations. Contention can arise when the same memory location is substantially simultaneously updated by two or more machines because of transmission delays and latency of the communications network interconnecting all the computers. Contention detection and resolution is disclosed. A count value (99) indicative of the cumulative number of times each memory location has been updated is utilized. Contention is indicated if the currently stored count value and the incoming updating count value are the same. A method of echo suppression and a method of echo rejection are disclosed.

Abstract: Some aspects include reception of a command from one of a chassis management module and a BIOS specifying a data region to be updated and a locking policy, determination of whether the data region is locked, implementation of the locking policy and returning of a session lock handle if it is determined that the data region is not locked, reception, from the one of the chassis management module and the BIOS, of data for updating the data region, the session lock handle, and an offset, determination that the session lock handle is associated with the data region, writing of the data to the data region at the offset, reception of a request for data of the updated data region from the other one of the chassis management module and the BIOS, determination of whether the updated data region is locked, and if it is determined that the updated data region is not locked, providing of the data of the updated data region to the other one of the chassis management module and the BIOS.

Abstract: A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.

Abstract: Methods, systems and software applications are provided for real time data processing. In one implementation, a method is provided for locking data objects in a computer system. The method may comprise determining whether a number of lock objects to be locked is less than or equal to a maximum number of lock objects; creating, when the number is less than or equal to the maximum, one or more lock objects comprising names and values for key fields; and creating, when the number is greater than the maximum, one or more lock objects by applying a heuristic process such that the lock objects include wild cards for key fields.

Abstract: A system, method, and computer program for caching a plurality of file fragments to improve file transfer performance, comprising the steps of exposing at least one file fragment of a computer file as a primary object to an application; caching said at least one file fragment at a plurality of points in a network system, wherein said at least one file fragment remains unchanged; and managing said at least one non-changing file fragment throughout said network system at a plurality of cache points and appropriate means and computer-readable instructions.

Abstract: A method of determining request transmission priority subject to request content and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the received requests have the priority subject to the respective content, and also determines whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time.

Abstract: System and methods for authenticating access to multiple data stores are disclosed. The system may include a server coupled to a network, a client device in communication with the server via the network and a plurality of data stores. The server may authenticate access to the data stores and forward information from those stores to the client device. An exemplary authentication method receives a request for access to data. Information concerning access to that data is stored and associated with an identifier assigned to a client device. If the identifier is found to correspond to the stored information during a future request for access to the store, access to that store is granted.

Abstract: Method and apparatus for managing concurrent access among computers to a bitmap stored on disk storage. In some examples, a command is received from a requesting computer of the computers, the command indicating that one or more bits in the bitmap are to be cleared. The bitmap as stored on the disk storage is updated responsive to the command to clear the one or more bits in the bitmap. Synchronization data associated with the bitmap is stored. The synchronization data is configured to distinguish between a current generation and a previous generation of the bitmap, and to specify an action to be performed in response to receiving a subsequent command for accessing the bitmap if the subsequent command identifies a previous generation.

Abstract: A method of and apparatus for arbitrating a memory access conflict to a memory array. The apparatus may include selection logic coupled with a plurality of ports and a memory array to arbitrate among a plurality of contending memory access requests and to conditionally block write data from accessing the memory array when write data arrives late in time.

Abstract: Provided are a method, system, and article of manufacture for varying access parameters for processes to access memory addresses in response to detecting a condition related to a pattern of processes access to memory addresses. A monitored condition is detected during application execution. An instrumentation program is invoked to monitor processes accessing data at addresses in a memory device in response to detecting the monitored condition. Information is logged on processes and the addresses they access in the memory device in response to invoking the instrumentation program. The logged information on the processes and the addresses they access is forwarded to an application analysis system in response to detecting a monitored condition during application execution.

Abstract: Atomic data are stored in blocks on a hard disk. The blocks are grouped into a committed block aggregate P1, which exists only on the hard disk, a next-generation committed block aggregate C1, which is converted into a committed block aggregate at predetermined times, and an atomic block aggregate S3, which is created for every user based on the committed block aggregate C1. User A makes desired data changes to S3. When user A terminates the data processing, the block aggregate storing the data is merged, like from the atomic block aggregate S4 to committed block aggregate C2, and stored on the hard disk as a committed block aggregate P3.

Abstract: A system for pushing data, the system includes a source node that stores a coherent copy of a block of data. The system also includes a push engine configured to determine a next consumer of the block of data. The determination being made in the absence of the push engine detecting a request for the block of data from the next consumer. The push engine causes the source node to push the block of data to a memory associated with the next consumer to reduce latency of the next consumer accessing the block of data.

Abstract: Mechanisms are disclosed for detecting protocols independently of the ports used by streams associated with the protocols or applications that may send out such streams. The detecting may entail using a content filter that is hosted on a networking stack, where the content filter may be composed of a stream buffer and handlers for detecting the protocols. The handlers may be further used to modify streams incoming to a port or streams outgoing from an application. The handlers can modify the streams in a variety of ways, including reading, inserting, replacing, deleting, and completing data in the streams according to some policy criteria, such as those set by parental controls. Individual handlers may be selected from a plurality or set of handlers so that they can be matched up to the appropriate streams.

Abstract: A processor and a memory controlling method. The processor enables a Scratch-Pad Memory (SPM) to prepare data that a processor core intends to process, using a data management unit including a data cache, thereby increasing a data processing rate.

Abstract: A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.

Abstract: A design structure is provided for a memory module containing a first interface for receiving data access commands and a second interface for re-transmitting data access commands to other memory modules, the second interface propagating multiple copies of received data access commands to multiple other memory modules. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports multiple replication of commands and another of which supports conventional daisy-chaining.

Abstract: A method of address-level log-based synchronization comprises a thread attempting to acquire a lock on an object. If its lock attempt fails, a thread logs, at a synchronization log, data access operations directed at the shared data object, and waits for a notification from the lock-owning thread indicating whether the logged operations succeeded. If its lock attempt succeeds, the lock-owning thread performs data access operations on the shared data object, and arbitrates among requests logged by other threads in the synchronization log, applying the modifications logged in the requests that do not conflict with other modification operations, and rejecting the requests that conflict. The master sends a success notification to the logging threads whose requests were accepted, and a failure notification to the logging threads whose requests were rejected.

Abstract: A design structure is provided for a memory module containing an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining.

Abstract: The system described herein may track references to a shared object by concurrently executing threads using a reference tracking data structure that includes an owner field and an array of byte-addressable per-thread entries, each including a per-thread reference counter and a per-thread counter lock. Slotted threads assigned to a given array entry may increment or decrement the per-thread reference counter in that entry in response to referencing or dereferencing the shared object. Unslotted threads may increment or decrement a shared unslotted reference counter. A thread may update the data structure and/or examine it to determine whether the number of references to the shared object is zero or non-zero using a blocking-optimistic or a non-blocking mechanism. A checking thread may acquire ownership of the data structure, obtain an instantaneous snapshot of all counters, and return a value indicating whether the number of references to the shared object is zero or non-zero.

Abstract: Machine-readable media, methods, apparatus and system for detecting a data access violation are described. In some embodiments, current memory access information related to a current memory access to a memory address by a current user thread may be obtained. It may be determined whether a cache includes a cache entry associated with the memory address. If the cache includes the cache entry associated with the memory address, then, an access history stored in the cache entry and the current memory access information may be analyzed to detect if there is at least one of an actual violation and a potential violation of accessing the memory address.

Abstract: A multiprocessor system includes first and second processors and a multi-path accessible semiconductor memory device including a shared memory area and a pseudo operation execution unit. The shared memory area is accessible by the first and second processors according to a page open policy. The pseudo operation execution unit responds to a virtual active command from one of the first and second processors to close a last-opened page. The virtual active command is generated with a row address not corresponding to any row of the shared memory area. For example, bit-lines of a last accessed row are pre-charged for closing the last-opened page.

Abstract: A system, method, and computer program product for handling shared cache lines to allow forward progress among processors in a multi-processor environment is provided. A counter and a threshold are provided a processor of the multi-processor environment, such that the counter is incremented for every exclusive cross interrogate (XI) reject that is followed by an instruction completion, and reset on an exclusive XI acknowledgement. If the XI reject counter reaches a preset threshold value, the processor's pipeline is drained by blocking instruction issue and prefetching attempts, creating a window for an exclusive XI from another processor to be honored, after which normal instruction processing is resumed. Configuring the preset threshold value as a programmable value allows for fine-tuning of system performance.

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Abstract: A memory system including a non-volatile memory, a cache memory, a control circuit, and a data processing device is configured. The high speed can be achieved by transferring data in the non-volatile memory to the cache memory to retain the same therein. When the data in the non-volatile memory is transferred to the cache memory, error correction is performed so as to improve the reliability. Since the cache memory and the non-volatile memory can be accessed from the data processing device independently, improvement in usability can be achieved. The memory system including the plurality of chips is configured as a memory system module where respective chips are arranged in a stacked manner and wired by a ball grid array (BGA) and wire bonding between chips.

Abstract: The present invention relates to mechanisms for handling and detecting collisions between threads (5, 6, 7) that execute computer program instructions out of program order. According to an embodiment of the present invention each of a plurality of threads (5, 6, 7) are associated with a respective data structure (9, 10, 11) comprising a number of bits (12) that correspond to memory elements (m0, m1, m2, mn) of a shared memory (4). When a thread accesses a memory element in the shared memory, it sets a bit in its associated data structure, which bit corresponds to the accessed memory element. This indicates that the memory element has been accessed by the thread. Collision detection may be carried out after the thread has finished executing by means of comparing the data structure of the thread with the data structures of other threads on which the thread may depend.

Abstract: A method, system, apparatus, and signal-bearing media for finding a logical unit data structure associated with a command and a logical unit of a device, selecting a command table based on the logical unit data structure and a host that issued the command, indexing the command into the command table, and performing a routine indicated by the command table in response to the indexing. The command table may be a normal command table if no other host has reserved the logical unit or a reserved command table if another host has reserved the logical unit.

Abstract: Atomic operation may be implemented in a processor system comprising a main memory and a power processor element (PPE) including a power processor unit (PPU) coupled to an external cache. The PPE may atomically load data from a lock-line in the main memory into a first location X in the external cache. A size of the data and the lock line may be larger than a data size for the standard atomic operations that may be performed with the PPE. The data may be reserved in a second location Y in the external cache.

Abstract: One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

Abstract: A memory controller is provided for dealing with change in the form of use or operation state of a system. The memory controller includes bus interfaces, a memory controller core unit, and a memory interface. The memory controller core unit has a command controller. The bus interface units and command controller exchange commands via a bus.

Abstract: An embodiment of the invention provides an apparatus and a method of dynamically controlling the number of busy waiters in for a synchronization object. The apparatus and method perform the steps of increasing a number of allowed busy waiters if there is a waiter in a sleep state and there are no current busy waiters when a requester releases the synchronization object, and decreasing the number of allowed busy waiters if a busy waiter moves from a busy waiting state to the sleep state.

Abstract: Apparatus and method are disclosed for managing lock state information in a distributed file system. A set of data containers storing data is maintained. The data containers are striped across a plurality of volumes, where each volume includes one or more data storage devices. A metadata volume is maintained with the plurality of volumes, the metadata volume configured to include a lock state database that stores lock state information for the plurality of volumes. The lock state information is communicated between the metadata volume and the plurality of volumes.