Abstract: In one embodiment, a method includes receiving an unstructured data record and parsing the unstructured data record to determine a characterization of the unstructured data record. The characterization includes determination of: a number of fields, a length for the fields, and an order of the fields as stored in the unstructured data record. The method also includes obtaining a first key pair that includes a primary key-name associated with a first key-value and hashing at least the first key-value to obtain a hash value. In addition, the method includes updating the unstructured data record to include the hash value as an indexing key thereby creating a modified data record. Also, the method includes storing the modified data record in a structured database. Moreover, the method includes updating an index of the structured database to include an entry for the modified data record, the entry including the hash value.

Abstract: Implementations described herein relate to selective data map unit access. A memory device may receive a request from a host device to access a resource associated with a data map unit. The memory device may identify whether the data map unit is in a locked state or an unlocked state. The data map unit may be in the locked state when another host device currently has exclusive access to the resource or may be in the unlocked state when no other host device currently has exclusive access to the resource. The memory device may selectively grant the host device exclusive access to the resource based on identifying whether the data map unit is in the locked state or the unlocked state.

Abstract: A computing system with a first instruction of an instruction set architecture (ISA) for direct invalidation, without writing back, in a hierarchical cache structure based on one single designated key identification code, and a second instruction of ISA for direct invalidation, without writing back, in the hierarchical cache structure based on a plurality of designated key identification codes is shown. A decoder transforms the first or second instruction into at least one microinstruction. Based on the at least one microinstruction, one direct invalidation request is provided corresponding to each designated key identification code, to be passed to the hierarchical cache structure through a memory ordering buffer. For each direct invalidation request, the cache line write-back and invalidation regarding a designated key identification code is performed on a last-level cache first, and then is performed on the in-core cache modules.

Abstract: An automated test equipment (ATE) system comprises a system controller communicatively coupled to a tester processor, where the system controller is operable to transmit instructions to the tester processor, and where the tester processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The apparatus also comprises an FPGA programmed to support a first protocol communicatively coupled to the tester processor comprising at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing a DUT of the plurality of DUTs. Further, the apparatus comprises a bus adapter comprising a protocol converter module operable to convert signals associated with the first protocol received from the FPGA to signals associated with a second protocol prior to transmitting the signals to the DUT, wherein the DUT communicates using the second protocol.

Abstract: An integrated circuit may include orthogonal multi-phase scheduling circuitry. The scheduling circuitry may include a number of orthogonal scheduling circuits each of which is configured to receive different command types and to output a single winning command. The scheduling circuitry may further include a phase assignment circuit for receiving the winning commands from the orthogonal scheduling circuits and for assigning the received winning commands to different corresponding phase groups. Each orthogonal scheduling circuit may include command buffers, command arbiters, a global arbiter, and associated safe checking circuits.

Abstract: According to examples, an apparatus may include a processor that may delete portions of firmware instructions responsive to an indication that the portions should be disabled. To facilitate the foregoing, the firmware instructions may be deployed in a segmented architecture stored in respective regions of a storage device. The regions may include a metadata region, a main region, and excludable regions. The metadata region may store metadata that describes the structure of the firmware instructions and/or the various other regions. The main region may store core firmware instructions that may not be deleted. Each excludable region may store respective excludable firmware instructions. Each excludable firmware instructions may be associated with a flag that indicates whether or not the instructions should be disabled. If so, the corresponding excludable region in the storage device is identified and the contents may be removed, permanently disabling the excludable firmware instructions that were stored there.

Abstract: A computerized-method for reducing wait-time in a multichannel-contact-center. For each query that is not resolved by a bot: a. selecting a digital-channel-type from a plurality of digital-channel-types; b. operating an aggregator module on the selected digital-channel-type to aggregate the received query and similar pending queries into a group-of-queries; c. operating a tracker-module on the group-of-queries to identify a query-resolution and to send a notification as to the query-resolution to the customer via the digital-channel-type that the query has been received; and d. repeating operations a.-c. until a query-resolution has been identified or all digital-channel-types in the plurality of digital-channel-types have been selected.

Abstract: A non-volatile memory receives a data read request from a processing core of a plurality of processing cores. The read request is directed to a data partition of a non-volatile memory. The non-volatile memory determines whether to process the read request using read-while-write collision management. When it is determined to process the read request using read-while-write collision management, an address associated with the read request is stored in an address register of a set of registers associated with the processing core. Write operations directed to the data partition are suspended. A read operation associated with the read request is executed while the write operations are suspended and data responsive to the read operation is stored in one or more data registers of the set of registers. The data stored in the one or more data registers of the set of registers is provided to the processing core.

Abstract: Implementations described herein relate to burst data read storage. In some implementations, a controller may receive a write command. The controller may determine whether a burst read flag, included in the write command, is set. The controller may write host data, associated with the write command, to a first type of storage block of the memory device or to a second type of storage block of the memory device based on whether the burst read flag is set.

Abstract: An error associated with a read operation corresponding to a memory die of a memory sub-system is detected. In response to detecting the error, a first read throughput level of the memory sub-system is identified. A quantity of queues receiving operation requests is decreased, the decreased quantity of queues corresponding to a second read throughput level. A read retry operation associated with the memory die is initiated at the second read throughput level.

Abstract: A data read/write method includes: establishing a first connection to a client, determining a first tablespace corresponding to the first connection, and determining a first node corresponding to the first connection or the first tablespace in a plurality of nodes, where the first connection receives a read/write request from the client; loading data in the first tablespace to a memory in the first node, and processing a read/write request on the first connection using a first working thread, where the first working thread is generated by a processor in the first node.

Abstract: A method for performing data access performance shaping of a memory device and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device, for performing data access on the NV memory according to the plurality of host commands; and monitoring the plurality of host commands to control respective performance metrics of a plurality of access control groups of the memory device with a dual-state leaky bucket (LB) model, wherein regarding any access control group, for example: determining at least one first performance metric according to at least one first command to be a first LB fill level of a dual-state LB; in response to the first LB fill level being below a state threshold, determining the dual-state LB to be in a first predetermined state, and configuring the dual-state LB to have a first predetermined drain rate, for dynamically adjusting performance quota.

Abstract: Methods, systems, and devices for scheduling command execution are described. A memory sub-system can schedule command execution according to a type of command received. For a read operation, a memory sub-system can receive read commands for multiple memory dice. The memory sub-system can select a first memory die and execute a first set of read commands associated with the first memory die. The memory sub-system can then select a second memory die and execute a second set of read commands associated with the second memory die.

Abstract: Systems, apparatuses and methods may provide for technology that partitions a high dynamic range (HDR) image into a plurality of regions and determines, on a per region basis, a luminance level of the HDR image. Additionally, the technology may select, on the per image basis, a encoding amount for each region in the plurality of regions based on the luminance level.

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. Different component solid state drives in solid state drive are configured with different optimizations of memory/storage operations. An address map in the solid state drive is used by the drive aggregator to host different namespaces in the component solid state drives based on optimization requirements of the namespaces and based on the optimizations of memory operations that have been implement in the component solid state drives.

Abstract: A system on a chip allows external NorFlash memory sharing by multiple master devices. The system on a chip is configured to use an external NorFlash memory and includes a plurality of master devices and NorFlash virtualising circuity. The NorFlash virtualizing circuitry is configured to suspend a program operation or an erase operation being carried out on the external NorFlash memory, permit a read operation to be carried out on the NorFlash memory and then resume the suspended program operation or erase operation. Each master device of the plurality of master devices operates as a master to independently access the external NorFlash memory.

Abstract: A computerized-method for reducing wait-time in a multichannel-contact-center is provided herein. For each query that is not resolved by a hot, operating a Channel-Agnostic-Queuing (CAQ) module. The CAQ-module includes: a. selecting a digital-channel-type in a predetermined order; b. operating an aggregator module on the selected digital-channel-type to: (i) identify similar pending queries in a queue-database related to the digital-channel-type: and (ii) aggregate the received query and the identified similar pending queries into a group-of-queries; c. operating a tracker-module on the group-of-queries to identify a query-resolution and to send a notification as to the query-resolution to the customer and to related customers of the identified similar pending queries; and d. when a total-parking-period of the plurality of digital-channel-types is lower than an expected wait-time of the received query and the received query hasn't been resolved, repeating operations a.-c.

Abstract: A shared memory provides multi-channel access from multiple computing or host devices. A priority circuit prioritizes the multiple memory requests that are submitted as bids from the multiple host channels, such that those memory access requests that do not give rise to a conflict may proceed in parallel. The shared memory may be multi-ported and a routing circuit routes the prioritized memory access request to the appropriate memory ports where the allowed memory access requests may be carried out.

Abstract: A memory system includes: a memory device; a first queue suitable for queuing commands received from a host; a second queue suitable for enqueuing the commands from the first queue and dequeuing the commands to the memory device according to the FIFO scheme; and a processor suitable for: delaying enqueuing a read command into the second queue until the program operation is successfully performed when a logical address of a write command, in response to which a program operation is being performed, is the same as a logical address corresponding to the read command enqueued in the first queue; and determining whether or not to enqueue a subsequent read command, which is enqueued in the first queue after the read command, into the second queue.

Abstract: A memory management method includes determining a memory page that needs to be swapped out of a memory, for each memory page that needs to be swapped out, generating, based on the memory page, a work task reclaiming the memory page, and allocating each work task to a dedicated worker thread for execution.

Abstract: A processor in a system is responsive to a coherent memory request buffer having a plurality of entries to store coherent memory requests from a client module and a non-coherent memory request buffer having a plurality of entries to store non-coherent memory requests from the client module. The client module buffers coherent and non-coherent memory requests and releases the memory requests based on one or more conditions of the processor or one of its caches. The memory requests are released to a central data fabric and into the system based on a first watermark associated with the coherent memory buffer and a second watermark associated with the non-coherent memory buffer.

Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.

Abstract: An error associated with a read operation corresponding to a target memory die of a memory sub-system is detected. In response to detecting the error, a first read throughput level of the memory sub-system is identified. The first read throughput level is adjusted to a second read throughput level. A read retry operation associated with the target memory die is executed at the second read throughput level.

Abstract: A distributed policy management (PM) system (e.g., system for authentication, authorization, and accounting (AAA) activities on a network) is provided. Nodes of the PM system may share information of the PM system using a distributed data store (e.g., a multi-master cache). Each node of the distributed PM system may further share information from the distributed data store with other nodes of a corporate infrastructure network by augmenting information in a remote authentication dial-in user service (RADIUS) protocol message. Nodes that are involved in policy management (e.g., network authentication server (NAS) or firewall) without access to the distributed data store may receive information via augmented RADIUS messages. In this manner, devices may be interfaced to the distributed PM system without having access to the distributed data store. High availability and load balancing implementations may be provided by leveraging the distributed data store across nodes of the PM system.

Abstract: A memory system may include a plurality of memory dies configured to store data therein, and a controller coupled to the plurality of memory dies through a plurality of channels, and configured to correlate at least some of a plurality of read requests and transferring the plurality of read requests to the plurality of channels, such that the plurality of read requests are processed in an interleaving way through the plurality of channels, when controlling the plurality of memory dies for the plurality of read requests. The controller may determine whether to perform the correlation operation in response to the number of the plurality of read requests, wherein the plurality of read requests include a read request for an internal operation of the controller and a read request received from a host.

Abstract: Aspects of the invention include receiving a request to obtain data located in an address space to diagnose a computer error. It is determined whether a threshold number of resources are available to obtain the data. Based on determining that the threshold number of resources is available to obtain the data, a priority level of the computer program is assessed. A number of threads to assign to a workload to obtain the data from the address space is determined based at least in part on the priority level of the computer program. The determined number of threads are assigned to the workload. The workload is divided into a number of parallel units equal to the number of threads assigned to the workload. The parallel units of the workload are executed by the assigned threads to capture the data in the address space. The captured data is stored.

Abstract: A memory system includes a plurality of non-volatile memory chips divided into a plurality of storage areas, and a memory controller that is connected to the plurality of memory chips to control an operation of each memory chip. The memory controller is configured to set an arbitration period separately for each of the respective storage areas, and to execute a process to store data into the storage areas one after another in accordance with the arbitration period set therefor.

Abstract: Switchless interconnect fabric message distribution includes end-to-end partitioning of message pathways or multiple priority levels with interrupt capability. A switchless interconnect fabric message distribution system includes a data distribution module and at least two host-bus adapters connected to the data distribution module. The data distribution module includes partition first in first out buffers. Each of the host-bus adapters includes an input manager connected to input priority first in first out buffers and an output manager connected to priority first in first out buffers.

Abstract: A memory controller for controlling a memory device for storing data, the memory controller, the memory controller comprising: a request transmitter for providing a program suspend request for suspending a program operation, when the memory device receives a read request from a host while the memory device is performing the program operation and a command controller for generating and outputting a program suspend command, based on the program suspend request, and outputting a cache read command or normal read command, based on a number of commands corresponding to a request received from the host, which are queued in a command queue.

Abstract: Aspects of a storage device are provided which allow a read command to be identified for execution from multiple read commands received from a host. The storage device includes a memory configured to store a plurality of data units each comprising one or more data fragments, and metadata associated with the data units. A controller is configured to receive from the host a plurality of read commands each requesting one of the data units. The controller is further configured to identify one of the read commands based on the metadata, and to transfer the data unit associated with the identified read command to the host before transferring the data unit associated with the other read commands.

Abstract: A method for safely sharing access to a volume is disclosed. In one embodiment, such a method includes notifying a storage system that a volume on the storage system is in use by a first host system. The method stores, on the storage system, a first indicator indicating the volume is in use by the first host system. When the storage system receives an I/O request from a second host system to access data on the volume, the storage system reads the first indicator to determine that the volume is in use by the first host system. The storage system may then reject the I/O request from the second host system as a result of the first indicator. A corresponding system and computer program product are also disclosed.

Abstract: Technologies for contention-aware cloud compute scheduling include a number of compute nodes in a cloud computing cluster and a cloud controller. Each compute node collects performance data indicative of cache contention on the compute node, for example, cache misses per thousand instructions. Each compute node determines a contention score as a function of the performance data and stores the contention score in a cloud state database. In response to a request for a new virtual machine, the cloud controller receives contention scores for the compute nodes and selects a compute node based on the contention score. The cloud controller schedules the new virtual machine on the selected compute node. The contention score may include a contention metric and a contention score level indicative of the contention metric. The contention score level may be determined by comparing the contention metric to a number of thresholds. Other embodiments are described and claimed.

Abstract: Techniques are disclosed relating to a thread-group-scoped gate instruction. In some embodiments, graphics processor circuitry is configured to execute, for multiple SIMD groups of a thread group, a graphics program that includes a gate instruction. During execution of the gate instruction for a first SIMD group, the processor accesses state information to determine that a threshold number of other SIMD groups in the thread group have not yet executed the gate instruction. Based on the determination, the processor executes a particular set of instructions of the graphics program for the first SIMD group (that is not executed by one or more other SIMD groups that reach the gate instruction after the first SIMD group). For example, the particular set of instructions may be a utility program that performs one or more operations for the entire thread group but is only executed by a subset of the SIMD groups.

Abstract: Provided are techniques for adjusting a dispatch ratio for dispatching tasks from multiple queues. The dispatch ratio is set for each queue of a plurality of queues. A number of Central Processing Unit (CPU) cycles used by tasks from each of the plurality of queues during the interval is tracked. A CPU high percentage is determined that indicates a percentage of CPU cycles used by high priority tasks. In response to determining that the CPU high percentage is below a high threshold, a new dispatch ratio is calculated that indicates an increased number of high priority tasks are to be dispatched, and the new dispatch ratio is based on the CPU high percentage, the high threshold, and a current dispatches high value. The increased number of high priority tasks are dispatched from the high priority queue based on the new dispatch ratio during a new interval.

Abstract: A method for performing store buffer coalescing in a multiprocessor computer system includes forming, in a coalescing store buffer associated with a core in said multiprocessor system, an atomic group of writes; and performing each individual write in said atomic group in an order which is a function of an address in a memory system to which each of the writes in said atomic group are being written.

Abstract: In one embodiment, a method includes allocating, by an operating system of a computing device, computer-implemented memory into a discardable portion and a durable portion; receiving, from a computer-executable program, a designation indicator of a particular data file that is associated with the computer-executable program indicating that the particular file is to be stored in the discardable portion of the memory and in response, storing the particular data file in one or more particular pages of the discardable portion of the memory; identifying an occurrence of a computing condition and in response, marking the one or more particular pages that include the particular data file as invalid for the computer-executable program; receiving, from the computer-executable program, a request for the particular data file; and in response to receiving the request, providing, to the computer-executable program, a notification that the particular data file is invalid for the computer-executable program.

Abstract: A system includes a memory, a processor in communication with the memory, an application, and a supervisor. The supervisor is configured to allocate an identifier corresponding to a virtual memory area and expose a data structure that is readable by the application. Responsive to a fault trigger associated with an address, the supervisor is configured to record fault information in the data structure. The application is configured to predict at least a portion of subsequent fault information based on fault information recorded in the data structure.

Abstract: A multilevel memory subsystem includes a persistent memory device that can access data chunks sequentially or randomly to improve read latency, or can prefetch data blocks to improve read bandwidth. A media controller dynamically switches between a first read mode of accessing data chunks sequentially or randomly and a second read mode of prefetching data blocks. The media controller switches between the first and second read modes based on a number of read commands pending in a command queue.

Abstract: A method includes determining, by a storage unit of a dispersed storage network (DSN), a storage unit memory pressure level. When the storage unit memory pressure level compares unfavorably to a threshold, the method further includes, in response to a data access request regarding an encoded data slice from a computing device, determining whether the data access request includes an override message or a non-override message. When the data access request includes the non-override message, the method includes generating a storage unit memory pressure level message in accordance with the storage unit memory pressure level and the type of data access request, sending the storage unit memory pressure level message to the computing device, and processing the data access request in accordance with the storage unit memory pressure level message. When the data access request includes the override message, the method further includes processing the data access request.

Abstract: A computer-implemented method includes: monitoring, by a computing device, computing resource utilization by a plurality of virtual computing components sharing a same kernel; monitoring, by the computing device, transaction counts produced by the plurality of virtual computing components; determining, by the computing device, that the transaction counts increase by less than a threshold number as the computing resource utilization increases; and creating, by the computing device, an additional virtual computing component on a separate kernel based on determining that the transaction counts increase by less than a threshold number as the computing resource utilization increases.

Abstract: A data processor is disclosed in which groups of execution threads can execute a set of instructions in lockstep, and in which a plurality of execution lanes can perform processing operations for the execution threads. Two or more execution threads of a thread group are issued to the same execution lane for execution. The two or more execution threads can then be processed by the execution lane successively, such that the execution lane performs the same processing operation successively. This can have the effect of reducing signal transitions, such that the overall energy consumption of the data processor can be reduced.

Abstract: A request to read data from a location associated with a memory component is received. The request is assigned a first tag, the first tag having a first identifier of a first buffer to store data read from the location. The request to read data is determined to collide with an earlier request to write data to the location. The earlier request is assigned a second tag, the second tag having a second identifier of a second buffer to store data to write to the location. An attempt to lock the second tag and the second buffer for the request to read data is made. The request to read data is fulfilled from the second buffer in response to a successful attempt to lock the second tag and the second buffer.

Abstract: A graphics processing unit may, in accordance with a kernel, determine that at least a first packet is written to a memory buffer of the graphics processing unit by a network interface card via a direct memory access, process the at least the first packet in accordance with the kernel, and provide a first notification to a central processing unit that the at least the first packet is processed in accordance with the kernel. The graphics processing unit may further determine that at least a second packet is written to the memory buffer by the network interface card via the direct memory access, process the at least the second packet in accordance with the kernel, where the kernel comprises a persistent kernel, and provide a second notification to the central processing unit that the at least the second packet is processed in accordance with the kernel.

Abstract: This patent specification relates to apparatus, systems, methods, and related computer program products for providing home security/smart home objectives. More particularly, this patent specification relates to a plurality of devices, including intelligent, multi-sensing, network-connected devices, that communicate with each other and/or with a central server or a cloud-computing system to provide any of a variety of useful home security/smart home objectives.

Abstract: A method includes generating a first lock requests, each for transmission to a storage unit, where each first lock request indicates a first encoded data slice. First ballots are received, each of the first ballots corresponds to a storage unit, each of the first ballots indicates a first ranking of first requesting entities that includes the DST processing unit. First election result data is generated based on the first ballots. The first election result data indicates a first winner. When the first winner is the DST processing unit, slice access requests are generated in response to the first election result data indicating that the first winner is the DST processing unit, each for transmission to one of the storage units, where each of the slice access requests indicates the first encoded data slice.

Abstract: A processing system includes a processing core to execute a virtual machine (VM) comprising a guest operating system (OS) and a memory management unit, communicatively coupled to the processing core, comprising a storage device to store an extended page table entry (EPTE) comprising a mapping from a guest physical address (GPA) associated with the guest OS to an identifier of a memory frame, a first plurality of access right flags associated with accessing the memory frame in a first page mode referenced by an attribute of a memory page identified by the GPA, and a second plurality of access right flags associated with accessing the memory frame in a second page mode referenced by the attribute of the memory page identified by the GPA.

Abstract: The invention provides for a database management system (100, 400) comprising a container management system (102). The container management system comprises: a container management system memory (106) for storing machine executable instructions (114) and a container management system processor (104).

Abstract: Methods, systems, and computer-readable storage media for automatically detecting potential performance degradation in a data analytics system including multiple servers, actions include determining a threshold performance score for each server of the multiple servers during an initial period, the threshold performance scores being determined at least partially based on a report generated by a respective server, and, after the initial period, and for each server: intermittently calculating a performance score, comparing the performance score to the threshold performance score to determine whether a violation indicating performance degradation occurs, and transmitting a notification to report consecutive violations.

Abstract: Technologies for contention-aware cloud compute scheduling include a number of compute nodes in a cloud computing cluster and a cloud controller. Each compute node collects performance data indicative of cache contention on the compute node, for example, cache misses per thousand instructions. Each compute node determines a contention score as a function of the performance data and stores the contention score in a cloud state database. In response to a request for a new virtual machine, the cloud controller receives contention scores for the compute nodes and selects a compute node based on the contention score. The cloud controller schedules the new virtual machine on the selected compute node. The contention score may include a contention metric and a contention score level indicative of the contention metric. The contention score level may be determined by comparing the contention metric to a number of thresholds. Other embodiments are described and claimed.

Abstract: A method of operating a system comprising multiple processor tiles divided into a plurality of domains wherein within each domain the tiles are connected to one another via a respective instance of a time-deterministic interconnect and between domains the tiles are connected to one another via a non-time-deterministic interconnect. The method comprises: performing a compute stage, then performing a respective internal barrier synchronization within each domain, then performing an internal exchange phase within each domain, then performing an external barrier synchronization to synchronize between different domains, then performing an external exchange phase between the domains.