Abstract: A shared memory provides multi-channel access from multiple computing or host devices. A priority circuit prioritizes the multiple memory requests that are submitted as bids from the multiple host channels, such that those memory access requests that do not give rise to a conflict may proceed in parallel. The shared memory may be multi-ported and a routing circuit routes the prioritized memory access request to the appropriate memory ports where the allowed memory access requests may be carried out.

Abstract: A memory system includes: a memory device; a first queue suitable for queuing commands received from a host; a second queue suitable for enqueuing the commands from the first queue and dequeuing the commands to the memory device according to the FIFO scheme; and a processor suitable for: delaying enqueuing a read command into the second queue until the program operation is successfully performed when a logical address of a write command, in response to which a program operation is being performed, is the same as a logical address corresponding to the read command enqueued in the first queue; and determining whether or not to enqueue a subsequent read command, which is enqueued in the first queue after the read command, into the second queue.

Abstract: A memory management method includes determining a memory page that needs to be swapped out of a memory, for each memory page that needs to be swapped out, generating, based on the memory page, a work task reclaiming the memory page, and allocating each work task to a dedicated worker thread for execution.

Abstract: A processor in a system is responsive to a coherent memory request buffer having a plurality of entries to store coherent memory requests from a client module and a non-coherent memory request buffer having a plurality of entries to store non-coherent memory requests from the client module. The client module buffers coherent and non-coherent memory requests and releases the memory requests based on one or more conditions of the processor or one of its caches. The memory requests are released to a central data fabric and into the system based on a first watermark associated with the coherent memory buffer and a second watermark associated with the non-coherent memory buffer.

Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.

Abstract: An error associated with a read operation corresponding to a target memory die of a memory sub-system is detected. In response to detecting the error, a first read throughput level of the memory sub-system is identified. The first read throughput level is adjusted to a second read throughput level. A read retry operation associated with the target memory die is executed at the second read throughput level.

Abstract: A distributed policy management (PM) system (e.g., system for authentication, authorization, and accounting (AAA) activities on a network) is provided. Nodes of the PM system may share information of the PM system using a distributed data store (e.g., a multi-master cache). Each node of the distributed PM system may further share information from the distributed data store with other nodes of a corporate infrastructure network by augmenting information in a remote authentication dial-in user service (RADIUS) protocol message. Nodes that are involved in policy management (e.g., network authentication server (NAS) or firewall) without access to the distributed data store may receive information via augmented RADIUS messages. In this manner, devices may be interfaced to the distributed PM system without having access to the distributed data store. High availability and load balancing implementations may be provided by leveraging the distributed data store across nodes of the PM system.

Abstract: A memory system may include a plurality of memory dies configured to store data therein, and a controller coupled to the plurality of memory dies through a plurality of channels, and configured to correlate at least some of a plurality of read requests and transferring the plurality of read requests to the plurality of channels, such that the plurality of read requests are processed in an interleaving way through the plurality of channels, when controlling the plurality of memory dies for the plurality of read requests. The controller may determine whether to perform the correlation operation in response to the number of the plurality of read requests, wherein the plurality of read requests include a read request for an internal operation of the controller and a read request received from a host.

Abstract: Aspects of the invention include receiving a request to obtain data located in an address space to diagnose a computer error. It is determined whether a threshold number of resources are available to obtain the data. Based on determining that the threshold number of resources is available to obtain the data, a priority level of the computer program is assessed. A number of threads to assign to a workload to obtain the data from the address space is determined based at least in part on the priority level of the computer program. The determined number of threads are assigned to the workload. The workload is divided into a number of parallel units equal to the number of threads assigned to the workload. The parallel units of the workload are executed by the assigned threads to capture the data in the address space. The captured data is stored.

Abstract: A memory system includes a plurality of non-volatile memory chips divided into a plurality of storage areas, and a memory controller that is connected to the plurality of memory chips to control an operation of each memory chip. The memory controller is configured to set an arbitration period separately for each of the respective storage areas, and to execute a process to store data into the storage areas one after another in accordance with the arbitration period set therefor.

Abstract: Switchless interconnect fabric message distribution includes end-to-end partitioning of message pathways or multiple priority levels with interrupt capability. A switchless interconnect fabric message distribution system includes a data distribution module and at least two host-bus adapters connected to the data distribution module. The data distribution module includes partition first in first out buffers. Each of the host-bus adapters includes an input manager connected to input priority first in first out buffers and an output manager connected to priority first in first out buffers.

Abstract: A memory controller for controlling a memory device for storing data, the memory controller, the memory controller comprising: a request transmitter for providing a program suspend request for suspending a program operation, when the memory device receives a read request from a host while the memory device is performing the program operation and a command controller for generating and outputting a program suspend command, based on the program suspend request, and outputting a cache read command or normal read command, based on a number of commands corresponding to a request received from the host, which are queued in a command queue.

Abstract: Aspects of a storage device are provided which allow a read command to be identified for execution from multiple read commands received from a host. The storage device includes a memory configured to store a plurality of data units each comprising one or more data fragments, and metadata associated with the data units. A controller is configured to receive from the host a plurality of read commands each requesting one of the data units. The controller is further configured to identify one of the read commands based on the metadata, and to transfer the data unit associated with the identified read command to the host before transferring the data unit associated with the other read commands.

Abstract: A method for safely sharing access to a volume is disclosed. In one embodiment, such a method includes notifying a storage system that a volume on the storage system is in use by a first host system. The method stores, on the storage system, a first indicator indicating the volume is in use by the first host system. When the storage system receives an I/O request from a second host system to access data on the volume, the storage system reads the first indicator to determine that the volume is in use by the first host system. The storage system may then reject the I/O request from the second host system as a result of the first indicator. A corresponding system and computer program product are also disclosed.

Abstract: Technologies for contention-aware cloud compute scheduling include a number of compute nodes in a cloud computing cluster and a cloud controller. Each compute node collects performance data indicative of cache contention on the compute node, for example, cache misses per thousand instructions. Each compute node determines a contention score as a function of the performance data and stores the contention score in a cloud state database. In response to a request for a new virtual machine, the cloud controller receives contention scores for the compute nodes and selects a compute node based on the contention score. The cloud controller schedules the new virtual machine on the selected compute node. The contention score may include a contention metric and a contention score level indicative of the contention metric. The contention score level may be determined by comparing the contention metric to a number of thresholds. Other embodiments are described and claimed.

Abstract: Techniques are disclosed relating to a thread-group-scoped gate instruction. In some embodiments, graphics processor circuitry is configured to execute, for multiple SIMD groups of a thread group, a graphics program that includes a gate instruction. During execution of the gate instruction for a first SIMD group, the processor accesses state information to determine that a threshold number of other SIMD groups in the thread group have not yet executed the gate instruction. Based on the determination, the processor executes a particular set of instructions of the graphics program for the first SIMD group (that is not executed by one or more other SIMD groups that reach the gate instruction after the first SIMD group). For example, the particular set of instructions may be a utility program that performs one or more operations for the entire thread group but is only executed by a subset of the SIMD groups.

Abstract: Provided are techniques for adjusting a dispatch ratio for dispatching tasks from multiple queues. The dispatch ratio is set for each queue of a plurality of queues. A number of Central Processing Unit (CPU) cycles used by tasks from each of the plurality of queues during the interval is tracked. A CPU high percentage is determined that indicates a percentage of CPU cycles used by high priority tasks. In response to determining that the CPU high percentage is below a high threshold, a new dispatch ratio is calculated that indicates an increased number of high priority tasks are to be dispatched, and the new dispatch ratio is based on the CPU high percentage, the high threshold, and a current dispatches high value. The increased number of high priority tasks are dispatched from the high priority queue based on the new dispatch ratio during a new interval.

Abstract: A method for performing store buffer coalescing in a multiprocessor computer system includes forming, in a coalescing store buffer associated with a core in said multiprocessor system, an atomic group of writes; and performing each individual write in said atomic group in an order which is a function of an address in a memory system to which each of the writes in said atomic group are being written.

Abstract: In one embodiment, a method includes allocating, by an operating system of a computing device, computer-implemented memory into a discardable portion and a durable portion; receiving, from a computer-executable program, a designation indicator of a particular data file that is associated with the computer-executable program indicating that the particular file is to be stored in the discardable portion of the memory and in response, storing the particular data file in one or more particular pages of the discardable portion of the memory; identifying an occurrence of a computing condition and in response, marking the one or more particular pages that include the particular data file as invalid for the computer-executable program; receiving, from the computer-executable program, a request for the particular data file; and in response to receiving the request, providing, to the computer-executable program, a notification that the particular data file is invalid for the computer-executable program.

Abstract: A system includes a memory, a processor in communication with the memory, an application, and a supervisor. The supervisor is configured to allocate an identifier corresponding to a virtual memory area and expose a data structure that is readable by the application. Responsive to a fault trigger associated with an address, the supervisor is configured to record fault information in the data structure. The application is configured to predict at least a portion of subsequent fault information based on fault information recorded in the data structure.

Abstract: A multilevel memory subsystem includes a persistent memory device that can access data chunks sequentially or randomly to improve read latency, or can prefetch data blocks to improve read bandwidth. A media controller dynamically switches between a first read mode of accessing data chunks sequentially or randomly and a second read mode of prefetching data blocks. The media controller switches between the first and second read modes based on a number of read commands pending in a command queue.

Abstract: A method includes determining, by a storage unit of a dispersed storage network (DSN), a storage unit memory pressure level. When the storage unit memory pressure level compares unfavorably to a threshold, the method further includes, in response to a data access request regarding an encoded data slice from a computing device, determining whether the data access request includes an override message or a non-override message. When the data access request includes the non-override message, the method includes generating a storage unit memory pressure level message in accordance with the storage unit memory pressure level and the type of data access request, sending the storage unit memory pressure level message to the computing device, and processing the data access request in accordance with the storage unit memory pressure level message. When the data access request includes the override message, the method further includes processing the data access request.

Abstract: A computer-implemented method includes: monitoring, by a computing device, computing resource utilization by a plurality of virtual computing components sharing a same kernel; monitoring, by the computing device, transaction counts produced by the plurality of virtual computing components; determining, by the computing device, that the transaction counts increase by less than a threshold number as the computing resource utilization increases; and creating, by the computing device, an additional virtual computing component on a separate kernel based on determining that the transaction counts increase by less than a threshold number as the computing resource utilization increases.

Abstract: A data processor is disclosed in which groups of execution threads can execute a set of instructions in lockstep, and in which a plurality of execution lanes can perform processing operations for the execution threads. Two or more execution threads of a thread group are issued to the same execution lane for execution. The two or more execution threads can then be processed by the execution lane successively, such that the execution lane performs the same processing operation successively. This can have the effect of reducing signal transitions, such that the overall energy consumption of the data processor can be reduced.

Abstract: A request to read data from a location associated with a memory component is received. The request is assigned a first tag, the first tag having a first identifier of a first buffer to store data read from the location. The request to read data is determined to collide with an earlier request to write data to the location. The earlier request is assigned a second tag, the second tag having a second identifier of a second buffer to store data to write to the location. An attempt to lock the second tag and the second buffer for the request to read data is made. The request to read data is fulfilled from the second buffer in response to a successful attempt to lock the second tag and the second buffer.

Abstract: A graphics processing unit may, in accordance with a kernel, determine that at least a first packet is written to a memory buffer of the graphics processing unit by a network interface card via a direct memory access, process the at least the first packet in accordance with the kernel, and provide a first notification to a central processing unit that the at least the first packet is processed in accordance with the kernel. The graphics processing unit may further determine that at least a second packet is written to the memory buffer by the network interface card via the direct memory access, process the at least the second packet in accordance with the kernel, where the kernel comprises a persistent kernel, and provide a second notification to the central processing unit that the at least the second packet is processed in accordance with the kernel.

Abstract: This patent specification relates to apparatus, systems, methods, and related computer program products for providing home security/smart home objectives. More particularly, this patent specification relates to a plurality of devices, including intelligent, multi-sensing, network-connected devices, that communicate with each other and/or with a central server or a cloud-computing system to provide any of a variety of useful home security/smart home objectives.

Abstract: A method includes generating a first lock requests, each for transmission to a storage unit, where each first lock request indicates a first encoded data slice. First ballots are received, each of the first ballots corresponds to a storage unit, each of the first ballots indicates a first ranking of first requesting entities that includes the DST processing unit. First election result data is generated based on the first ballots. The first election result data indicates a first winner. When the first winner is the DST processing unit, slice access requests are generated in response to the first election result data indicating that the first winner is the DST processing unit, each for transmission to one of the storage units, where each of the slice access requests indicates the first encoded data slice.

Abstract: A processing system includes a processing core to execute a virtual machine (VM) comprising a guest operating system (OS) and a memory management unit, communicatively coupled to the processing core, comprising a storage device to store an extended page table entry (EPTE) comprising a mapping from a guest physical address (GPA) associated with the guest OS to an identifier of a memory frame, a first plurality of access right flags associated with accessing the memory frame in a first page mode referenced by an attribute of a memory page identified by the GPA, and a second plurality of access right flags associated with accessing the memory frame in a second page mode referenced by the attribute of the memory page identified by the GPA.

Abstract: The invention provides for a database management system (100, 400) comprising a container management system (102). The container management system comprises: a container management system memory (106) for storing machine executable instructions (114) and a container management system processor (104).

Abstract: Methods, systems, and computer-readable storage media for automatically detecting potential performance degradation in a data analytics system including multiple servers, actions include determining a threshold performance score for each server of the multiple servers during an initial period, the threshold performance scores being determined at least partially based on a report generated by a respective server, and, after the initial period, and for each server: intermittently calculating a performance score, comparing the performance score to the threshold performance score to determine whether a violation indicating performance degradation occurs, and transmitting a notification to report consecutive violations.

Abstract: Technologies for contention-aware cloud compute scheduling include a number of compute nodes in a cloud computing cluster and a cloud controller. Each compute node collects performance data indicative of cache contention on the compute node, for example, cache misses per thousand instructions. Each compute node determines a contention score as a function of the performance data and stores the contention score in a cloud state database. In response to a request for a new virtual machine, the cloud controller receives contention scores for the compute nodes and selects a compute node based on the contention score. The cloud controller schedules the new virtual machine on the selected compute node. The contention score may include a contention metric and a contention score level indicative of the contention metric. The contention score level may be determined by comparing the contention metric to a number of thresholds. Other embodiments are described and claimed.

Abstract: A method of operating a system comprising multiple processor tiles divided into a plurality of domains wherein within each domain the tiles are connected to one another via a respective instance of a time-deterministic interconnect and between domains the tiles are connected to one another via a non-time-deterministic interconnect. The method comprises: performing a compute stage, then performing a respective internal barrier synchronization within each domain, then performing an internal exchange phase within each domain, then performing an external barrier synchronization to synchronize between different domains, then performing an external exchange phase between the domains.

Abstract: First/second memories hold rows of N weight/data words. Each of N processing units (PU) of index J have a register, an accumulator having an output, an arithmetic unit that performs an operation thereon to accumulate a result, the first input receives the output of the accumulator, the second input receives a respective first memory weight word, the third input receives a respective data word output by the register, and multiplexing logic receives a respective second memory data word and a data word output by the register of PU J?1 and outputs a selected data word to the register. PU J?1 for PU 0 is PU N?1. The multiplexing logic of PU 0 also receives the data word output by the register of PU (N/2)?1. The multiplexing logic of PU N/2 also receives the data word output by the register of PU N?1.

Abstract: First/second memories hold rows of N weight/data words. Each of N processing units (PU) of index J have a register, an accumulator having an output, an arithmetic unit that performs an operation thereon to accumulate a result, the first input receives the output of the accumulator, the second input receives a respective first memory weight word, the third input receives a respective data word output by the register, and multiplexing logic receives a respective second memory data word and a data word output by the register of PU J?1 and outputs a selected data word to the register. PU J?1 for PU 0 is PU N?1. The multiplexing logic of PU N/4 also receives the data word output by the register of PU (3N/4)?1. The multiplexing logic of PU 3N/4 also receives the data word output by the register of PU (N/4)?1.

Abstract: A memory address translation apparatus comprises a translation data store to store one or more instances of translation data. Each instance provides address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicates a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space. When a given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data store, detector circuitry retrieves one or more further instances of the translation data and translation circuitry applies the translation defined by a detected instance of the translation data to the given virtual memory address.

Abstract: Various systems and methods for detecting and preventing side-channel attacks, including attacks aimed at discovering the location of KASLR-randomized privileged code sections in virtual memory address space, are described. In an example, a computing system includes electronic operations for detecting unauthorized attempts to access kernel virtual memory pages via trap entry detection, with operations including: generating a trap page with a physical memory address; assigning a phantom page at an open location in the privileged portion of the virtual memory address space; generating a plurality of phantom page table entries corresponding to an otherwise-unmapped privileged virtual memory region; placing the trap page in physical memory and placing the phantom page table entry in a page table map; and detecting an access to the trap page via the phantom page table entry, to trigger a response to a potential attack.

Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts during which the first processor core is not able to execute threads other than the first thread, or (2) an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread. Prioritization of selected messages sent over interconnection circuitry configured to connect each processor core to a memory system of the processor is preserved. The selected messages associated with instructions identified as being associated with an unlock operation are prioritized over messages associated with instructions identified as being associated with a lock operation.

Abstract: The present invention relates to a system for simultaneous forensic acquisition and analysis of data from a target data repository. The system comprises a source agent in communication with the target data repository. The source agent is incapable of writing to the target data repository and is configured to read a portion of the target data repository. The system further comprises an investigator computer having a processor configured to send at least one prioritized read command to the source agent to schedule a read of the target data repository based on a predetermined priority. A data sink is configured to store at least a partial forensic image of the target data repository based on the data read by said source agent.

Abstract: A command process load balancing system performs load balancing of received commands among a number of server processes to resolve access contention for virtual software resources. These contentions are resolved through a history recording unit that records a history including contents of a processed command and a response time of a process for the command into a history database. A prediction unit predicts, in a case where a set of commands to be processed is assigned to a server process, whether or not a load that is equal to or higher than a reference value is applied, on the basis of the history recorded in the history database. An assigning unit assigns at least one command included in the set of commands to be processed to a different server process, in accordance with prediction that a load that is equal to or higher than the reference.

Abstract: Disclosed is a heterogeneous field devices control management system based on an industrial internet operating system. In order to solve the problems that it is difficult to add new heterogeneous field devices to an existing system, as well as that the system has low security and a real-time performance, on one hand, according to embodiments of the present disclosure, on the basis of the differences of real-time requirements of services operated by heterogeneous field devices, a real-time virtual machine processes a real-time service and a non-real-time virtual machine processes a non-real-time service, thus different operating environments could be customized for a real-time service and a non-real-time service, avoiding the situation that when a system upgrade is made for a non-real-time service or a non-real-time virtual service fails, a real-time service is also affected, service isolation is realized, and, stability and reliability of industrial field control are enhanced.

Abstract: A computer implemented method for avoiding false activation of hang avoidance mechanisms of a system is provided. The computer implemented method includes receiving, by a nest of the system, rejects from a processor core of the system. The rejects are issued based on a cache line being locked by the processor core. The computer implemented method includes accumulating the rejects by the nest. The computer implemented method includes determining, by the nest, when an amount of the rejects accumulated by the nest has met or exceeded a programmable threshold. The computer implemented method also includes triggering, by the nest, a global reset to counters of the hang avoidance mechanisms of a system in response to the amount meeting or exceeding the programmable threshold.

Abstract: Methods and systems enabling rapid application development, verification, and deployment requiring only knowledge of high level languages. Two aspects of the disclosed methods and systems are called Machine Intelligence and Learning for Graphic chip Accessibility (MILeGrA) and Machine Intelligence and Learning for Graphic chip Execution (MILeGrE). Using MILeGrA and MILeGrE, high-level language programmers do not need to learn complex coprocessor programming languages, but can still use coprocessors (e.g., GPU processors) to benefit from results-in-seconds big data capabilities through the translation of coprocessor-unaware code to coprocessor-aware code. Execution of such coprocessor-unaware code on coprocessors includes parsing the coprocessor-unaware code to generate intermediate code, analyzing the intermediate code to determine a model for coprocessor-aware code generation, and generating coprocessor-aware code based on the model using machine learning techniques.

Abstract: The invention introduces a method for scheduling and executing commands in a flash memory, performed by a processing unit, including at least the following steps: reading information stored in a command profile space to determine whether a priority command is present in a command queue; de-queuing the priority command from the command queue and executing the priority command when the priority command is present in the command queue; and using a scheduling algorithm to select a simple read/write command from the command queue and executing the simple read/write command when no priority command is present in the command queue.

Abstract: Provided is a control device for a system that includes a plurality of correlated function blocks. The control device includes: a setting unit for setting an evaluation function about a function block state in association with each of the plurality of function blocks; a virtual evaluation function creating unit for setting, as a virtual function block, a group of a predetermined function blocks selected from the plurality of function blocks, and creating a virtual evaluation function by using the evaluation functions of the function blocks contained in the virtual function block; and a system control unit for controlling the system based on the virtual evaluation function.

Abstract: Embodiments disclosed herein are related to systems, methods, and computer readable medium for allocating one or more system resources for the exclusive use of an application. The embodiments include receiving a request for an exclusive allocation of one or more system resources for a first application, the one or more system resources being useable by the first application and one or more second applications; determining an appropriate amount of the one or more system resources that are to be allocated exclusively to the first application; and partitioning the one or more system resources into a first portion that is allocated for the exclusive use of the first application and a second portion that is not allocated for the exclusive use of the first application, the second portion being available for the use of the one or more second applications.

Abstract: Techniques for controlling access to shared resources may include receiving multiple requests to access shared information associated with an identifier. For each of the requests, an entry in a linked list can be allocated to the request, and each entry can be associated with the identifier. The shared information associated with the identifier can be retrieved, and stored in each entry associated with the identifier. A conflict indicator is set in each entry to indicate whether the shared information is available for the request corresponding to the entry. The shared information stored in each entry is provided for each request after the conflict indicator in the corresponding entry indicates the shared information is available for the request.

Abstract: A memory system comprises a memory device coupled to a memory controller, the memory controller for receiving one or more memory requests from one or more core devices via an interconnect bus. The memory controller tracks utilization of the interconnect bus by tracking a selection of the one or more memory requests with fetched data from the one or more memory devices and waiting for scheduling to return on the interconnect bus during a time window. The memory controller, responsive to detecting utilization of the interconnect bus during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of the fetched data to be returned with at least one read request from among the selection of one or more memory requests, the reduced data size selected from among at least two read data size options for the at least one read request of a maximum read data size and the reduced read data size that is less than the maximum read data size.

Abstract: A multi-tenant virtual machine infrastructure (MTVMI) allows multiple tenants to independently access and use a plurality of virtual computing resources via the Internet. Within the MTVMI, different tenants may define unique configurations of virtual computing resources and unique rules to govern the use of the virtual computing resources. The MTVMI may be configured to provide valuable services for tenants and users associated with the tenants.

Abstract: An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.