Abstract: Methods and systems enabling rapid application development, verification, and deployment requiring only knowledge of high level languages. Two aspects of the disclosed methods and systems are called Machine Intelligence and Learning for Graphic chip Accessibility (MILeGrA) and Machine Intelligence and Learning for Graphic chip Execution (MILeGrE). Using MILeGrA and MILeGrE, high-level language programmers do not need to learn complex coprocessor programming languages, but can still use coprocessors (e.g., GPU processors) to benefit from results-in-seconds big data capabilities through the translation of coprocessor-unaware code to coprocessor-aware code. Execution of such coprocessor-unaware code on coprocessors includes parsing the coprocessor-unaware code to generate intermediate code, analyzing the intermediate code to determine a model for coprocessor-aware code generation, and generating coprocessor-aware code based on the model using machine learning techniques.

Abstract: The invention introduces a method for scheduling and executing commands in a flash memory, performed by a processing unit, including at least the following steps: reading information stored in a command profile space to determine whether a priority command is present in a command queue; de-queuing the priority command from the command queue and executing the priority command when the priority command is present in the command queue; and using a scheduling algorithm to select a simple read/write command from the command queue and executing the simple read/write command when no priority command is present in the command queue.

Abstract: Provided is a control device for a system that includes a plurality of correlated function blocks. The control device includes: a setting unit for setting an evaluation function about a function block state in association with each of the plurality of function blocks; a virtual evaluation function creating unit for setting, as a virtual function block, a group of a predetermined function blocks selected from the plurality of function blocks, and creating a virtual evaluation function by using the evaluation functions of the function blocks contained in the virtual function block; and a system control unit for controlling the system based on the virtual evaluation function.

Abstract: Embodiments disclosed herein are related to systems, methods, and computer readable medium for allocating one or more system resources for the exclusive use of an application. The embodiments include receiving a request for an exclusive allocation of one or more system resources for a first application, the one or more system resources being useable by the first application and one or more second applications; determining an appropriate amount of the one or more system resources that are to be allocated exclusively to the first application; and partitioning the one or more system resources into a first portion that is allocated for the exclusive use of the first application and a second portion that is not allocated for the exclusive use of the first application, the second portion being available for the use of the one or more second applications.

Abstract: Techniques for controlling access to shared resources may include receiving multiple requests to access shared information associated with an identifier. For each of the requests, an entry in a linked list can be allocated to the request, and each entry can be associated with the identifier. The shared information associated with the identifier can be retrieved, and stored in each entry associated with the identifier. A conflict indicator is set in each entry to indicate whether the shared information is available for the request corresponding to the entry. The shared information stored in each entry is provided for each request after the conflict indicator in the corresponding entry indicates the shared information is available for the request.

Abstract: A memory system comprises a memory device coupled to a memory controller, the memory controller for receiving one or more memory requests from one or more core devices via an interconnect bus. The memory controller tracks utilization of the interconnect bus by tracking a selection of the one or more memory requests with fetched data from the one or more memory devices and waiting for scheduling to return on the interconnect bus during a time window. The memory controller, responsive to detecting utilization of the interconnect bus during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of the fetched data to be returned with at least one read request from among the selection of one or more memory requests, the reduced data size selected from among at least two read data size options for the at least one read request of a maximum read data size and the reduced read data size that is less than the maximum read data size.

Abstract: A multi-tenant virtual machine infrastructure (MTVMI) allows multiple tenants to independently access and use a plurality of virtual computing resources via the Internet. Within the MTVMI, different tenants may define unique configurations of virtual computing resources and unique rules to govern the use of the virtual computing resources. The MTVMI may be configured to provide valuable services for tenants and users associated with the tenants.

Abstract: An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

Abstract: A system and method can support transaction processing in a transactional environment. A transactional system operates to route a request to a transactional server, wherein the transactional server is connected to a resource manager (RM) instance. Furthermore, the transactional system can assign an affinity context to the transactional server, wherein the affinity context indicates the RM instance that the transactional server is associated with, and the transactional system can route one or more subsequent requests that are related to the request to the transactional server based on the affinity context.

Abstract: Embodiments herein disclose a method and a base station for accessing a channel of an unlicensed band in a wireless communication network. The method includes maintaining a plurality of virtual stations by the base station in the wireless communication network based on a value. Further, the method includes contending to access the channel using the plurality of virtual stations. Each virtual station in the plurality of virtual stations includes a contention window and a counter value.

Abstract: A method and apparatus is provided for selecting power preference information based on network usage information used for a background process of a terminal. The power preference information selection method of the present disclosure includes measuring background network usage of a terminal, acquiring network usage information of the terminal when the background network usage exceeds a predetermined threshold, selecting the power preference information based on the network usage information, and transmitting the power preference information to the base station.

Abstract: A footprints device includes an input module and an output module. The input module receives a request for footprint data. The footprint data relates to names of users. The output module sends the footprint data to an address book. The footprint data is marked to indicate when at least one of the names of the users is a contact of the address book.

Abstract: Methods, systems and computer readable media for efficient state change support for hierarchical data models in a virtualized system are described. In some implementations, the method can include determining a system status including a system-level bit masked word having a plurality of bits, each bit corresponding to a status of a different hierarchical level of the system, and receiving a change notification. The method can also include querying an entity at a lower hierarchy level if a cascaded state change is identified for that entity. The method can further include continuing to query one or more entities in successively lower hierarchy levels so long as a cascaded state change is identified for a corresponding entity in a lower hierarchy level. The method can also include determining the current status for one or more entities having a changed status.

Abstract: Technologies for contention-aware cloud compute scheduling include a number of compute nodes in a cloud computing cluster and a cloud controller. Each compute node collects performance data indicative of cache contention on the compute node, for example, cache misses per thousand instructions. Each compute node determines a contention score as a function of the performance data and stores the contention score in a cloud state database. In response to a request for a new virtual machine, the cloud controller receives contention scores for the compute nodes and selects a compute node based on the contention score. The cloud controller schedules the new virtual machine on the selected compute node. The contention score may include a contention metric and a contention score level indicative of the contention metric. The contention score level may be determined by comparing the contention metric to a number of thresholds. Other embodiments are described and claimed.

Abstract: The present invention realizes a functional safety of a multiprocessor system without tightly coupling processor elements. When causing a plurality of processor elements to execute the same data processing and realizing a functional safety of the processor element, there is adopted a bus interface unit that performs control of performing safety measure processing when the non-coincidence of access requests issued from the processor elements has been fixed, and of starting access processing responding the access request when these access requests coincide with one another.

Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying and synchronization requests of a plurality of concurrently executing hardware threads are received in a shared queue. The plurality of storage-modifying requests includes a translation invalidation request of an initiating hardware thread, and the synchronization requests includes a synchronization request of the initiating hardware thread. The translation invalidation request is broadcast such that the translation invalidation request is received and processed by the plurality of processor cores to invalidate any translation entry that translates a target address of the translation invalidation request.

Abstract: This disclosure relates to a geographically distributed, multi-master system for storing data records, and associated methods and computer-readable media for replicating data records across geographically distributed data stores of the system in a manner that achieves consistency between data stored in geographically distributed regions as well as deterministic data replication.

Abstract: Aspects disclosed relate to a priority-based access of compressed memory lines in a processor-based system. In an aspect, a memory access device in the processor-based system receives a read access request for memory. If the read access request is higher priority, the memory access device uses the logical memory address of the read access request as the physical memory address to access the compressed memory line. However, if the read access request is lower priority, the memory access device translates the logical memory address of the read access request into one or more physical memory addresses in memory space left by the compression of higher priority lines. In this manner, the efficiency of higher priority compressed memory accesses is improved by removing a level of indirection otherwise required to find and access compressed memory lines.

Abstract: Integrated circuits may include memory interface circuitry operable to communicate with memory. The memory interface circuitry may include a memory controller and a memory interface circuit. The memory controller may fulfill memory access requests using the memory interface circuit. The memory controller may operate based on controller clock cycles of a controller clock, whereas the memory interface circuit may operate based on memory clock cycles of a memory clock. Each controller clock cycle may have a set of corresponding memory clock cycles. The memory interface circuitry may be configured using logic design computing equipment. The logic design computing equipment may identify memory timing requirements and controller latency requirements. The computing equipment may determine a command placement configuration that satisfies the timing and latency requirements. The computing equipment may configure the integrated circuit with the command placement configuration.

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory.

Abstract: A cache memory control procedure has: cache area allocating including allocating, in response to an acquisition request, and according to an effective cache usage degree that is based on a memory access frequency and a difference between a cache hit rate in a case where the dedicated cache area is allocated and a cache hit rate in a case where a shared cache area in the cache memory is allocated, the dedicated cache area for a higher effective cache usage degree and the shared cache area for a lower effective cache usage degree; and releasing the dedicated cache area which is allocated, in response to a release request which is issued during execution of a process by the processor and requests the release of the allocated dedicated cache area.

Abstract: A nonvolatile memory device includes a memory cell array including a data cell area, and a mode cell area that stores write mode information of the data cell area, a mode information storage block storing previous write mode information read out from the mode cell area in a previous read operation, and a control logic reading out the write mode information from the mode cell area comparing the read-out write mode information and the previous write mode information, and reading the data cell area in a read mode selected based on a comparison result.

Abstract: In an embedded system, there are a plurality of data requesting devices, a plurality of data sources and a bus fabric interconnecting the data requesting devices and the data sources, wherein the bus fabric comprises a plurality of bus components. Some or all of the data sources and arbitration devices associated with the bus components resolve contentions between data bursts by selecting a first one of the contending data bursts; determining a length of a critical section of the first selected data burst; and processing the critical section of the selected data burst. Then, a second one of the contending data bursts is selected, a length of a critical section of the second selected data burst is determined, and the critical section of the second selected data burst is processed before a non-critical section of the selected data burst.

Abstract: An evaluation value DS for evaluating responsiveness of a first node when no loads are being transferred, an evaluation value Dn for evaluating responsiveness of a path P connecting between the first and second nodes assuming that loads are being transferred, and an evaluation value Dr for evaluating responsiveness of the second node N2 assuming that the second node has received a load from the first node are calculated. Whether or not to transfer the load is determined depending upon comparison results of magnitude of DS and a sum of Dr+Dn.

Abstract: Technologies for contention-aware cloud compute scheduling include a number of compute nodes in a cloud computing cluster and a cloud controller. Each compute node collects performance data indicative of cache contention on the compute node, for example, cache misses per thousand instructions. Each compute node determines a contention score as a function of the performance data and stores the contention score in a cloud state database. In response to a request for a new virtual machine, the cloud controller receives contention scores for the compute nodes and selects a compute node based on the contention score. The cloud controller schedules the new virtual machine on the selected compute node. The contention score may include a contention metric and a contention score level indicative of the contention metric. The contention score level may be determined by comparing the contention metric to a number of thresholds. Other embodiments are described and claimed.

Abstract: A system and method can support transaction processing in a transactional environment. A transactional system operates to route a request to a transactional server, wherein the transactional server is connected to a resource manager (RM) instance. Furthermore, the transactional system can assign an affinity context to the transactional server, wherein the affinity context indicates the RM instance that the transactional server is associated with, and the transactional system can route one or more subsequent requests that are related to the request to the transactional server based on the affinity context.

Abstract: A partitioned key-value store is provided that supports atomic memory operations. A server performs a memory operation in a partitioned key-value store by receiving a request from an application for at least one atomic memory operation, the atomic memory operation comprising a memory address identifier; and, in response to the atomic memory operation, performing one or more of (i) reading a client-side memory location identified by the memory address identifier and storing one or more key-value pairs from the client-side memory location in a local key-value store of the server; and (ii) obtaining one or more key-value pairs from the local key-value store of the server and writing the obtained one or more key-value pairs into the client-side memory location identified by the memory address identifier. The server can perform functions obtained from a client-side memory location and return a result to the client using one or more of the atomic memory operations.

Abstract: A memory controller for heterogeneous computer processors dynamically adjusts access priorities by the different processors to maximize performance in the execution of a single parallel application program on both processor architectures. In one embodiment, the memory controller predicts sequential memory accesses by the processor having higher memory latency or fewer access requests to lockout the other processor during those sequences for improved implementation of the intended prioritization.

Abstract: A vector data access unit includes data access ordering circuitry, for issuing data access requests indicated by elements of earlier and a later vector instructions, one being a write instruction. An element indicating the next data access for each of the instructions is determined. The next data accesses for the earlier and the later instructions may be reordered. The next data access of the earlier instruction is selected if the position of the earlier instruction's next data element is less than or equal to the position of the later instruction's next data element minus a predetermined value. The next data access of the later instruction may be selected if the position of the earlier instruction's next data element is higher than the position of the later instruction's next data element minus a predetermined value. Thus data accesses from earlier and later instructions are partially interleaved.

Abstract: In response to a warning that power may be interrupted, a non-volatile data storage sub-system of a host computer system re-orders machine readable instructions that the non-volatile data storage sub-system is going to perform. This re-ordering of instructions decreases the probability that important data will be lost. The re-ordering of instructions is performed according to rules.

Abstract: Disclosed are various embodiments for balancing a load on a queue among multiple consumers. A target polling hit rate is derived for at least one queue from a consumer load. The consumer load on the at least one queue is adjusted responsive to a change in an observed polling hit rate for the at least one queue.

Abstract: A memory access control system includes a plurality of operators, a first memory, and a second memory. The plurality of operators are configured to execute different arithmetic operations. The first memory has a shared region accessible from the plurality of operators. The second memory is configured to cause any one of the plurality of operators to access. One of the operators is configured to access the second memory to load required data and execute a process concurrently with loading data required for a separate other process to cause the first memory to hold the data required for the separate other process.

Abstract: Concepts and technologies are described herein for providing status of site access requests. In accordance with the concepts and technologies disclosed herein, a user attempts to access functionality of a server application that is limited to authorized users. In response to the access attempt, the server application determines if the user is authorized to access the functionality and if the user has previously requested access to the functionality. If the user has not previously requested access to the application, the server application can present a user interface to the user for requesting access to the server application. If the user has previously requested access to the application, the server application can present an indication that an access request already exists, history and status information associated with the access request, and/or an interface for submitting messages to the site owner or other entity.

Abstract: Alert management may include receiving, by a monitoring module from one or more disparate monitored sources, an alert, where the alert is a data structure that includes a plurality of fields; storing, by the monitoring module, the alert in a database; processing, by the monitoring module periodically at predefined intervals, the database, including identifying, in dependence upon a predefined ruleset, one or more alerts; storing, by the monitoring module, the identified alerts in a staging table, including creating, for each of the identified alerts, a primary key in dependence upon the fields of the identified alert; populating, by the monitoring module for each of the alerts stored in the staging table, one or more attribute fields of the alert in dependence upon the created primary key of the alert; and storing, by the monitoring module, the populated alerts in the database.

Abstract: An electronic device includes a target selection unit, a priority determination unit, and a mirroring execution unit. The target selection unit is configured to select, as a mirroring target, a setting value of each of items of the electronic device if the setting value is different from an initial value. The priority determination unit is configured to determine a priority of mirroring, designated for a setting value serving as the mirroring target. The mirroring execution unit is configured to perform the mirroring so as to cause a setting value, whose determined priority is relatively high, to remain on a priority basis.

Abstract: A memory device has a storage array having a plurality of accessible memory banks and a configurable first set of memory segments. The plurality of accessible memory banks include a second set of memory segments. During a first mode of operation, the first set of memory segments is configured to be an additional accessible memory bank. During a second mode of operation, a pair of memory segments in the first set of memory segments are configured to be an additional set of memory segments in each of the plurality of accessible memory banks.

Abstract: A storage management application of a storage array is operable to create a new volume on the storage device array, and to automatically configure, responsive to user selection of an application protection profile, data protection services for application data to be stored on the volume, and/or, responsive to user selection of an application performance profile, application specific performance parameters. The application protection profile specifies scheduling and replication of snapshots for application data to be stored on the volume, and the application performance profile specifies performance parameters such as setting a block size, enabling or modifying a data caching algorithm, turning on or modifying data compression, etc. The scheduling, replication and/or application performance may be managed by a daemon associated with the storage management application which communicates with an agent associated with an application server on which the application executes.

Abstract: A CPU 80 controls data transfer from a first device to a second device in a kernel mode. A main memory 90 stores data to be transferred from the first device to the second device. The CPU 80 has: a first device control means 81 which controls the first device; a second device control means which controls the second device; and a data transfer control means 83 which makes a read instruction which instructs the first device control means 81 to store data read from the first device in the main memory 3, and makes a write instruction which instructs the second device control means 82 to write the data stored in the main memory 3 in the second device.

Abstract: A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.

Abstract: Apparatuses, systems, and methods are disclosed for executing data transformations for a data storage device. A storage controller module controls a storage operation for a set of data within a data storage device. A transformation module determines to apply a data transformation to the set of data in response to a transformation indicator. A processing module applies the data transformation to the set of data internally on the data storage device prior to completing the storage operation.

Abstract: Processors and methods disclosed herein include a cache memory unit, n processor cores where n?1, a controller connected to the cache memory unit and to each of the n processor cores, and n obstruction monitoring units, where each obstruction monitoring unit is connected to the controller and to a different one of the n processor cores, and where during operation of the electronic processor, each obstruction monitoring unit is configured to detect an obstruction corresponding to an operation from the processor core connected to the obstruction monitoring unit before the operation executes in the cache memory unit.

Abstract: A method managing execution of recovery code in a memory system includes; upon detecting a read error using a CPU and firmware to execute recovery code defining a read recovery operation including a read retry operation, during execution of the recovery code, generating a read request directed to the read retry operation, and immediately thereafter terminating execution of the recovery code, and thereafter, only upon receiving an asynchronous interrupt from the memory controller following completion of the read retry operation, the CPU resumes execution of the recovery code by the firmware, otherwise the CPU performs another task unrelated to execution of the recovery code.

Abstract: A method for implementing embedded dynamic random access memory (eDRAM) refreshing in a high performance cache architecture. The method includes receiving a memory access request, via a cache controller, from a memory refresh requestor, the memory access request for a memory address range in a cache memory. The method also includes detecting that the cache memory located at the memory address range is available to receive the memory access request and sending the memory access request to a memory request interpreter. The method further includes receiving the memory access request from the cache controller, determining that the memory access request is a request to refresh contents of the memory address range in the cache memory, and refreshing data in the memory address range.

Abstract: A method and system for reducing memory power usage are disclosed. The method and system comprise receiving at least one low-priority command and delaying execution of the at least one low-priority command until a predetermined event occurs, wherein the memory remains in a low-power mode until the predetermined event occurs.

Abstract: Examples are disclosed for context aware synchronization. A mutual exclusion (mutex) lock object or monitor may be created to enable threads to acquire a lock to access a shared data structure when executing a critical section of code. The mutex lock object may have at least a first input associated with a context via which the one or more threads execute the given critical block of code. The mutex lock object may then be stored in a shared memory and an indication as the where the mutex lock object was stored in the shared memory may be provided to a thread. The thread may use the mutex lock object to acquire the lock to access the shared data structure. Other mutex lock objects may be created in a similar manner to allow additional threads to acquire locks to access the shared data structure. Other examples are described and claimed.

Abstract: A system includes multiple master devices and at least one memory refresh scheduler. When a master device needs higher priority for memory access, the master device sends a dynamic priority signal to the memory refresh scheduler and in response, the memory refresh scheduler changes its policy for issuing refresh commands.

Abstract: A semiconductor memory device includes an I/O circuit suitable for inputting and outputting data signals, and a control logic suitable for controlling the I/O circuit. The control logic includes a flip-flop suitable for operating in response to a dock signal, which is irrelevant to the data signals, and feed a first output signal back, a first pulse generation circuit suitable for generating a data output control pulse in response to a second output signal of the flip-flop which is an inverted signal of the first output signal, and a second circuit suitable for generating a strobe signal in response to the second output signal.

Abstract: A method for using a pipelined L2 cache to implement memory transfers for a video processor. The method includes accessing a queue of read requests from a video processor. For each of the read requests, a determination is made as to whether there is a cache line hit corresponding to the request. For each cache line miss, a cache line slot is allocated to store a new cache line responsive to the cache line miss. An in-order set of cache lines is output to the video processor responsive to the queue of read requests.

Abstract: A memory refresh requestor, a memory request interpreter, a cache memory, and a cache controller on a single chip. The cache controller configured to receive a memory access request, the memory access request for a memory address range in the cache memory, detect that the cache memory located at the memory address range is available, and send the memory access request to the memory request interpreter when the memory address range is available. The memory request interpreter configured to receive the memory access request from the cache controller, determine if the memory access request is a request to refresh a contents of the memory address range, and refresh data in the memory address range when the memory access request is a request to refresh memory.

Abstract: Disclosed is a data managing method of a storage device which includes at least one nonvolatile memory device and a controller controlling the nonvolatile memory device. The data managing method includes receiving an input/output request and generating a section directing logical addresses based on the input/output request. The section is managed using section information, and the section information includes a start logical address corresponding to the input/output request, spatial locality information having the number of the directed logical addresses, and historical request information.