Abstract: Non-inclusive cache systems and methods are provided. In one embodiment a non-inclusive cache system is provided comprising a non-inclusive cache and a cache agent that receives a request for access to the non-inclusive cache and denies the request for access to the non-inclusive cache if the non-inclusive cache system exceeds a predetermined level of activity.

Abstract: A memory mapping apparatus for a multi-processing unit includes at least one memory matching unit configured to perform matching between a plurality of processing units and a plurality of memories, a memory controller configured to perform access control and arbitration for the respective memories, a memory mapping unit configured to include a window map for the respective processing units, make correspond the memories to the respective processing units with reference to the window map, and assign part of the entire address region of the corresponding memory, and a window map change unit configured to change a window map for a processing unit in which a request to use the memory has occurred in response to a request to use the memory from any one of the processing units.

Abstract: The methods and systems described herein provide for granting a virtual machine exclusive access to an optical disc drive responsive to a determination the virtual machine initiated a transaction with the optical disc drive. A drive manager maps an optical disc drive connected to the computing device to a plurality of virtual machines hosted by a hypervisor executed by the computing device. The drive manager intercepts a transaction stream generated by the optical disc drive and converts the transaction stream to a command stream. The drive manager determines, based on an analysis of the command stream, a first virtual machine of the plurality of virtual machines initiated a transaction with the optical disc drive. Responsive to the determination, the drive manager locks the optical disc drive to grant the first virtual machine exclusive access to the optical disc drive.

Abstract: Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations.

Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

Abstract: Disclosed herein is a processing network element (NE) comprising at least one receiver configured to receive a plurality of memory request messages from a plurality of memory nodes, wherein each memory request designates a source node, a destination node, and a memory location, and a plurality of response messages to the memory requests from the plurality of memory nodes, wherein each memory request designates a source node, a destination node, and a memory location, at least one transmitter configured to transmit the memory requests and memory responses to the plurality of memory nodes, and a controller coupled to the receiver and the transmitter and configured to enforce ordering such that memory requests and memory responses designating the same memory location and the same source node/destination node pair are transmitted by the transmitter in the same order received by the receiver.

Abstract: A method and device for maintaining data in a data storage system, comprising a plurality of data storage nodes, the method being employed in a storage node in the data storage system and comprising: monitoring and detecting, conditions in the data storage system that imply the need for replication of data between the nodes in the data storage system; initiating replication processes in case such a condition is detected, wherein the replication processes include sending multicast and unicast requests to other storage nodes, said requests including priority flags, receiving multicast and unicast requests from other storage nodes, wherein the received requests include priority flags, ordering the received requests in different queues depending on their priority flags, and dealing with requests in higher priority queues with higher frequency than requests in lower priority queues.

Abstract: Various embodiments of a system and method for handling network partitions in a cluster of nodes are disclosed. The system and method may use a set of arbitration servers that are ordered in a particular order. Client nodes in different partitions may send requests to the arbitration servers to attempt to win control of them. The client node that wins a majority of the arbitration servers may remain in the cluster, and the client nodes in the other partitions may exit the cluster. The first arbitration server may award control to whichever client node whose request for control is received first. The remaining arbitration servers may be configured to give preference to the winner of one or more of the previous arbitration servers to attempt to ensure that one of the client nodes wins a majority.

Abstract: A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Abstract: A method and apparatus for detecting and preemptively ameliorating potential logic unit thrashing in a storage system having multiple I/O requesters is disclosed. In response to detecting that each of two requesters has usable access to both of the active-passive pair of controllers, one of the active-passive pair of controllers is selected to be designated as an active resource controller. In response to detecting that one of the two requesters has usable access to only one of the active-passive pair of controllers, only one of the active-passive pair of controllers is selected to be designated as an active resource controller. In response to detecting that each of the two requesters has usable access only to different ones of the active-passive pair of controllers, one of the active-passive pair of controllers is selected to be designated as an active resource controller.

Abstract: Various embodiments of the present invention manage access to a cache memory. In or more embodiments a request for a targeted interleave within a cache memory is received. The request is associated with an operation of a given type. The target is determined to be available. The request is granted in response to the determining that the target is available. A first interleave availability table associated with a first busy time associated with the cache memory is updated based on the operation associated with the request in response to granting the request. A second interleave availability table associated with a second busy time associated with the cache memory is updated based on the operation associated with the request in response to granting the request.

Abstract: A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.

Abstract: Computer readable media, methods and apparatuses are disclosed that may be configured for sequentially reading data of a file stored on a storage medium. The disclosure also provides for alternating transferring of fixed size portions of the file data to a first buffer and a second buffer, alternating processing of data blocks of the fixed sized portions in parallel from the first and second buffers by a plurality of processing threads, and outputting the processed data blocks.

Abstract: A mechanism for accessing a cache memory is provided. With the mechanism of the illustrative embodiments, a processor of the data processing system performs a first execution a portion of code. During the first execution of the portion of code, information identifying which cache lines in the cache memory are accessed during the execution of the portion of code is stored in a storage device of the data processing system. Subsequently, during a second execution of the portion of code, power to the cache memory is controlled such that only the cache lines that were accessed during the first execution of the portion of code are powered-up.

Abstract: System and method for allocating memory resources are disclosed. The system utilizes a bus system coupled to a plurality of requestors and a plurality of memory systems coupled to the bus system. Each memory system includes a memory component and a memory management module including a value that represents access rights to the memory component. The memory management module is configured to receive an access request from a first requestor of the plurality of requestors and to grant access to the memory component only if the value indicates that the first requestor has access rights to the memory component. The memory management module is configurable to change the value to give the access rights to the memory component to a second requestor of the plurality of requestors.

Abstract: Techniques are described for using chunk stores as building blocks to construct larger chunk stores. A chunk store constructed of other chunk stores (a composite chunk store) may have any number and type of building block chunk stores. Further, the building block chunk stores within a composite chunk store may be arranged in any manner, resulting in any number of levels within the composite chunk store. The building block chunk stores expose a common interface, and apply the same hash function to content of chunks to produce the access key for the chunks. Because the access key is based on content, all copies of the same chunk will have the same access key, regardless of the chunk store that is managing the copy. In addition, no other chunk will have that same access key.

Abstract: The exemplary embodiments provide a computer-implemented method, apparatus, and computer-usable program code for managing memory. A notice of a shortage of real memory is received. For each active thread, the thread classification of the active thread is compared to a global hierarchy of thread classifications to determine a thread to affect. The global hierarchy of thread classifications defines the relative importance of each thread classification. An action to take for the determined thread is determined. The determined action is performed for the determined thread.

Abstract: According to an embodiment, a memory system includes a memory unit, a memory controller, a timer and a timer control unit. The memory unit has nonvolatile first and second chips capable of holding data. The memory controller transfers data received from host equipment simultaneously to the first and second chips. The timer measures a lapse of preset shift time. The timer control unit starts writing of data into the second chip immediately after the lapse of the shift time.

Abstract: A parallel access system including: a group of processing entities that comprises N processing entities; wherein N is a positive integer that exceeds one; a group of memory banks that stores K information elements; wherein the group of memory banks comprises N pairs of single access memory banks; each pair of memory banks comprises an even memory bank and an odd memory bank; wherein each pair of memory banks stores sub-set of K/N information elements; wherein an even memory bank of each pair of memory banks stores even address information elements of a certain sub-set of K/N information elements and an odd memory bank of each pair of memory banks stores odd address information elements of the certain sub-set of K/N information elements; wherein K/N is an even positive integer; and a non-blocking interconnect, coupled to the group of processing entities and to the group of memory banks; wherein during each fetch cycle each processing entity of the group of processing entities fetches a first information elemen

Abstract: A data read/write system includes a system clock, a single port memory, a cache memory that is separate from the single port memory, and a controller coupled to an instruction pipeline. The controller receives, via the instruction pipeline, first data to write to an address of the single port memory, and further receives, via the instruction pipeline, a request to read second data from the single port memory. The controller stores the first data in the cache memory, and retrieves the second data from either the cache memory or the single port memory during one or more first clock cycles of the system clock. The controller copies the first data from the cache memory and stores the first data at the address in the single port memory during a second clock cycle of the system clock that is different than the one or more first clock cycles.

Abstract: Disclosed is a method of storage tiering with minimal use of DRAM memory for header overhead that utilizes the beginning of the volume to store frequently accessed or hot data. A solid state storage device is placed at the beginning of a tiered volume and is used to store frequently accessed data. When data becomes less frequently accessed it is moved to a cold data storage area on a hard disk drive in the tiered volume. The data exchange is performed on a one-to-one basis reducing the amount and use of DRAM.

Abstract: Provided are memory control apparatus and methods for controlling data transfer between a memory controller and at least two logical memory busses connected to memory, comprising a memory controller; a buffer; a bidirectional data bus connecting the controller and the buffer; a control interface connecting the controller and the buffer, the buffer being connected to at least two logical memory busses for memory read and write operations, the buffer comprising data storage areas to buffer data between the controller and the logical memory busses, and logic circuits to decode memory interface control commands from the controller; and a data access and control bus connecting the buffer and each of the logical memory busses to control memory read and write operations.

Abstract: In accordance with the disclosed subject matter there are described techniques for segregating requests issued by threads running in a computer system.

Abstract: Available capacity of a specific memory block is secured as much as possible. A termination candidate process selection unit (204) selects, for each of a plurality of memory blocks, a plurality of processes as a termination candidate process group, a termination process decision unit (206) determines whether or not the selected termination candidate process group is to be terminated with priority over a currently held termination candidate process group, a process group termination possibility determination unit (205) determines whether of not the termination candidate process group determined to be terminated can be terminated, and the termination process decision unit (206) rewrites the currently held termination candidate process group to the termination candidate process group determined to be able to be terminated, and decides the currently held termination candidate process group as a process to be terminated when selection of a termination candidate process group is ended for all the memory blocks.

Abstract: A multi-user computer system and a remote control method for the multi-user computer system includes a remote controller, with an input unit that receives a remote-control password to remotely operate the computer, information on an OS booted when the remote-control password is input, a key input setting the computer in a mode wherein the remote-control password and the OS information are set, and a key input operating the computer, a microprocessor, a wireless transmitter, and a computer, with a wireless receiver, a microprocessor, and a BIOS that automatically loads an OS corresponding to the remote-control password stored in the memory when the received remote-control password stored in the wireless receiver and the remote-control password in the memory are the same.

Abstract: A memory arbiter minimizes latency of memory accesses in a system having multiple processors. The memory arbiter improves overall system performance by managing the memory requests from each processor individually before those requests are sent to a central memory arbiter for handling memory requests for the shared resources from the multiple processors. The local memory arbiter buffers the memory requests from a local processor, analyzes the buffered memory requests, and optimizes the requests by reordering commands according to a rule set, and by performing write merging and prefetch squashing in certain conditions.

Abstract: A processor processing method is executed by a memory controller, and includes determining based on a log of access of a shared resource by a first application, whether the first application running on a first processor operates normally; and causing a second processor to run a second application other than the first application upon the first application being determined to not be operating normally.

Abstract: In one embodiment, a system includes a memory and a first bridge unit for processor access with the memory coupled with an input-output bus and the memory. The first bridge unit is configured to receive requests from the input-output bus to read or write data receive requests from the MFNU to free memory and choose among the requests to send to the memory on a first memory bus. The system also includes a second bridge unit for packet data access with the memory coupled with a packet input unit, packet output unit, and the memory. The second bridge unit is configured to receive requests to write packet data from the packet input unit, receive requests to read packet data from the packet output unit, and choose among the requests from the packet input unit and the packet output unit to send to the memory on a second memory bus.

Abstract: A device may receive a request to read data from or write data to a memory that includes a number of memory banks. The request may include an address. The device may perform a mapping operation on the address to map the address from a first address space to a second address space, identify one of the memory banks based on the address in the second address space, and send the request to the identified memory bank.

Abstract: Various technologies and techniques are disclosed for providing type stability techniques to enhance contention management. A reference counting mechanism is provided that enables transactions to safely examine states of other transactions. Contention management is facilitated using the reference counting mechanism. When a conflict is detected between two transactions, owning transaction information is obtained. A reference count of the owning transaction is incremented. The system ensures that the correct transaction was incremented. If the owning transaction is still a conflicting transaction, then a contention management decision is made to determine proper resolution. When the decision is made, the reference count on the owning transaction is decremented by the conflicting transaction. When each transaction completes, the reference counts it holds to itself is decremented. Data structures cannot be deallocated until their reference count is zero.

Abstract: A data processing system is provided with a programmable memory protection unit 10 defining a plurality of programmable memory regions 2, 4, 6, 8 each with associated programmable memory attributes. A default memory protection unit 22 is provided and defines a plurality of default memory regions a, b, c, d, e each with associated default memory attributes. If a miss occurs in the programmable memory protection unit 10, and the memory access is a privileged level memory access, then the default memory protection unit 22 will return default memory attributes for that memory request.

Abstract: A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.

Abstract: Coordinating media requests from a plurality of sources that share a shared media resource is disclosed. One or more media requests requiring action by the shared media resource is received from one or more of the plurality of sources. Each received media request is placed in a queue of requests requiring action by the shared media resource. Media requests in the queue are serviced based at least in part on their relative importance.

Abstract: A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. As an example a system is discussed that includes a data transfer controller circuit operable to provide a read request to a storage device. The read request indicates a data set to be provided from the storage device and a processing priority of at least a portion of the data set.

Abstract: According to one aspect of embodiments, a multiprocessor system includes a cache memory corresponding to each of the processors, a hierarchy setting register in which the hierarchical level of each cache memory is set, an access control unit that controls access between each cache memory. The hierarchical level of the cache memory for each processor is stored in a rewritable hierarchy setting register. Each processor handles a cache memory corresponding to another processor as the cache memory having a deeper hierarchy than the cache memory corresponding to the each processor. As the result, each processor can access all the cache memories, and therefore the efficiency of cache memory utilization can be improved and the hierarchical level can be set so that the latency becomes optimal for each application.

Abstract: A method of arbitrating requests from bus masters for access to shared memory in order to reduce access latency, comprises looking ahead into currently scheduled requests to the shared memory and predicting latency of the requests based on characteristics of the currently scheduled requests, such as increasing page hit rate, or balancing read and write traffic. The requests are scheduled based at least in part on the predicted latency.

Abstract: A shared memory device is disclosed which includes: a plurality of processor elements; a plurality of memory modules configured to be accessible by the plurality of processor elements; and a connection device configured to enable a specific processor element out of the plurality of processor elements to access a specific memory module out of the plurality of memory modules; wherein the plurality of processor elements are allowed to access via the connection device a plurality of memory systems each constituted by at least one memory module; and wherein each of the plurality of memory systems accessible by different processor elements allows the plurality of memory modules to be partially shared and accessed by the different processor elements.

Abstract: A data storage device accepts queued read and write commands that have deadlines. The queued read and write commands are requests to access the data storage device. The deadlines of the queued read and write commands can be advisory deadlines or mandatory deadlines.

Abstract: Techniques are disclosed relating to maximizing utilization of memory systems within power constraints of the memory systems. In one embodiment, an integrated circuit may include multiple memory controllers and an arbitration unit. Each memory controller may be configured to generate requests to perform memory operations on one or more portions of memory. The arbitration unit may be configured to grant no more than a specified number of requests during a time window TW. In some embodiments, a voltage converter that supplies power to the memory system may be configured to supply power to perform no more than the specified number of requests during the time window TW. The arbitration unit may thus be used, in some embodiments, to ensure that the greatest possible number of the specified number of memory requests are granted during a given time window TW (without exceeding the specified number).

Abstract: Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address sequence is automatically modified to force a selected address to be fetched next by the IFU model. The instruction address sequence may be modified by inserting one or more new instruction addresses, or by jumping to a non-sequential address in the instruction address sequence. In exemplary implementations, the selected address is a corresponding address for an existing instruction already loaded in the IFU cache, or differs only in a specific field from such an address. The instruction address control is preferably accomplished without violating any rules of the processor architecture by sending a flush signal to the IFU model and overwriting an address register corresponding to a next address to be fetched.

Abstract: In at least one embodiment, a method includes locally scheduling a memory request requested by a thread of a plurality of threads executing on at least one processor. The memory request is locally scheduled according to a quality-of-service priority of the thread. The quality-of-service priority of the thread is based on a quality of service indicator for the thread and system-wide memory bandwidth usage information for the thread. In at least one embodiment, the method includes determining the system-wide memory bandwidth usage information for the thread based on local memory bandwidth usage information associated with the thread periodically collected from a plurality of memory controllers during a timeframe. In at least one embodiment, the method includes at each mini-timeframe of the timeframe accumulating the system-wide memory bandwidth usage information for the thread and updating the quality-of-service priority based on the accumulated system-wide memory bandwidth usage information for the thread.

Abstract: Embodiments of a method and apparatus for using graphics memory (also referred to as video memory) for non-graphics related tasks are disclosed herein. In an embodiment a graphics processing unit (GPU) includes a VRAM cache module with hardware and software to provide and manage additional cache resourced for a central processing unit (CPU). In an embodiment, the VRAM cache module includes a VRAM cache driver that registers with the CPU, accepts read requests from the CPU, and uses the VRAM cache to service the requests. In various embodiments, the VRAM cache is configurable to be the only GPU cache or alternatively, to be a first level cache, second level cache, etc.

Abstract: Method and apparatus for scheduling access requests for a multi-bank low-latency random read memory (LLRRM) device within a storage system. The LLRRM device comprising a plurality of memory banks, each bank being simultaneously and independently accessible. A queuing layer residing in storage system may allocate a plurality of request-queuing data structures (“queues”), each queue being assigned to a memory bank. The queuing layer may receive access requests for memory banks in the LLRRM device and store each received access request in the queue assigned to the requested memory bank. The queuing layer may then send, to the LLRRM device for processing, an access request from each request-queuing data structure in successive order. As such, requests sent to the LLRRM device will comprise requests that will be applied to each memory bank in successive order as well, thereby reducing access latencies of the LLRRM device.

Abstract: A method for measuring latencies caused by processing performed within a common resource is provided. A current latency value representing a time of residency of an IO request in a queue prior to receipt of acknowledgment from the common resource of completion of the IO request is received from a device comprising the queue, which maintains entries for IO requests that have been dispatched to and are pending at the common resource. An average latency value is calculated based in part on the current latency value. An adjusted capacity size for the queue is calculated based in part on the average latency value and the queue's capacity is set to the adjusted capacity size. IO requests are held in a buffer if the queue's capacity is full to reduce the effect of an amount of work transmitted to the common resource on current latency values provided by the device.

Abstract: A computer includes first and second processors, first and second I/O devices, a shared memory, and an interrupt controller. The first processor issues a control command for causing the first I/O device to read target data from the first apparatus and store the target data in the shared memory. The first I/O device reads the target data from the first apparatus and, transfers the target data to the shared memory, and generates an I/O complete interrupt. The interrupt controller delivers the generated I/O complete interrupt to the second processor. When the second processor receives the I/O complete interrupt, the second processor issues a control command for causing the second I/O device to read the target data from the shared memory and send the target data to the second apparatus. The second I/O device reads the target data from the shared memory and sends the target data to the second apparatus.

Abstract: In a data read-and-write controlling device, without waiting for confirmation that data is written in a RAM, data is written in a WER and an ADR, and at the same time, address information of the data is written in the RAM write-information table. That is, the data read-and-write controlling device associates an address retained at a data register of a write controlling unit with the value (a write request is present=“1”) of a write request that makes a request for writing data in the RAM, the value being retained in a write request register, and then causes the result to be stored in the RAM write-information table as the address information.

Abstract: A method, system, and apparatus for expanding the storage capacity of a data storage system are provided. According to one method, the physical storage devices that store the data and metadata for one or more logical disks are organized into a container. A logical disk segment is created within the container for each logical disk. When storage capacity is added through the addition of logical disks, a new logical disk segment is added to the end of the container for the new logical disk. When storage capacity is added through the addition of capacity to an existing logical disk, a new logical disk segment is added to the end of the container for the new logical disk segment within the logical disk. The devices within a container may be migrated between server computers or between CPUs with their associated mass storage controllers.

Abstract: A system and method utilize a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated with a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, a plurality of memory devices may be arranged in a memory package in a stacked die memory configuration.

Abstract: The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and size of the input buffers used to receive the data streams. This allows the device to employ large, relatively slow memory elements, thereby permitting large amounts of sequential data to be stored by the receiving device. Using control information that was written as the data was being stored in the memory banks, a reordering element is later able to retrieve the data elements from the plurality of memory banks, in an order that is different from that in which the stream was received, and to reassemble the data stream into the original sequence.