Abstract: Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations.

Abstract: A method for unidirectional communication between tasks includes providing a first task having access to an amount of virtual memory, blocking a communication channel portion of said first task's virtual memory, such that the first task cannot access said portion, providing a second task, having access to an amount of virtual memory equivalent to the first task's virtual memory, wherein a communication channel portion of the second task's virtual memory corresponding to the blocked portion of the first task's virtual memory is marked as writable, transferring the communication channel memory of the second task to the first task, and unblocking the communication channel memory of the first task.

Abstract: A method is provided for protecting a computer system, comprising: attaching a security descriptor to a process running on a processor of the computer system; associating with the security descriptor an isolation indicator that indicates the process runs in an isolation mode; calling a system routine by the isolated process that is also callable by a process that is not running in isolation mode; attempting to write to an object of a disk or a registry by the system routine called by the isolated process; determining whether the system routine is requesting the write on behalf of the isolated process or not; if the write is requested on behalf of the isolated process, then performing the write in a pseudo storage area; and if the write is requested on behalf of the non-isolated process, then performing the write in an actual storage area in which the disk or registry resides.

Abstract: System, method, and program to perform simultaneous read and write operations in a NAND-type memory device, including: assigning a first partition in a NAND-type memory device, wherein the first partition is configured to perform read operations on high priority read content; assigning a second partition in the NAND-type memory device, wherein the second partition is configured to perform read operations and write operations, wherein the read operations are performed on non-high priority read content; and controlling the first partition and second partition to operate in a simultaneous manner.

Abstract: An apparatus and system for protecting memory of a virtual guest includes initializing a virtual guest on a host computing system. The host computing system includes a virtual machine manager that manages operation of the virtual guest. The virtual guest includes a distinct operating environment executing in a virtual operation platform provided by the virtual machine manager. The method includes receiving an allocation of run-time memory for the virtual guest, the allocation of run-time memory comprising a portion of run-time memory of the host computing system. The method includes setting, by the virtual guest, at least a portion of the allocation of run-time memory to be inaccessible by the virtual machine manager.

Abstract: A method for operating a dynamic back-up storage system includes: providing a high speed memory including a first rank memory device and subsequent ranks of memory devices; providing a non-volatile memory for saving data from the high speed memory; and providing a control logic unit for controlling access, of a central processing unit that executes a program, from the high speed memory including restoring the subsequent ranks of memory devices while the central processing unit is executing the program from the first rank memory device.

Abstract: A method of declaring and using variables includes; determining whether variables are independent variables or common variables, declaring and storing the independent variables in a plurality of data structures respectively corresponding to the plurality of processors, declaring and storing the common variables in a shared memory area, allowing each one of the plurality of processors to simultaneously use the independent variables in a corresponding one of the plurality of data structures, and allowing only one of the plurality of processors at a time to use the common variables in the shared memory area.

Abstract: A system and method for controlling access to a shared storage device in a computing cluster having at least two nodes configured as cluster members provide fencing and quorum features without using the device controller hardware/firmware so fencing can be provided with storage devices that do not support disk reservation operations, such as with non-SCSI compliant disks. A polling thread on each node periodically reads a designated storage space on the shared storage device at a polling interval to determine if its corresponding node registration key is present, and halts the node if the key has been removed. A cluster membership agent removes a corresponding node registration key from the designated storage space of the shared storage device and publishes new membership information indicating that the corresponding node has departed the cluster only after delaying for a time period greater than the polling interval.

Abstract: A tamper resistant servicing Agent for providing various services (e.g., data delete, firewall protection, data encryption, location tracking, message notification, and updating software) comprises multiple functional modules, including a loader module (CLM) that loads and gains control during POST, independent of the OS, an Adaptive Installer Module (AIM), and a Communications Driver Agent (CDA). Once control is handed to the CLM, it loads the AIM, which in turn locates, validates, decompresses and adapts the CDA for the detected OS environment. The CDA exists in two forms, a mini CDA that determines whether a full or current CDA is located somewhere on the device, and if not, to load the full-function CDA from a network; and a full-function CDA that is responsible for all communications between the device and the monitoring server. The servicing functions can be controlled by a remote server.

Abstract: A lock mechanism can be supported in a transactional middleware system to protect transaction data in a shared memory when there are concurrent transactions. The transactional middleware machine environment comprises a semaphore provided by an operating system running on a plurality of processors. The plurality of processors operates to access data in the shared memory. The transactional middleware machine environment also comprises a test-and-set (TAS) assembly component that is associated with one or more processes. Each said process operates to use the TAS assembly component to perform one or more TAS operations in order to obtain a lock for data in the shared memory. Additionally, a process operates to be blocked on the semaphore and waits for a release of a lock on data in the shared memory, after the TAS component has performed a number of TAS operations and failed to obtain the lock.

Abstract: Solutions to a value recycling problem facilitate implementations of computer programs that may execute as multithreaded computations in multiprocessor computers, as well as implementations of related shared data structures. Some exploitations allow non-blocking, shared data structures to be implemented using standard dynamic allocation mechanisms (such as malloc and free). Some exploitations allow non-blocking, indeed even lock-free or wait-free, implementations of dynamic storage allocation for shared data structures. In some exploitations, our techniques provide a way to manage dynamically allocated memory in a non-blocking manner without depending on garbage collection. While exploitations of solutions to the value recycling problem that we propose include management of dynamic storage allocation wherein values managed and recycled tend to include values that encode pointers, they are not limited thereto.

Abstract: In one embodiment, the present invention includes a method for accessing a shared memory associated with a reader-writer lock according to a first concurrency mode, dynamically changing from the first concurrency mode to a second concurrency mode, and accessing the shared memory according to the second concurrency mode. In this way, concurrency modes can be adaptively changed based on system conditions. Other embodiments are described and claimed.

Abstract: A method and data processing system enables scheduling of atomic operations within a Peripheral Component Interconnect Express (PCIe) architecture during page migration. In at least one embodiment, firmware detects the activation of a page migration operation. The firmware notifies the I/O host bridge, which responds by setting an atomic operation stall (AOS) bit to a pre-established value that indicates that there is an ongoing migration within the memory subsystem of a memory page that is mapped to that I/O host bridge. When the AOS bit is set to the pre-established value, the I/O host bridge prevents/stalls any received atomic operations from completing. The I/O host bridge responds to receipt of receipt of an atomic operation by preventing the atomic operation from being initiated within the memory subsystem, when the AOS bit is set to the pre-established value. The AOS bit is reset when the migration operation has completed.

Abstract: One embodiment of the present invention sets forth a method for sharing graphics objects between a compute unified device architecture (CUDA) application programming interface (API) and a graphics API. The CUDA API includes calls used to alias graphics objects allocated by the graphics API and, subsequently, synchronize accesses to the graphics objects. When an application program emits a “register” call that targets a particular graphics object, the CUDA API ensures that the graphics object is in the device memory, and maps the graphics object into the CUDA address space. Subsequently, when the application program emits “map” and “unmap” calls, the CUDA API respectively enables and disables accesses to the graphics object through the CUDA API. Further, the CUDA API uses semaphores to synchronize accesses to the shared graphics object. Finally, when the application program emits an “unregister” call, the CUDA API configures the computing system to disregard interoperability constraints.

Abstract: Embodiments include a method comprising detecting addition of a new nonvolatile machine-readable medium to a data storage pool of nonvolatile machine-readable media. The method includes preventing from being performed a first operation of a file system that requires a first parameter that identifies a logical indication of a location within the nonvolatile machine-readable media for the file system, until logical indications of locations within the new nonvolatile machine-readable medium for the file system have been stored in the data storage pool. The method includes allowing to be performed, prior to logical indications of locations within the new nonvolatile machine-readable medium being stored in the data storage pool, a second operation of the file system that does not require a second parameter that identifies a logical indication of a location within the nonvolatile machine-readable media, wherein the second operation causes data to be written into the new nonvolatile machine-readable medium.

Abstract: A storage controller comprises a cache storage used as a cache of an external storage and a control processor coupled to the cache storage. The control processor comprises an internal access function and an external access function. The internal access function transmits a read command to the cache storage. The cache storage determines whether the read target data complying with the read command is stored in a physical storage device or not. If the result of the determination is negative, the external access function is executed while, if the result of the determination is positive, the external access function is not executed because the cache storage transmits the read target data to the internal access function without issuing a request to the external access function.

Abstract: An access control system (10) is disclosed for controlling access to data stored on at least one data storage medium (14) of a computing system. The access control system (10) comprises authentication means (25) to authenticate users permitted to access data stored in the at least one data storage medium (14) and database means (29) arranged to store data access profiles. Each data access profile is associated with a user permitted to access data stored in the at least one data storage medium (14), each data access profile includes information indicative of the degree of access permitted by a user to data stored in the at least one data storage medium (14), and each data access profile includes a master data access profile (M) and a current data access profile (C). The current data access profile (C) is modifiable within parameters defined by the master data access profile (M).

Abstract: A multi-port arbitration system has a write detection circuit coupled to each of a number of ports. An address coincidence detector is coupled to each of the ports. A deactivation pulse generator circuit is coupled to the address coincidence detector.

Abstract: Provided is an information processing apparatus and method of controlling same in which, when data transfer is performed among a plurality of control circuits, which control circuit is used to execute data transfer is controlled appropriately based on the transfer conditions of data transfer. To accomplish this, the apparatus has first and second control circuits, a request for data transfer performed between the first and second control circuits is acquired, the transfer conditions of the acquired data transfer are analyzed and which of the first and second control circuits is to execute the data transfer is selected.

Abstract: A Trusted Service Manager (TSM) receives via a first communication channel from a Service Provider (SP) a request (REQ(MIA)) that contains an application (MIA) together with a unique identifier of a mobile phone (MOB), particularly its telephone number. The mobile phone (MOB) is equipped with a memory device (MIF) that comprises multiple memory sectors being protected by sector keys. Preferably the memory device (MIF) is a MIFARE device. The TSM extracts the application (MIA) and the unique identifier from the received request, assigns destination sector(s) and associated sector key(s) of the memory device (MIF), compiles the application (MIA), the sector key(s) and the sector number(s) of the destination sector(s) into a setup-message (SU(MIA)), encrypts the setup-message and transmits it to either the mobile phone via a second communication channel or the Service Provider via the first communication channel (CN).

Abstract: Provided are a method and apparatus for controlling a shared memory, and a method of accessing the shared memory. The apparatus includes a processing unit configured to process an application program, a user program unit configured to execute a program written by a user based on the application program of the processing unit, a shared memory unit connected to each of the processing unit and the user program unit through a system bus and configured to store data interchanged between the processing unit and the user program unit, and a control unit configured to relay a control signal indicating whether the system bus, by which the data is interchanged between the processing unit and the user program unit, is occupied, and control connection of each of the processing unit and the user program unit with the system bus in response to the control signal.

Abstract: A method of allowing exclusive access to shared data by a computing device and a computer readable article embodying instructions for executing the method. The method includes: reading from a storage unit into a memory a program including a code for execution in a critical section and an instruction to write a value into or read a value from a shared data area in the memory; acquiring a lock on the critical section before start of a first instruction in the critical section; writing a value into a thread-local area in the memory in response to an instruction to write the value into the shared data area; writing into the shared data area the value written into the thread-local area upon completion of a final instruction in the critical section; and releasing the lock on the critical section, thereby allowing exclusive access to shared data.

Abstract: Techniques for selective compression of database information are presented. Selective first portions of a field associated with a database table are identified along with metadata associated with the database table. The first portions and the metadata are then compressed by selecting one or more compression algorithms in response to compression capabilities associated with the algorithms.

Abstract: In a shared memory process different threads may attempt to access a shared data variable in a shared memory. Locks are provided to synchronize access to shared data variables. Each lock is allocated to have a location in the shared memory relative to the instance of shared data that the lock protects. A lock may be allocated to be adjacent to the data that it protects. Lock resolution is facilitated because the memory location of a lock can be determined from an offset with respect to the data variable that is being protected by the lock.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to nested transaction rollback and provide a method, system and computer program product for dynamic nest level determination for nested transaction rollback. In an embodiment of the invention, a nested transaction rollback method can be provided. The method can include detecting a violation of a block of memory accessed within a set of nested transactions, retrieving a tentative rollback level for the violation, discarding a speculative state for the block of memory at each level of the set of nested transactions up to and including the tentative rollback level, refining the tentative rollback level to a lower level in the set of nested transactions, and additionally discarding a speculative state for the block of memory at additional levels in the set of nested transactions up to and including the refined rollback level.

Abstract: In a virtualized system using memory page sharing, a method is provided for maintaining sharing when Guest code attempts to write to the shared memory. In one embodiment, virtualization logic uses a pattern matcher to recognize and intercept page zeroing code in the Guest OS. When the page zeroing code is about to run against a page that is already zeroed, i.e., contains all zeros, and is being shared, the memory writes in the page zeroing code have no effect. The virtualization logic skips over the writes, providing an appearance that the Guest OS page zeroing code has run to completion but without performing any of the writes that would have caused a loss of page sharing. The pattern matcher can be part of a binary translator that inspects code before it executes.

Abstract: Protection of shared data in a multi-core processing environment is disclosed. A page-fault handling mechanism is adapted to synchronize access to shared memory. An application of the present invention is for synchronizing access to potentially shared data, where the shared data is opaque in that it does not have a well-defined structure.

Abstract: A data object is stored in a hosted storage system and includes an access control list specifying access permissions for data object stored in the hosted storage system. The hosted storage system provides hosted storage to a plurality of clients that are coupled to the hosted storage system. A request to store a second data object is received. The request includes an indicator that the first data object stored in the hosted storage system should be used as an access control list for the second data object. The second data object is stored in the hosted storage system. The first data object is assigned as an access control list for the second data object stored in the hosted storage system.

Abstract: A system and method is disclosed for fast lock acquisition and release in a lock-based software transactional memory system. The method includes determining that a group of shared memory areas are likely to be accessed together in one or more atomic memory transactions executed by one or more threads of a computer program in a transactional memory system. In response to determining this, the system associates the group of memory areas with a single software lock that is usable by the transactional memory system to coordinate concurrent transactional access to the group of memory areas by the threads of the computer program. Subsequently, a thread of the program may gain access to a plurality of the memory areas of the group by acquiring the single software lock.

Abstract: A system and method for locking and unlocking access to a shared memory for atomic operations provides immediate feedback indicating whether or not the lock was successful. Read data is returned to the requestor with the lock status. The lock status may be changed concurrently when locking during a read or unlocking during a write. Therefore, it is not necessary to check the lock status as a separate transaction prior to or during a read-modify-write operation. Additionally, a lock or unlock may be explicitly specified for each atomic memory operation. Therefore, lock operations are not performed for operations that do not modify the contents of a memory location.

Abstract: A method, circuit arrangement, and design structure utilize a lock prediction data structure to control ownership of a cache line in a shared memory computing system. In a first node among the plurality of nodes, lock prediction data in a hardware-based lock prediction data structure for a cache line associated with a first memory request is updated in response to that first memory request, wherein at least a portion of the lock prediction data is predictive of whether the cache line is associated with a release operation. The lock prediction data is then accessed in response to a second memory request associated with the cache line and issued by a second node and a determination is made as to whether to transfer ownership of the cache line from the first node to the second node based at least in part on the accessed lock prediction data.

Abstract: Data transmission efficiency for structured data can be improved by representing structured data using immutable blocks. The contents of the immutable blocks can include data and/or pointers to immutable blocks. An immutable data block cannot be altered after creation of the block. When data represented as immutable blocks is transmitted from one processor to another processor, the transmitter sends block contents for blocks that have not previously been defined at the receiver, and sends block IDs (as opposed to block contents) for blocks that have previously been defined at the receiver. The systematic use of block IDs instead of block contents in transmission where possible can significantly reduce transmission bandwidth requirements.

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Abstract: A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting in the release of the locks. As a result, in the intermediary period between acquiring and releasing the locks, any subsequent writes to memory locations that are locked are accelerated through non-execution of lock acquire operations.

Abstract: In accordance with one embodiment, additions to the standard computer microprocessor architecture hardware are disclosed comprising novel page table entry fields 015 062, special registers 021 022, instructions for modifying these fields 120 122 and registers 124 126, and hardware-implemented 038 runtime checks and operations involving these fields and registers. More specifically, in the above embodiment of a Hard Object system, there is additional meta-data 061 in each page table entry beyond what it commonly holds, and each time a data load or store is issued from the CPU, and the virtual address 032 translated to the physical address 034, the Hard Object system uses its additional PTE meta-data 061 to perform memory access checks additional to those done in current systems. Together with changes to software, these access checks can be arranged carefully to provide more fine-grain access control for data than do current systems.

Abstract: Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection.

Abstract: A system and method for providing a command queue selection scheme by selecting commands by giving preference to commands based on the power consumption characteristics the command. In one embodiment the selection scheme involves calculating the value of the cost of energy saving associated with the access of a command by an evaluation function Costi=EAT+C×F1 (seek distance, latency). C is a dynamically adjustable power control function that determines how much power decreases with the selection of a particular command and F1 is a functional calculation of the power consumption value associated with the particular command. In one embodiment commands with low power consumption will be accessed in preference to commands with shorter seek distance.

Abstract: A cache memory and a tag memory are included in a banked memory system and used to effectively enable parallel write and read operations on each clock cycle, even though the memory banks consist of single-port devices that are not inherently capable of parallel write and read operations.

Abstract: Methods and systems are provided that may be utilized for spilling in query processing environments.

Abstract: Provided is a host computer which is connected to a system resource through n (n?2) number of paths. The host computer includes: a plurality of logical partitions accessible to the system resource; an allocation unit that allocates the paths to the plurality of logical partitions; and an allocation table. The allocation table is user configurable and stores, in a correlated manner, information indicating the logical partitions and information capable of indicating the number of paths to be allocated to the logical partitions indicated by the information. The allocation unit allocates the paths to the logical partitions in accordance with the allocation table. This makes it possible to secure the I/O response also for logical partitions having a small amount of I/O.

Abstract: A method, system, and computer usable program product for using a dual mode reader writer lock. A contention condition is detected in the use of a lock in a data processing system, the lock being used for managing read and write access to a resource in the data processing system. A determination of the data structure used for implementing the lock is made. If the data structure is a data structure of a reader writer lock (RWL), the data structure is transitioned to a second data structure suitable for implementing the DML. A determination is made whether the DML has been expanded. If the DML is not expanded, the DML is expanded such that the data structure includes an original lock and a set of expanded locks. The original lock and each expanded lock in the set of expanded locks forms an element of the DML.

Abstract: Methods, systems, and products are disclosed for administering an epoch initiated for remote memory access that include: initiating, by an origin application messaging module on an origin compute node, one or more data transfers to a target compute node for the epoch; initiating, by the origin application messaging module after initiating the data transfers, a closing stage for the epoch, including rejecting any new data transfers after initiating the closing stage for the epoch; determining, by the origin application messaging module, whether the data transfers have completed; and closing, by the origin application messaging module, the epoch if the data transfers have completed.

Abstract: A method, in one embodiment, can include a server receiving a message to deactivate a partition key of an object based storage system. A token of the object based storage system is signed by the partition key. The object based storage system includes the server. Additionally, after receiving the message, the server can deactivate the partition key to block access to a partition of the object based storage system by a client. The server includes the partition.

Abstract: An information processor for executing multiple applications including an external application under a control of an operating system, includes: a executing section that executes the external application in an isolated environment based on user identification information that is under the control of the operating system and allocated to the external application.

Abstract: Technology for minimizing disruptions when host data on a physical volume is encapsulated into a virtualization layer or de-encapsulated is disclosed. Evaluation of a physical volume used as data storage for a virtualization layer before committing to direct access to the physical volume is enabled by preventing direct access before presenting the physical volume directly to the host and by preventing the virtualization layer from moving data on the physical volume while redirecting to the physical volume a first plurality of I/O requests that were directed to the virtualization layer.

Abstract: A distribution medium (20) for providing an application to a host system (4) includes an interface element (21) for interfacing with the host (4), a memory or storage module (22) that stores application code representing the application and a hardware element (23). The hardware element (23) directly accesses application content stored in the memory (22), processes that application content to transform it to another form, and then provides the transformed content to the host system (4).

Abstract: A system and method to ensure trustworthiness of a remote service provided by a service provider. The method includes monitoring runtime dependencies invoked during execution of a service transaction associated with the remote service, the service transaction being requested by a service requester. The method further includes determining whether a deviation exists between the runtime dependencies and a trusted list of dependencies associated with the remote service. The method also includes blocking execution of the service transaction based on determining that the deviation between the runtime dependencies and the trusted list of dependencies exists.

Abstract: Transparent hypervisor pinning of critical memory areas is provided for a shared memory partition data processing system. The transparent hypervisor pinning includes receiving at a hypervisor a hypervisor call initiated by a logical partition to register a logical memory area of the logical partition with the hypervisor. Responsive to this hypervisor call, the hypervisor transparently determines whether the logical memory is a critical memory area for access by the hypervisor. If the logical memory area is a critical memory area, then the hypervisor automatically pins the logical memory area to physical memory of the shared memory partition data processing system, thereby ensuring that the memory area will not be paged-out from physical memory to external storage, and thus ensuring availability of the logic memory area to the hypervisor.

Abstract: A computer component mounting assembly includes a base plate, a carrier configured to receive a vibration sensitive computer component, and a vibration isolation system including three isolators connecting the carrier to the base plate. The three isolators are spaced at different angular positions around a central point, and the vibration isolation system is configured such that the vibration isolation system has a rotational natural frequency about the central point of less than 45 Hz.

Abstract: Novel storage area networks (SANs) and methods of operation thereof utilize a plurality of hosts coupled via an interconnect with one or more storage units. A manager device, process or other functionality in communication with a plurality of agent processes, devices or other functionality, each of which is associated with a host. The agents identify attributes of (i) their associated hosts, (ii) interconnect to which that host is coupled, and/or (iii) storage units to which that host is coupled via the interconnect. The manager responds to these attributes identified by the agents to manage the SAN. The manager can be implemented on a first digital data processor and the hosts on further digital data processors. These digital data processors can be coupled via a first network, e.g., an IP or other network, to support communications between the manager and the agents. A second network, e.g.