Abstract: A programmable electronic device (10) stores a number of cipher-text software modules (14) to which access is granted after evaluating a user's token (55, 80, 82), a software-restriction class (58) for a requested software module (14), and/or a currently active access-control model (60). Access-control models (60) span a range from uncontrolled to highly restrictive. Models (60) become automatically activated and deactivated as users are added to and deleted from the device (10). A virtual internal user proxy that does not require users to provide tokens (80, 82) is used to enable access to modules (16) classified in a global software-restriction class (62) or when an uncontrolled-access-control model (68) is active. Both licensed modules (76) and unlicensed modules (18,78) may be loaded in the device (10). However, no keys are provided to enable decryption of unlicensed modules (18,78).

Abstract: A method and system for saving and retrieving data includes saving data in data storage fields of a data storage device in a computer. A back-up data storage field is selected in the data storage device. A data changing operation including new data is initiated on specified data saved in a current data storage field. A copy of all the data stored in boundary data storage fields is copied and stored in the back-up data storage field before changing the current data to provide data retrieval if the data is unrecoverable in the current data storage field, when a loss of power to the data storage device occurs.

Abstract: The present invention comprises a CHA 110 which transmits/receives data to/from an external device, a DKA 140 which transmits/receives data to/from an HDD unit 200, a primary cache unit 120 which has a primary cache memory 124, a secondary cache unit 130 which is installed between the primary cache unit 120 and the DKA 140 and has a secondary cache memory 134, a CCP 121 which stores write target data received by the CHA 110 in the primary cache memory 124, and a CCP 131 which stores the write target data in the secondary cache memory 134, and transfers the write target data stored in the secondary cache memory 134 to the DKA 140.

Abstract: A disk array system including a plurality of disk drives, including: a plurality of first-type disk drives being used to form a first-type logical unit having a plurality of a first-type of chunks; a plurality of second-type disk drives being used to form a second-type logical unit having a plurality of a second-type of chunks; and a storage controller, if the storage controller copies data stored in a source chunk to a destination chunk, selecting the destination chunk from the first-type of chunks or the second-type of chunks.

Abstract: A method of dynamically switching partitions for a memory card having a plurality of physical blocks is provided. The method includes configuring logical blocks for mapping to at least a portion of the physical blocks and dividing the logical blocks into first and second partitions; coupling the memory card to a host system and setting CSD corresponding to the memory card as a first default value corresponding to the first partition, wherein the host system requests the CSD to obtain the first default value and accesses the first partition according to the first default value; and setting the CSD corresponding to the memory card as a second default value corresponding to the second partition in response to a switch command from the host system, wherein the host system re-requests the CSD to obtain the second default value and accesses the second partition according to the second default value.

Abstract: A hardware device register is written without transferring the register content from the hardware device to a host device over an interface bus for modification. The hardware device receives an address identifying the target register included in the hardware device and bit information associated with a write operation involving the target register from the host device over the interface bus. The address is stored in a first register included in the hardware device and dedicated for supporting write operations. The bit information is stored in a second register included in the hardware device and also dedicated for supporting write operations. The target register is accessed based on the address stored in the first register dedicated for supporting write operations and one or more bits of the target register are written based on the bit information without first transferring the register content to the host device over the interface bus.

Abstract: A storage apparatus includes: a memory allowing an operation to be carried out in order to additionally write new write data into a storage area already used for storing previous write data so as to store the new data in the storage area along with the previous write data; an input/output section configured to receive write data in a write access; and a control section configured to write the write data into the memory on the basis of the write access, wherein, in internal processing based on the write access, the control section carries out an additional-write operation for a storage area already used for storing the previous write data in the internal processing.

Abstract: A system recovery method is provided. The system recovery method includes grouping storage addresses corresponding to a storage device into a first memory area and a second memory area. The system recovery method also includes storing initial data from a host system into the storage addresses of the first memory area, storing update data for updating the initial data into the storage addresses of the second memory area, and establishing an address corresponding table to record update information corresponding to the storage addresses for storing the update data. The system recovery method further includes erasing the update information from the address corresponding table when the storage device is powered off and re-coupled to the host system. Thereby, the system recovery method can instantly recover system settings.

Abstract: A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the memory address. The memory interface can connect to a host configured to access data in a conventional SDRAM memory device so that the host can access data in the memory.

Abstract: A data processing apparatus includes a storage controller and a processor. The storage controller is configured to write a series of data blocks constituting a particular unit of data to a storage and read out the series of data blocks from the storage. The processor is further configured to generate a write-side process and a read-side process, notify the read-side process from the write-side process of an identifier of a storage area in the storage, cause the storage controller to sequentially write the series of data blocks to the storage area using the write-side process, and cause the storage controller to read the series of data blocks from the storage area corresponding to the identifier using the read-side process after the identifier is received in the read-side process.

Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips having writable storage regions in which data is written. The data has one or more pieces of first data, and one or more pieces of the first data includes second data. The device includes a determining unit that determines a prescribed number or fewer of semiconductor memory chips to which the first data is written; a write controller that writes the the first data and redundant information calculated from the second data and used for correcting an error in the second data into the writable storage regions in the determined semiconductor memory chips; and a storage unit that stores identification information and region specifying information associated with each other.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: Data storage reliability is maintained in a write-back distributed data storage system including multiple nodes, each node comprising a processor and an array of failure independent data storage devices. Information is stored as a set of stripes, each stripe including a collection of multiple data strips and associated parity strips, the stripes distributed across multiple corresponding primary data nodes and multiple corresponding parity nodes. A primary data node maintains the data strip holding a first copy of data, and each parity node maintains a parity strip holding a parity for the multiple data strips. A read-modify-write parity update protocol is performed for maintaining parity coherency, the primary data node driving parity coherency with its corresponding parity nodes, independently of other data nodes, in order to keep its relevant parity strips coherent.

Abstract: A controller for one type of NAND flash memory device that emulates another type of NAND flash memory device. The controller may include a host NAND interface to receive host data from a NAND host device, and a data aggregator for aggregating the host data with complementary data, to thereby create device data that is storable in a device page of an array of NAND flash memory cells of the NAND flash memory device. After creating the device data the controller writes the device data into a device page of the NAND flash memory cells. The controller also includes a data parser to parse host data from device data when data read operations are executed by the controller. If required, the controller uses the data parser to parse complementary data from device data to create device data when data writing operations are executed by the controller.

Abstract: A method for operating a memory device that includes a plurality of analog memory cells includes accepting at an input of the memory device a self-contained command to perform a memory access operation on at least one of the memory cells. The command includes an instruction specifying the memory access operation and one or more parameters that are indicative of analog settings to be applied to the at least one of the memory cells when performing the memory access operation. The self-contained command is executed in the memory device by extracting the parameters, applying the analog settings to the at least one of the memory cells responsively to the extracted parameters, and performing the specified memory access operation in accordance with the instruction on the at least one of the memory cells using the settings.

Abstract: According to an aspect of the embodiment, in a control method for a disk array apparatus, a CPU of a first control module acquires other system state information, which is decided based on a battery and a nonvolatile memory of the second control module and indicates a data saving possibility of a cache memory of a second control module. The CPU of the first control module determines, based on the other system state information acquired and own system state information, which is decided based on a battery and a nonvolatile memory of the first control module and indicates a data saving possibility of a cache memory of the first control module, whether the disk array apparatus is set in a write-back state or a write-through state.

Abstract: A multithreaded processor with a banked cache is provided. The instruction set includes at least one atomic operation which is executed in the L2 cache if the atomic memory address source data is aligned. The core executing the instruction determines whether the atomic memory address source data is aligned. If it is aligned, the atomic memory address is sent to the bank that contains the atomic memory address source data, and the operation is executed in the bank. In one embodiment, if the instruction is mis-aligned, the operation is executed in the core.

Abstract: One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.

Abstract: The invention features a method for controlling storage of data in a plurality of storage devices each including storage blocks, for example, in a RAID array. The method includes receiving a plurality of write requests associated with data, and buffering the write requests. A file system defines a group of storage blocks, responsive to disk topology information. The group includes a plurality of storage blocks in each of the plurality of storage devices. Each data block of the data to be written is associated with a respective one of the storage blocks, for transmitting the association to the plurality of storage devices.

Abstract: A method for accessing a downgrade memory and a downgrade memory apparatus are provided. The downgrade memory apparatus comprises at least one management unit and a controller. The management unit comprises a plurality of blocks, each block having a plurality of pages, and each page having a plurality of sectors, the downgrade memory having a plurality of non-accessible sectors. The controller is configured to parse a write command corresponding to a special block, to select at least one accessible sector according to a status information of the special block and to program the write command to the special block, wherein the status information indicates at least one non-accessible sector in the special block. Thereby the method and the apparatus of downgrade memory may as well omit the non-accessible sectors as enhance the usage memory capacity in accordance with the status information.

Abstract: A storage device includes a controller that is configured to execute safe deletion operations so as to free up storage space on the device in response to triggering events. The safe deletion operations ensure that the data states of a host device making use of the storage device and the storage device itself are synchronized so as to prevent deletion of data from the storage device before it is offloaded to another storage platform.

Abstract: Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a phase change memory device.

Abstract: Systems and methods for controlling memory access operations are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines a destination bank, and the request is placed in an appropriate bank queue. An ordering unit determines if the current request can be reordered relative to the received order and generates a new memory cycle order based on the reordering determination. The reordering may be based on whether there are multiple requests to the same memory page, multiple reads, or multiple writes. A memory interface executes each memory request in the memory cycle order. A data buffer holds write data until it is written to the memory and read data until it is returned to the requestor. The data buffer also may hold memory words used in read-modify-write operations.

Abstract: A method and apparatus are disclosed for reclaiming solid state storage with limited write cycles such as flash memory. Through the use of shared storage for common data patterns, physical space may be conserved or reclaimed in a solid state device. The apparatus may use internal mappings and/or external device drivers to handle the reclamation of unused space. By enabling reclamation of physical space, the disclosed systems, apparatus, and methods may provide more efficient read and write access and improved wear leveling.

Abstract: A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.

Abstract: A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.

Abstract: Techniques for writing to memory using adaptive write techniques. An adaptive write technique includes receiving at a computer a message including a plurality of symbols. The message is written to a memory. The writing to memory includes performing for each symbol in the message: writing a data value to a memory location in the memory and reading contents of the memory location after the data value has been written. The data value is determined at the computer in response to the symbol and to the contents of any memory locations previously read as part of writing the message to the memory. It is determined at the computer if the contents of the memory locations reflect the message. The writing is restarted at the computer in response to determining that the contents of the memory locations do not reflect the message.

Abstract: The invention provides a data access method. First, a plurality of commands received from a host is stored in a command queue. A plurality of logical address ranges of the commands is then calculated. A plurality of write commands is then selected from the commands, wherein the logical address ranges of the write commands are overlapping with each other. Whether at least one read command having a receiving order that is in between the receiving orders of the write commands exists in the command queue is then determined. When the at least one read command does not exist, write data corresponding to the write commands are combined together to obtain combined write data according to the logical address ranges of the write commands. A combined write command and the combined write data are then sent to a memory to request that the memory executes the write commands.

Abstract: A method for secure data reading and a data handling system is provided. The method protects the data reading from fault attacks by repeating read request in an interleaved manner, in particular the method comprises the steps of (M200) dispatching a first read request; (M400) dispatching a second read request; (M600) dispatching a further first read request; and (M1000-a) producing an anomaly signal if a first result produced by the memory in response to the first read request does not agree with a further first result produced by the memory in response to the further first read request.

Abstract: A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.

Abstract: A system for controlling asynchronous updates to a register, the system including a generally accessible register that is asynchronously updateable by hardware and software. The system also includes protection logic that is in communication with the register. The protection logic includes circuitry to prevent a hardware update to the register from being overwritten by a software update.

Abstract: According to the present invention, methods and apparatus are provided for improving data transfers between hosts and targets connected through fiber channel switches. A host connected intelligent port and a target connected intelligent port associated with fiber channel edge switches are configured to snoop frames from the host and target and establish flows for acceleration. The host connected intelligent port and the target connect intelligent port preemptively respond to host and target transmissions to reduce data transfer latency.

Abstract: In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

Abstract: In a consolidated electronic control unit (ECU) integrally produced by a plurality of conventional ECUs, an inventive relay program is adapted to enable a CPU of the consolidated ECU to rewrite internal and external parameters into the external and internal parameters, respectively, with reference to a correspondence list previously set between the internal parameter and the external parameter. The internal parameter is a parameter that is to be used by a specific program implemented in the consolidated ECU. The external parameter is a parameter that corresponds to the internal parameter and that is to be used by a non specific program implemented in the consolidated ECU.

Abstract: A system manages a buffer having a group of entries. The system receives information relating to a read request for a memory. The system determines whether an entry in the buffer contains valid information. If the entry is determined to contain valid information, the system transmits the information in the entry in an error message. The system may then store the received information in the entry. In another implementation, the system stores data in one of the entries of the buffer, removes an address corresponding to the one entry from an address list, and starts a timer associated with the one entry. The system also determines whether the timer has exceeded a predetermined value, transferring the data from the one entry when the timer has exceeded the predetermined value, and adds the address back to the address list.

Abstract: A smartcard includes a write unit that writes data to be written to a data memory according to a write command supplied from an external device, a determining unit that determines whether important data is contained in the data to be written specified by the write command supplied from the external device, a calculating unit that calculates a head address of the important data in the data memory based on data length from a head of the data to be written to a head of the important data and an address on the data memory at which a process of writing the data to be written is started when the determining unit determines that important data is contained in the data to be written, and a position table that stores information indicating a head address of the important data in correspondence to information indicating the important data.

Abstract: A write buffer for read-write interlocks improves memory access performance by minimizing the latency needed to avoid a read-after-write hazard when a read follows a write to the same memory location. Rather than waiting until a write has been stored in the memory location, the write buffer provides an acknowledgement signal before the data has been stored in memory in order for a subsequent read of the memory location to proceed. The write buffer merges the data to be written with any data that is stored in memory for the read request to return the current data for the read request.

Abstract: Systems and methods for controlling memory access operation are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines a destination bank, and the request is placed in an appropriate bank queue. An ordering unit determines if the current request can be reordered relative to the received order and generates a new memory cycle order based on the reordering determination. The reordering may be based on whether there are multiple requests to the same memory page, multiple reads, or multiple writes. A memory interface executes each memory request in the memory cycle order. A data buffer holds write data until it is written to the memory and read data until it is returned to the requestor. The data buffer also may hold memory words used in read-modify-write operations.

Abstract: A database of codesets for a remote control device includes codeset information blocks for derivative codesets and codeset information blocks for nonderivative codesets. A codeset information block for a derivative codeset includes: a bit indicating that the block is for a derivative codeset, a plurality of bits each of which corresponds to a respective one of a plurality of fields in a referenced codeset information block, and a pointer that points to the referenced codeset information block. The digital value of a bit determines whether information from the corresponding field in the referenced block will be used as part of the derivative codeset or whether such information is contained in the derivative codeset information block itself. The sizes of the fields in the referenced block are predetermined or are determinable, so a field in the referenced block can be located if its bit is set in the referencing block.

Abstract: A memory architecture of a display device including a display data memory block and a processor is provided. The display data memory block includes N sub-memories and N arbiters respectfully coupled to the N sub-memories, wherein N is a positive integer larger than 1. The processor is used for respectfully and continuously outputting corresponding N control signals and N address signals to the N arbiters. After receiving the corresponding control signals, the N arbiters respectfully output the corresponding address signals to corresponding sub-memories, such that the N sub-memories simultaneously access data respectfully according to the N address signals.

Abstract: In one embodiment, a mechanism for a reader page for a ring buffer is disclosed. In one embodiment, a method for implementing a reader page for a ring buffer includes allocating, by a processing device, a block of storage separate from a ring buffer as a reader page for a reader of the ring buffer, the ring buffer stored in a physical memory device, and swapping, by the processing device, a head page of the ring buffer with the reader page so that the reader page is part of the ring buffer and the head page is no longer attached to the ring buffer.

Abstract: A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the memory address. The memory interface can connect to a host configured to access data in a conventional SDRAM memory device so that the host can access data in the memory.

Abstract: A database garbage collector that removes appropriate database entries accessed during a recent transaction.

Abstract: Traditional networked file systems like NFS do not extend to wide-area due to network latency and dynamics introduced in the WAN environment. To address that problem, a wide-area networked file system is based on a traditional networked file system (NFS/CIFS) and extends to the WAN environment by introducing a file redirector infrastructure residing between the central file server and clients. The file redirector infrastructure is invisible to both the central server and clients so that the change to NFS is minimal. That minimizes the interruption to the existing file service when deploying WireFS on top of NFS. The system includes an architecture for an enterprise-wide read/write wide area network file system, protocols and data structures for metadata and data management in this system, algorithms for history based prefetching for access latency minimization in metadata operations, and a distributed randomized algorithm for the implementation of global LRU cache replacement scheme.

Abstract: According to one embodiment, a disk controller includes a receiver, a read-modify-write controller, and a wait controller. The receiver receives data in units of predetermined data length. The read-modify-write controller performs a read-modify-write operation when the receiver receives the data to write the data to a sector on a disk medium the rotation of which is controlled. The sector is longer than the predetermined data length. The wait controller delays the start of the read-modify-write operation by the read-modify-write controller for within the time which the disk medium takes to rotate once and which is substantially the same as the time required to control the read-modify-write operation.

Abstract: In a reconfigurable data strobe-based memory system, data strobes may be re-tasked in different modes of operation. For example, in one mode of operation a differential data strobe may be used as a timing reference for a given set of data signals. In a second mode of operation, one of the components of the differential data strobe may be used as a timing reference for a first portion of the set of data signals and the other component used as a timing reference for a second portion of the set of data signals. Different data mask-related schemes also may be invoked for different modes of operation. For example, in a first mode of operation a memory controller may generate a data mask signal to prevent a portion of a set of data from being written to a memory array. Then, in a second mode of operation the memory controller may invoke a coded value replacement scheme or a data strobe transition inhibition scheme to prevent a portion of a set of data from being written to a memory array.

Abstract: An information system includes a storage system having a controller in communication with a plurality of storage devices. In some embodiments, the storage devices are divided into at least a first group and a second group, with a first temperature sensor sensing a temperature condition for the first group, and a second temperature sensor for sensing a temperature condition for the second group. A heat distribution rule designates the first groups to be high temperature groups and the second groups to be low temperature groups. The heat distribution rule is implemented by designating a higher load of input/output (I/O) operations to the high temperature groups than to the low temperature groups, such as by migrating volumes having high I/O loads to the high temperature groups. In other embodiments, there are multiple storage systems, and each storage system is designated as a high temperature system or a low temperature system.

Abstract: Techniques are provided for quickly reacquiring mutual exclusion locks (QRLs), such as in the case in which a single process repeatedly acquires and releases the lock and in which no other process attempts to acquire the same lock. When the first holder of a QRL first acquires the lock, it biases the lock to itself. Bias may be directed in different way or at different times in some realizations. Biasing may involve a one-time compare-and-swap instruction. Thereafter, this bias-holder can reacquire and release the lock free of atomic read-modify-write operations. If a second process attempts to acquire a QRL, then the lock may revert to a “default lock”. Any standard mutual exclusion lock may be used as the default lock. A QRL lock may be reinitialized so that it can be rebiased. Rebiasing may be valuable in the case of migratory data access patterns.

Abstract: The memory device electrically connectable to a host circuit includes a nonvolatile data memory section, a data reception section, a determination section, and a data transmission section. The data reception section receives, from the host circuit, data including first data to be written into a memory array, and second data generated from the first data. The determination section determines the consistency the first data and the second data. The data transmission section transmits the result of the determination to the host circuit.

Abstract: Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after write commands are executed internally prior to executing the earlier received write commands. Write commands are buffered so that the commands can be executed upon completion of the later received read command. One example of a buffered write command circuit includes a write command buffer to buffer write commands and propagate buffered write commands therethrough in response to a clock signal and further includes write command buffer logic. The write command buffer logic generates an active clock signal to propagate the buffered write commands through the write command buffer for execution, suspends the active clock signal in response to receiving a read command after the write command is received, and restarts the active clock upon completion of the later received read command.