Abstract: A processor and a method for executing load operation and store operation thereof are provided. The processor includes a data cache and a store buffer. When executing a store operation, if the address of the store operation is the same as the address of an existing entry in the store buffer, the data of the store operation is merged into the existing entry. When executing a load operation, if there is a memory dependency between an existing entry in the store buffer and the load operation, and the existing entry includes the complete data required by the load operation, the complete data is provided by the existing entry alone. If the existing entry does not include the complete data, the complete data is generated by assembling the existing entry and a corresponding entry in the data cache.

Abstract: A device is provided wherein a traditional EEPROM device is emulated by using two or more pages of block-erasable memory and mapping each traditional EEPROM write instruction to an incremented active data sector in a first page of the block-erasable memory while a second page of the block-erasable memory is being partially or fully erased. Then, when the first page of block-erasable memory has had its plurality of data sectors written, changing the active page to the second block-erasable memory and mapping traditional EEPROM writes to incremented data sectors therein while the previously written block-erasable memory is being partially or fully erased.

Abstract: A data processing apparatus and method are provided for performing hazard detection in respect of a series of access requests issued by processing circuitry for handling by one or more slave devices. The series of access requests include one or more write access requests, each write access request specifying a write operation to be performed by an addressed slave device, and each issued write access request being a pending write access request until the write operation has been completed by the addressed slave device. Hazard detection circuitry comprises a pending write access history storage having at least one buffer and at least one counter for keeping a record of each pending write access request.

Abstract: A disk array system including a plurality of disk drives, including: a plurality of first-type disk drives being used to form a first-type logical unit having a plurality of a first-type of chunks; a plurality of second-type disk drives being used to form a second-type logical unit having a plurality of a second-type of chunks; and a storage controller, if the storage controller copies data stored in a source chunk to a destination chunk, selecting the destination chunk from the first-type of chunks or the second-type of chunks.

Abstract: A storage system that stores verify commands for all the write commands requiring verification in a verify-list that will be processed as a background task is described. The verify-list can include coded data fields that flexibly designate selected alternative states or possibilities for how and where the user data is actually stored. Alternatives for the verify-list include storing the actual raw data, no data, the data in compressed form, a CRC type signature of the data and/or a pointer to a backup copy of the data that is stored either in non-volatile memory such as flash memory or on the disk media in a temporary area. In case of a verification error in various alternative embodiments the user data can be recovered using the backup copy in the verify-list in the write cache, the backup copy in flash memory or on the disk, or from the host.

Abstract: Provided are a ring buffer circuit in which a data full state and a data empty state may be correctly detected without depending on whether read and write operations are synchronous or asynchronous with each other, and a control circuit for the ring buffer circuit. The ring buffer circuit includes: a read and write memory having addresses specified by N bits; a write address counter pointer and a read address counter pointer which are provided for the read and write memory to count (N+1)-bit gray codes; and write and read address converter circuits provided to convert the (N+1)-bit gray codes output from the write and read address counter pointers into N-bit addresses which may be directly designated as write and read addresses of the read and write memory.

Abstract: Machine readable instructions, methods, and systems of causation of a data read against a first storage system to optionally store a data write to preserve the version to allow viewing and recovery are disclosed. In an embodiment, a system for providing secondary data storage and recovery services for one or more networked host nodes includes a server application for facilitating data backup and recovery services; a first data storage medium accessible to the server application; a second data storage medium accessible to the server application; and at least one client application for mapping write locations allocated by the first data storage medium to write locations represented in a logical view of the first data storage medium.

Abstract: An integrated circuit memory system includes a write-back buffer and a control circuit that support read-write-modify (RWM) operations within a high capacity memory device. A RWM operation may include reading from the integrated circuit memory device and the write-back buffer to identify whether the memory device or the write-back buffer has the data requested by a read instruction issued to the memory system. The data read from the write-back buffer is then written into the memory device and a modified version of the requested data is written to the write-back buffer in anticipation of subsequent transfer to the memory device.

Abstract: A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.

Abstract: A memory may be configured to rearrange and store data to enable a conflict free mode for a memory access pattern required by a coder-decoder(codec) and configured to output a plurality of data from a plurality of banks of the memory in parallel. In addition, a data interconnection unit is configured to shift the plurality of data output from the memory and provide the shifted data to a plurality of operation units as input data. The operation result from each of the plurality of operation units is stored in a region of the memory.

Abstract: Systems (100) and methods (300) for enhancing a data store (DS) addressable at a block level and interfaced with a host device (HD) via a memory controller (MC), which may comprise a VMCC (110, 210). The methods involve receiving an access operation (AO) from HD (104) at MC. In response to receiving the AO, plug-ins (232) are invoked. The plug-ins include a pre-processing plug-in (2324) for facilitating an indexing function of MC and/or a post-processing plug-in (2325) for facilitating a monitoring function of MC. The methods also involve accessing DS (106, 206) to read a bock of data therefrom, write the block of data thereto, or erase the block of data therefrom in accordance with the AO. The methods further involve obtaining post-processing information about the AO in response to an invocation of the post-processing plug-in and updating a log-file (224) stored in the DS with the post-processing information.

Abstract: Separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.

Abstract: Methods, systems and computer program products to implement hardware memory locks are described herein. A system to implement hardware memory locks is provided. The system comprises an off-chip memory coupled to a SOC unit that includes a controller and an on-chip memory. Upon receiving a request from a requester to access a first memory location in the off-chip memory, the controller is enabled to grant access to modify the first memory location based on an entry stored in a second memory location of the on-chip memory. In an embodiment, the on-chip memory is Static Random Access Memory (SRAM) and the off-chip memory is Random Access Memory (RAM).

Abstract: Disclosed is a storage apparatus that extends endurance and reduces bit cost. A storage apparatus includes a controller and a semiconductor storage media that has a plurality of storage devices. The plurality of storage devices include a first storage device and a second storage device having an upper limit of an erase count of data smaller than that of the first storage device. Area conversion information includes correspondence of a first address to be specified as a data storage destination and a second address of an area in which data is to be stored. A rewrite frequency of stored data is recorded for each area.

Abstract: A network device may operate to increase application performance over a wide area network. In one particular implementation, the network device may monitor accesses to a disk drive from entities and determine whether an entity is accessing the disk drive in a manner that causes a disproportionate amount of performance degradation. If so, the network device may throttle access to the disk drive for the entity.

Abstract: Replacement data for updating data recorded on an information storage medium is recorded in an area for logical overwrite (LOW) replacement; replacement data for replacing a defect generated on the medium is recorded in an area for defect replacement; and, if a defect is generated in an original block recorded in a predetermined area of the medium during a read-modify-write (RMW) process for a LOW for at least partial data of an original block, a replacement block replacing the original block is recorded in the area for LOW replacement and a defect list (DFL) entry including location information of the original block and location information of the replacement block is generated to indicate the replacement state.

Abstract: A nonvolatile storage device is provided with a nonvolatile main storage memory whose erase size is larger than a cluster size, and a buffer, i.e. a nonvolatile auxiliary storage memory. At the time of writing data in the memory, the data is temporarily stored in the buffer, then, a plurality of data in the buffer are collectively taken out to be stored in the main storage memory. Data in an original block is saved in a write block in the main storage memory. Thus, the data can be written in the main storage memory at a high speed.

Abstract: An information storage medium, a recording/reproducing apparatus and a recording/reproducing method are provided to increase data reproduction efficiency.

Abstract: An image forming apparatus and a method of overwriting for a storage unit in an image forming apparatus. The method of overwriting data in a storage unit of an image forming apparatus includes configuring a plurality of overwriting options corresponding to data stored in the storage unit; deleting the data stored in the storage unit according to a delete instruction; and overwriting data according to the configuration of the plurality of overwriting options corresponding to the data stored in the storage unit.

Abstract: A method, apparatus, and system of a software technique for improving disk write performance on raid system where write sizes are not an integral multiple of number of data disks are disclosed. In one embodiment, a method includes configuring a queue module to place an amount of data of a write operation into a data buffer module associated with a memory system if writing the amount of data to the memory system would generate a read-modify-write operation to occur, using the data buffer module to temporarily store the amount of data, writing the amount of data from the data buffer module to the memory system. The method may include algorithmically determining the amount of data to place in the data buffer module as a portion of the write operation that may cross a boundary between a striped sector unit (SSU) and/or an other SSU.

Abstract: A memory interface permits a read-modify-write process to be implemented as an interruptible process. A pending read-modify-write is capable of being temporarily interrupted to service a higher priority memory request.

Abstract: A technique involves providing access to shared data based on enhanced standard virtual memory mechanisms. Once data from a shared area of memory is moved into primary memory of a first computerized device from a second computerized device, the first computerized device can retain that data in order to shorten the latency of subsequent accesses. Such a technique can be configured to handle shared data at the sub-page-granular level using sparse virtual pages to minimize memory access contention and thus improve the likelihood of quick re-hits. Furthermore, such a technique can be conveniently accomplished through an enhancement to a common page fault handler of an operating system and utilizing atomic remote access support from a standard communications protocol thus alleviating the need to employ more costly and complicated solutions such as inflexible hardware implementations or independent programs that could pose additional design burdens and reliability concerns.

Abstract: Separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system is provided. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.

Abstract: Each CM retains a function management table in which entry information indicating which function is operating in which CM for what period is registered. Every time a command is executed in a function processing unit on the basis of an instruction from a GUI, components of a CM perform control, communicating registered pieces of content in a function management table to corresponding components of another CM for synchronization among the CMs. Regardless of which of a plurality of CMs in a storage apparatus is a master, processing can be executed in any CM from any GUI without inconsistency in the processing between the CMs.

Abstract: A memory controller controls a memory access to each memory region out of one or more memory regions in SIMD unit. The memory controller includes: a pointer-calculation hardware unit that increments by unit SIMD a value of an access control pointer corresponding to each of the memory regions at different timings corresponding to an access mode set beforehand in each memory region; and a memory-access-control hardware unit that calculates an access destination address in each of the memory regions based on a value of an access control pointer in the memory region, and causes a memory access in SIMD unit to be performed to the calculated access destination address.

Abstract: It is possible to classify a continuous content into separate series to be written into a storage medium. A reception device receives a digital broadcast program and EIT and generates program attribute information according to the information associated with the series contained in EIT. Upon reception of a write-into-DVD instruction of a recorded digital broadcast program in a program recording region inputted by a user via UI, a write control device integrates the program attribute information in the program attribute information storage region, the write-into-DVD history information in the write-into-DVD history information storage region, and the DVD information obtained from the DVD drive, so as to judge whether write into DVD is enabled. The write control device presents the judgment information to the user via UI and controls write of the recorded digital broadcast program into the DVD according to the user instruction input information acquired via the UI.

Abstract: Various flash management techniques may be described. An apparatus may comprise a processor, a flash memory coupled to the processor, and a flash management module. The flash management module may be executed by the processor to receive a write transaction request to write data to a flash memory, and write the data to a set of multiple discontiguous logical sectors corresponding to a set of physical sectors of the flash memory in a single atomic operation. Other embodiments are described and claimed.

Abstract: A memory controller, a PCB and a computer system employing the memory controller, and a memory adjusting method using the memory controller. The memory controller interfaces data reading from and writing to a memory and includes: a characteristic estimating part estimating a characteristic of a memory output signal outputted from the memory for the data reading and writing; and a characteristic adjusting part controlling the memory so that the characteristic of the memory output signal is within a predetermined reference range if the characteristic of the memory output signal estimated by the characteristic estimating part is beyond the predetermined reference range.

Abstract: A technique for accessing a shared resource of a computerized system involves running a first portion of a first thread within the computerized system, the first portion (i) requesting a lock on the shared resource and (ii) directing the computerized system to make operations of a second thread visible in a correct order. The technique further involves making operations of the second thread visible in the correct order in response to the first portion of the first thread running within the computerized system, and running a second portion of the first thread within the computerized system to determine whether the first thread has obtained the lock on the shared resource. Such a technique alleviates the need for using a MEMBAR instruction in the second thread.

Abstract: In a system which realizes to prevent leakage/loss of secret information by prohibiting a write operation to a secondary storage apparatus and a write operation to an external medium, an automatic collection of secret data to a server is executed, an existing application mode of PC is not damaged, and then an update of OS and an application is executed. The present invention places a secondary storage apparatus write control driver on the lower level than a file system, and redirects a write operation to the secondary storage apparatus, setting up a memory to be a primary cache, and cache data file on a cache server of a network destination to be a secondary cache. Thereby, the write operation to the secondary storage apparatus is not executed, and difference data is stored on the cache server, so that the automatic collection of secret data to the server can be realized.

Abstract: A method for providing proactive synchronization in a computer system includes a processor requesting exclusive access to a given memory resource. The request may include one or more addresses associated with the given memory resource. The method also includes comparing each of the addresses in the request to each address in a plurality of sets of addresses. Each address in the sets of addresses may correspond to a respective memory resource to which a requestor has exclusive access. In addition, in response to any address of the one or more addresses matching any address in the plurality of sets of addresses, the method includes returning a count value associated with the set including the matching address. The count value may be indicative of the number of requestors contending for the matching address. Software may utilize this count value to proactively choose an item with lower contention probabilities in subsequent attempts.

Abstract: A memory controller and a method for improved computer system performance invalidates (i.e., cancels or does not allow for execution of) speculative or unnecessary scrub write commands as part of the periodic execution of the overall scrub command upon the occurrence of certain events, such as if the error checking and correction (ECC) operation indicates that the data were received without error or if the ECC operation indicates that the data received have an uncorrectable error.

Abstract: A memory flush is processed in accordance with a state machine that keeps track of the flush states of a memory target. A memory target is not flushed if it has not been written to, or if a memory flush has already been completed for that memory target. A memory target is flushed if the memory partition is in a flush needed state or a flush pending state. Each memory target has an associated state machine, but only one state machine is maintained per memory target.

Abstract: A data processing apparatus includes a memory which receives and outputs data with a predetermined data width, an operation circuit which outputs a read command or a write command to access the memory, and an access control circuit which replaces a part of first read data read from the memory with a partial data, and outputs partially replaced data as write data to the memory when receiving the write command and the partial data with a data width smaller than the predetermined data width associated with the write command, from the operation circuit. The access control circuit replaces a part of second read data which has been acquired in response to the read command outputted before, instead of the first read data, with the partial data, and outputs replaced partially data as the write data if the write command has been outputted in connection with a read command outputted before the write command.

Abstract: Methods, apparatuses, and systems are presented for updating data in memory while executing multiple threads of instructions, involving receiving a single instruction from one of a plurality of concurrently executing threads of instructions, in response to the single instruction received, reading data from a specific memory location, performing an operation involving the data read from the memory location to generate a result, and storing the result to the specific memory location, without requiring separate load and store instructions, and in response to the single instruction received, precluding another one of the plurality of threads of instructions from altering data at the specific memory location while reading of the data from the specific memory location, performing the operation involving the data, and storing the result to the specific memory location.

Abstract: A method for denying probes during proactive synchronization includes a first processor operating in an advanced synchronization mode, which includes the first processor specifying and acquiring exclusive access to a given memory resource. During operation in the advanced synchronization mode, specifying comprises executing a code sequence including: one or more locked memory reference instructions having a LOCK prefix and one or more addresses associated with the given memory resource. Specifying also includes executing an ACQUIRE instruction that is subsequent to the one or more locked memory reference instructions. The method further includes a second processor requesting access to the given memory resource and issuing a probe message. In response to receiving the probe message, the first processor responding to the probe message with a failure message, thereby denying the second processor access to the given memory resource.

Abstract: The write optimizer described in this disclosure optimizes write traffic to a disk. The write optimization technique writes small data sets to be written to a disk drive to a log file in write optimized order and rewrites the small data sets to disk drive in read optimized order when the disk drive is idle. The write optimizer reserves a portion of a disk to be used for write performance improvement, and then takes all small writes to the disk and writes them to the reserved area rather than to their intended destination. When the disk becomes idle (or the reserved area full), the write optimizer takes the data that has been written to the reserved area and that has not been subsequently overwritten and copies it to its final location.

Abstract: In a semiconductor storage device 10 included in a liquid container 20, on reception of an encoding request for encoding readout data, a write-read controller 140 changes over the position of a switch 141 to output encoded readout data, which is obtained by an encoding operation in a data encoding circuit 150, to a data signal terminal SDAT. In the case of no reception of the encoding request for encoding the readout data, on the other hand, the write-read controller 140 changes over the position of the switch 141 to output raw data read out from a memory array 100 to the data signal terminal SDAT.

Abstract: A system comprises a first node that provides a broadcast request for data. The first node receives a read conflict response to the broadcast request from the first node. The read conflict response indicates that a second node has a pending broadcast read request for the data. A third node provides the requested data to the first node in response to the broadcast request from the first node. The first node fills the data provided by the third node in a cache associated with the first node.

Abstract: A circuit includes a memory having error correction, circuitry which initiates a write operation to memory. When error correction is enabled and the write operation to the memory has the width of N bits, the write operation to the memory is performed in one access to the memory, and when error correction is enabled and the write operation to the memory has the width of M bits, where M bits is less than N bits, the write operation to the memory is performed in more than one access to the memory. In one example, the one access to the memory includes a write access to the memory, and the more than one access to the memory includes a read access to the memory and a write access to the memory.

Abstract: Automatic software controlled caching generations in network applications are described herein. In one embodiment, a candidate representing a plurality of instructions of a plurality of threads that perform one or more external memory accesses is identified, where the external memory accesses have a substantially identical base address. One or more directives and/or instructions are inserted into an instruction stream corresponding to the identified candidate to maintain contents of at least one of a content addressable memory (CAM) and local memory (LM) of a processor, and to modify at least one of the external memory access to access at least one of the CAM and LM of the processor without having to perform the respective external memory access. Other methods and apparatuses are also described.

Abstract: Providing proactive synchronization in a computer system may include providing an augmented instruction set with additional synchronizing instructions. Therefore, a method includes a processor executing a set of instructions to request exclusive access to a plurality of memory resources. The set of instructions includes an ACQUIRE instruction. In addition, the method may include storing addresses referenced by the set of instructions within a buffer. Further, the method may include sending the addresses referenced by the set of instructions, as a set, to be compared to other addresses to which exclusive access to memory addresses has been granted in response to execution of the ACQUIRE instruction.

Abstract: A programmable control interface is for circuits using complex commands. The programmable interface includes a memory for storing sampled commands and a sequencing circuit. The sequencing circuit is programmable. Thus, a processor downloads into the programmable interface a sequencing specific to the sequence of commands. Once the programmable interface has been programmed, the processor launches the start of the sequence and the programmable interface manages and controls in a standalone manner the inputs/outputs with the slave circuit. The management and control of the slave circuit is independent of any interrupt specific to the system. The programmable interface uses a software-type upgrade to interface with new slave circuits that may appear on the market.

Abstract: A computer, which includes multiple memory modules each of which is provided with an SPD for storing setting information about the memory, a setting information acquisition section of an SPD controller of a memory controller, obtains setting information from the SPD of each memory module, and the setting information is held in a setting information holding section. The storage control device of the computer compares the acquired pieces of setting information. When the contents of the pieces of setting information are different from one another, the storage control device overwrites setting information in the SPD's of the memory modules other than the memory module corresponding to the setting information by using the contents of any one of the pieces of setting information.

Abstract: A memory includes a plurality of blocks that each include a plurality of memory cell arrays connected to divided bit lines, a first decoder that generates a block select signal for selecting any of the blocks based on an inputted address signal, read/write portions disposed for the respective blocks, each of the read/write portions executes read or write of the memory cell array belonging to the block of its own, and signal generation portions each generates an operation control signal for bringing the read/write portion that belongs to the selected block into an operating state when the block thereof has been selected by the block select signal. Each of the signal generation portions generates an operation control signal for bringing the read/write portion that belongs to the block thereof into a non-operating state when the block thereof is not selected by the block select signal.

Abstract: An apparatus, system, and method are disclosed for coordinating storage requests in a multi-processor/multi-thread environment. A append/invalidate module generates a first append data storage command from a first storage request and a second append data storage command from a second storage request. The storage requests overwrite existing data with first and second data including where the first and second data have at least a portion of overlapping data. The second storage request is received after the first storage request. The append/invalidate module updates an index by marking data being overwritten as invalid. A restructure module updates the index based on the first data and updates the index based on the second data. The updated index is organized to indicate that the second data is more current than the first data regardless of processing order. The modules prevent access to the index until the modules have completed updating the index.

Abstract: Systems and methods for providing data modification operations in memory subsystems. Systems include a plurality of memory devices, a memory controller, one or more memory busses connected to the memory controller and a memory hub device. The memory controller receives and responds to memory access requests including memory update requests from a processor. The memory controller also generates a memory update command in response to receiving a memory update request. The memory hub device includes a first port, a second port and a control unit. The first port is in communication with the memory controller via one or more of the memory busses for transferring data and control information between the memory hub device and the memory controller. The second port is in communication with one or more of the memory devices.

Abstract: A method, system, and computer program product for storing result data from an external device. The method includes receiving the result data from the external device, the receiving at a system. The result data is stored into a store data buffer. The store data buffer is utilized by the system to contain store data normally generated by the system. A special store instruction is executed to store the result data into a memory on the system. The special store instruction includes a store address. The executing includes performing an address calculation of the store address based on provided instruction information, and updating a memory location at the store address with contents of the store data buffer utilizing a data path utilized by the system to store data normally generated by the system.

Abstract: A method for generating a modified packet for output from a router. First, a received packet is stored in one memory location. Modified bytes corresponding to the received packet are computed and stored in a separate memory location. The modified packet is generated by multiplexing between select unmodified bytes of the received packet with the modified bytes.

Abstract: A method of regeneration of a recording state of digital data stored in a node of a data network, the method including the steps of classifying files stored in the node, periodically writing a digital file from the node to a temporary memory, the temporary memory being a component of said node, and writing the digital file from the temporary memory to the same node.