Status Storage Patents (Class 711/156)
  • Patent number: 11442900
    Abstract: A method, system and computer program product for sharing resources among remote repositories. In a shared file system, a resource identifier and metadata are created for a resource, where the resource identifier is stored in a lock file in a shared volume accessible by the remote repositories. The lock file is then released in response to distributing the associated resource to the remote repositories. Alternatively, in a peer-to-peer system, a request is received to create, read, update or delete a resource stored in a content repository. A resource name, a resource version and/or a resource fingerprint are received in connection with the request to create, read, update or delete the resource in the content repository. A determination is then made as to whether the received resource name, resource version and/or resource fingerprint matches the respective resource name, resource version and/or resource fingerprint stored in a node graph for the resource.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: September 13, 2022
    Assignee: International Business Machines Corporation
    Inventors: Barry P. Gower, Larry R. Hamann, Andrew S. Myers, Seth R. Peterson, Davanum M. Srinivas, Donald R. Woods
  • Patent number: 11436105
    Abstract: A data processing method includes: configuring a predetermined memory space to record information regarding data to be backed up of a memory device, where the information is used to indicate data associated to which logical memory space is the data to be backed up; and updating the information according to commands received from a host device.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: September 6, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yen-Chung Chen, Yi-Ting Wei, Tzu-Yu Chao, Ming-Yuh Yeh
  • Patent number: 11435919
    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to perform operations comprising opening a block family associated with the memory device; initialize a timer associated with the block family; assigning a plurality of cursors to the block family; responsive to programming a first block associated with a first cursor of the memory device, associating the first block with the block family; responsive to programming a second block associated with a second cursor of the memory device, associating the second block with the block family; and responsive to detecting expiration of the timer, closing the block family.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Bruce A. Liikanen, Peter Feeley, Larry J. Koudele, Shane Nowell, Steven Michael Kientz
  • Patent number: 11409707
    Abstract: A method, system and computer program product for sharing resources among remote repositories. In a shared file system, a resource identifier and metadata are created for a resource, where the resource identifier is stored in a lock file in a shared volume accessible by the remote repositories. The lock file is then released in response to distributing the associated resource to the remote repositories. Alternatively, in a peer-to-peer system, a request is received to create, read, update or delete a resource stored in a content repository. A resource name, a resource version and/or a resource fingerprint are received in connection with the request to create, read, update or delete the resource in the content repository. A determination is then made as to whether the received resource name, resource version and/or resource fingerprint matches the respective resource name, resource version and/or resource fingerprint stored in a node graph for the resource.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: August 9, 2022
    Assignee: International Business Machines Corporation
    Inventors: Barry P. Gower, Larry R. Hamann, Andrew S. Myers, Seth R. Peterson, Davanum M. Srinivas, Donald R. Woods
  • Patent number: 11409451
    Abstract: Systems, methods, and storage media for using the otherwise-unutilized storage space on a storage device without having a substantial effect on the normal operation of the storage device by one or more users accessing the storage device through one or more primary file organization architecture controllers of the storage device are disclosed.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: August 9, 2022
    Assignee: Veriblock, Inc.
    Inventors: Justin Fisher, Maxwell Sanchez
  • Patent number: 11360708
    Abstract: Technologies are provided for supporting storage device write barriers. A storage device can be configured to associate a data access command with a write barrier. The write barrier can be used to indicate that one or more data access commands should be processed before one or more other data access commands are processed. For example, a host computer can transmit one or more data access commands to a storage device. The storage device can determine that the one or more data access commands are associated with a write barrier. The host computer can continue to transmit additional data access commands to the storage device. However, the storage device will not process the additional data access commands until after the one or more data access commands associated with the write barrier have been processed.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: June 14, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Munif M. Farhan, Keun Soo Jo, James Alexander Bornholt, Andrew Kent Warfield, Andrew C. Schleit, Seth W. Markle
  • Patent number: 11347434
    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a read command specifying an identifier of a logical block and a page number; translate the identifier of the logical block into a physical address of a physical block stored on the memory device, wherein the physical address comprises an identifier of a memory device die; identify, based on block family metadata associated with the memory device, a block family associated with the physical block and the page number; determine a threshold voltage offset associated with the block family and the memory device die; compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the memory device die; and read, using the modified threshold voltage, data from a physical page identified by the page number within the physical block.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Mark Ish
  • Patent number: 11301149
    Abstract: Embodiments of the present disclosure relate to an electronic apparatus that includes a metadata generator, to generate an extents table (ET) that lists one or more extents pages (EPs), where an EP is a fixed size, and where the one or more EPs store one or more extents. An extent includes an allocation indication for a cluster in a memory device, where a number of the extents corresponds to a number of clusters of the memory device, where a subset number of the extents is stored in one of the one or more EPs, and where the subset number is based on the fixed size of the EP. The electronic apparatus further includes a metadata updater, to modify the allocation indication in the extent stored in the one of the one or more EPs, based on a corresponding change in an allocation of the cluster in the memory device.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: James Harris, Benjamin Walker, Tomasz Zawadzki
  • Patent number: 11232073
    Abstract: Example methods and apparatuses for file compaction in a key-value store system relating to the field of data processing technologies are described. One example method for file compaction in a key-value store (KV-Store) system includes compacting, according to a to-be-deleted log (Delete Log) that corresponds to a to-be-compacted sorted string table (SSTable), the to-be-compacted SSTable to generate a new SSTable. A key corresponding to a non-latest value in the KV-Store system and stored in the to-be-compacted SSTable is recorded in the Delete Log, and the new SSTable does not include a key-value pair that corresponds to the key in Delete Log. The to-be-compacted SSTable is then deleted.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: January 25, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Shimin Chen, Liangchang Zhu, Jun Zhang
  • Patent number: 11231991
    Abstract: An SOC includes a security processor. The security processor includes an encryption/ECC encoding processor configured to perform an encryption operation on data using Metadata and to generate ECC data by performing ECC encoding processing on encrypted data and the Metadata, a decryption/ECC decoding processor configured to extract the encrypted data and the Metadata by performing ECC decoding processing using the ECC data and to recover the data by performing a decryption operation on the encrypted data using the Metadata, and an address controller configured to receive a first address related to storage of the data, to generate a second address based on the first address, and to perform an address generating operation identifying a same region in memory for storing the Metadata and the ECC data based on the second address.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 25, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-goo Heo, Yoon-bum Seo, Young-jin Chung, Jin-su Hyun
  • Patent number: 11227661
    Abstract: A controller controls an operation of a semiconductor memory device. The controller includes an erased page search controller, a command generator, and a data receiver. The erased page search controller determines a search mode of the semiconductor memory device, selects a page to search for, among a plurality of pages, based on the search mode, and generates a search control signal corresponding to a selected page. The command generator generates a search read command for the selected page based on the search control signal. The data receiver receives, from the semiconductor memory device, search read data corresponding to the search read command. The search read command is a command for controlling the semiconductor memory device to perform a read operation by applying a read voltage to multiple word lines including a word line corresponding to the selected page.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: January 18, 2022
    Assignee: SK hynix Inc.
    Inventor: Jiman Hong
  • Patent number: 11228574
    Abstract: The disclosure describes systems, methods and devices relating to a sign-on and management hub or service for users of multiple internal, external or Software-as-a-Service (SaaS) software applications (Apps), with options for centralized management and sharing of accounts without needing to provide login credentials to individual users.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: January 18, 2022
    Assignee: Google LLC
    Inventors: Erik Gustavson, Scott Kriz, Aaron Eisenberger, Garrett Brown, Jason Carulli, Andrew Arrow, Prashant Nadarajan, Fong Woh Fai, Chung Weng Wai, Saw Kee Wooi
  • Patent number: 11216211
    Abstract: Technology is described for controlling different types of physical devices in a device farm hosted in a service provider environment. A removable storage slot adapter may be physically inserted into a removable storage slot of a physical device. The removable storage slot adapter may present an emulated removable storage device using a removable storage configuration obtained over a network from a management service hosted by the service provider environment. The removable storage slot adapter may interpret commands from the device to access data blocks of the emulated removable storage device. The removable storage slot adapter may access a storage service hosted by the service provider environment to fulfill the commands and data access operations requested from the device.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: January 4, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Mauricio Da Silva Miranda, Calvin Yue-Ren Kuo, Jonathan I. Turow
  • Patent number: 11182294
    Abstract: A data processing apparatus 2 includes a cache memory 8 for storing data items to be accessed. Coherency control circuitry 20 controls coherency between data items stored within the cache memory and one or more other copies of the data items stored outside the cache memory. A data access buffer 6 buffers a plurality of data access to respective data items stored within the cache memory. Access control circuitry 20 is responsive to coherency statuses managed by the coherency control circuitry for the plurality of data items to be subject to data access operations to be performed together atomically as an atomic set of data accesses to ensure that the coherency statuses for all of these data items permit all of the atomic set of data accesses to be performed within the cache memory before the set of atomic data accesses are commenced.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: November 23, 2021
    Assignee: ARM Limited
    Inventors: Jason Parker, Graeme Peter Barnes
  • Patent number: 11182363
    Abstract: A method for validating data in a copy repository is disclosed. In one embodiment, such a method includes establishing a template that designates valid fields within a data set, as well as valid values and types of data within the fields. The method further establishes a timeframe over which to validate versions of the data set residing in a copy repository. Starting at a first end of the timeframe and proceeding to a second end, the method validates each version of the data set residing in the copy repository. To accomplish this, the method configures a computing system to a state that existed when the version was created in the copy repository. The method then opens the version on the computing system and validates the version against the template. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: David C. Reed, Gregory E. McBride
  • Patent number: 11176032
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving a first write command from a host, the controller determines a first physical address indicative of a physical storage location of the nonvolatile memory to which first write data associated with the first write command is to be written, and updates an address translation table such that the first physical address is associated with a logical address of the first write data. The controller starts updating the address translation table before the transfer of the first write data is finished or before the write of the first write data to the nonvolatile memory is finished.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: November 16, 2021
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11151031
    Abstract: Methods and systems are disclosed for optimizing record placement in defragmenting a graph database. Issues with fragmented data within a graph database are addressed on the record level by placing data that is frequently accessed together contiguously within memory. For example, a dynamic rule set may be developed based on dynamically analyzing access patterns of the graph database, policies, system characteristics and/or other heuristics. Based on statistics regarding normal query patterns, the systems and methods may identify an optimal position for certain types of edges that are often traversed with respect to particular types of nodes.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: October 19, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Åge Kvalnes, Jan-Ove Karlberg, Tor Kreutzer, Amund Kronen Johansen, Steffen Viken Valvåg
  • Patent number: 11119874
    Abstract: A memory fault detection method includes: receiving a first interrupt signal sent when a count value of a first leaky bucket counter of a server reaches a first threshold; disabling an interrupt switch of the first leaky bucket counter; enabling the interrupt switch of the first leaky bucket counter after the interrupt switch of the first leaky bucket counter has been disabled for a preset time and the count value of the first leaky bucket counter is reset to zero; receiving a second interrupt signal sent when a count value of a second leaky bucket counter reaches a second threshold; if the second leaky bucket counter and the first leaky bucket counter are a same leaky bucket counter, and the second rank and a first rank are a same rank, determining that a hardware fault occurs in the first rank.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: September 14, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Gang Song, Chengguo Ding, Fei Zhang
  • Patent number: 11099949
    Abstract: A method and apparatus for programming a one-time programmable (OTP) memory device is disclosed that allows for resuming and recovering from an interrupted programming cycle (e.g. due to loss of power or user interaction). Upon re-initiation of a programming cycle with the same memory range, a programming controller may detect the memory address where interruption occurred, and resume programming from that address. If the programming interruption resulted in an incorrectly programmed word at the interrupted address, a word repair register may be mapped to the corrupted address to enable correction of that word. The remainder of the memory range may then be programmed normally.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: August 24, 2021
    Assignee: Cirrus Logic, Inc.
    Inventors: Michael A Kost, Bradley A Lambert, John P Tourish, Girish Subramaniam
  • Patent number: 11086517
    Abstract: Memory management that includes allocating physical memory having an append-only permission associated therewith to requesting user space applications is described. If a page frame is append-only, then data written to the page frame cannot be overwritten. Rather, any new data written to an append-only page frame must be written beginning at the next available write location within the page frame. An MMU determines whether a write request is requesting an append-only page frame, in which case, the MMU reserves the append-only page frame for the write request and consults a corresponding entry in a page table append to determine whether an offset associated with the write request is larger than a stored value in the entry that indicates the next available write location in the page frame. If so, the write request is executed and the data is written to the page frame beginning at the next available write location.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: August 10, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Breno H. Leitao, Juscelino Candido De Lima Junior, Carlos Eduardo Seo
  • Patent number: 11062777
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: July 13, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Jun Nakai, Noboru Shibata
  • Patent number: 11061607
    Abstract: There are provided an electronic system and an operating method thereof. The electronic system includes: a host for queuing an external command to wait or to be output, based on a status of dies included in a storage device; a central processing unit for generating a command for controlling the storage device in response to a request received from the host or the external command; and a controller memory buffer for storing status information indicating whether the dies are in a status in which access is possible or a status in which access is impossible, wherein the central processing unit receives status information of the dies from the storage device, and stores status information matched to each of the dies in the controller memory buffer.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Duck Hoi Koo, Yong Jin
  • Patent number: 11048417
    Abstract: Techniques perform storage management. Such techniques involve: detecting a change of a size of storage space for a file system, the file system having one or more associated bitmaps, each active bit in the one or more bitmaps indicating data status in storage space not exceeding an upper size limit of the file system; in response to detecting the change, determining, based on the upper size limit, a first number of bits required for indicating the changed storage space; and in response to determining that the first number exceeds a second number of current active bits in the one or more bitmaps, allocating at least one additional active bit for the file system. Accordingly, the number of bits for indicating the file system can be dynamically adjusted based on the changes of the file system.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: June 29, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Yue Yang, Xin Zhong, Yangfeng Chen, Qinghua Ling, Yan Shao
  • Patent number: 11042435
    Abstract: A circuit apparatus 100 includes: an interface circuit 120 that receives setting data; and a control circuit 110 that controls the operations of the circuit apparatus 100 based on the setting data and also controls access to a nonvolatile memory 10. The control circuit 110 generates error detection data based on the setting data received by the interface circuit 120, and writes the setting data and the error detection data to the nonvolatile memory 10.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: June 22, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Atsushi Ishikawa
  • Patent number: 11017838
    Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: May 25, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee-Woong Kang, Dong-Hun Kwak, Jun-Ho Seo, Hee-Won Lee
  • Patent number: 11010074
    Abstract: Disclosed is a system and method for providing host adjustable performance parameters for SSDs. The method includes accessing a latency profile based on a determined device age of a solid state drive (SSD). The method also includes providing for display a user interface comprising a plurality of interface elements to adjust a respective plurality of performance specifications of the SSD, wherein the user interface is configured based on the latency profile. The method also includes receiving, via the user interface, an adjustment to the plurality of performance specifications. The method also includes sending an instruction to the SSD to configure the SSD with a parameter set based on the adjusted plurality of performance specifications.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: May 18, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Navneeth Kankani, Linh Tien Truong
  • Patent number: 11003642
    Abstract: Columnar storage provides many performance and space saving benefits for analytic workloads, but previous mechanisms for handling single row update transactions in column stores suffer from poor performance. A columnar data layout facilitates both low-latency random access capabilities together with high-throughput analytical access capabilities, simplifying Hadoop architectures for use cases involving real-time data. In disclosed embodiments, mutations within a single row are executed atomically across columns and do not necessarily include the entirety of a row. This allows for faster updates without the overhead of reading or rewriting larger columns.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: May 11, 2021
    Assignee: Cloudera, Inc.
    Inventor: Todd Lipcon
  • Patent number: 10983820
    Abstract: A computer-implemented method includes receiving a request for storage for a container and determining whether a suitable thin provisioned volume currently exists based on criteria in the request. In response to determining that a suitable thin provisioned volume currently exists, the method includes selecting an unused portion of the thin provisioned volume and creating a container volume in the selected unused portion of the thin provisioned volume. The method also includes permitting input/output (I/O) to the container volume and releasing the selected unused portion of the thin provisioned volume in response to determining the container volume is no longer needed.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sandeep Bangur, Pankaj Deshpande, Aakanksha Mathur, Pradip Waykos
  • Patent number: 10976928
    Abstract: Technologies for identifying data stored on a solid state drive (“SSD”) device that correspond to data associated with a delete event, and marking the deleted data stored on the SSD as invalid such that the SSD can avoid unnecessary operations on the invalid data. Included are interfaces operable to communicate invalid data information and providing a remove-on-delete command that provides invalid data information sufficient to identify the SSD data to be marked as invalid.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: April 13, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Frank J. Shu, Nathan S. Obr
  • Patent number: 10970227
    Abstract: A data processing apparatus is provided, comprising a processor configured to execute a process, in particular with at least one thread, a memory management unit component configured to access a page table, and a page fault handler configured to handle page faults by triggering a page fault in response to detecting one of a plurality of predefined bit patterns in the page table, and by assigning a different page fault operation for the process, in particular with the at least one thread, to each of the plurality of predefined bit patterns.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: April 6, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Jani Kokkonen
  • Patent number: 10949115
    Abstract: A Data Storage Device (DSD) includes a flash memory for storing data. Portions of the flash memory are grouped into logical groups based on at least one of a number of Program/Erase (P/E) cycles and a physical level location of the portions of the flash memory. A command performance latency is monitored for each logical group, and at least one polling time for each respective logical is set based on the monitored command performance latency for the logical group. The at least one polling time indicates a time to wait before checking whether a portion of the flash memory in the logical group has completed a command.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 16, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chao Sun, Xinde Hu, Dejan Vucinic
  • Patent number: 10929263
    Abstract: In one example implementation according to an embodiment described herein, a computer-implemented method includes detecting input/output (I/O) interrupts for executing I/O operations occurring over a period of time. The method further includes calculating an I/O interrupt delay time (IIDT) for each I/O interrupt occurring during the period of time. The method further includes binning the IIDT for each I/O interrupt occurring during the period of time into one of a plurality of bins based on a value of the IIDT, each of the plurality of bins storing a count of IIDT values within a defined range. The method further includes determining a highest IIDT value. The method further includes identifying a performance degradation based at least on one of the count of IIDT values of each of the plurality of bins or the highest IIDT value. The method further includes implementing a corrective action to mitigate the performance degradation.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: February 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Richard Paveza, Harry M Yudenfriend
  • Patent number: 10929382
    Abstract: In general, embodiments of the invention relate to methods and systems for replicating data, which is stored in a source system, in a target system. More specifically, embodiments of the invention enable parallel transmission and verification of portions of the data. Once the portions of the data have been verified, embodiments of the invention combine the verified portions of the data to obtain the final combined data. The combined data is then verified.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: February 23, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Krithika Subramanian, Srisailendra Yallapragada, Harshadrai Parekh, Bhimsen Bhanjois
  • Patent number: 10909029
    Abstract: Methods, computer program products, and systems for managing memory in a computer system in which memory locations in use at any given time are represented as a set of memory objects in a first object graph. The first object graph includes a system root object associated by references to each of the memory objects. A method includes creating a second root object for the memory to form a second object graph for the memory. The method also includes, in response to the dereferencing of a first object from the first object graph, associating the dereferenced first object with the second object graph so that the second object graph includes at least one dereferenced object.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: February 2, 2021
    Assignee: International Business Machines Corporation
    Inventor: Edward J. Slattery
  • Patent number: 10878898
    Abstract: A memory system includes a first memory, a second memory, and a first circuit. The first memory includes a memory cell array including memory cell transistors, and a peripheral circuit configured to read data of a plurality of bits stored in a memory cell transistor of the memory cell array based on a comparison between threshold voltages of the memory cell transistor and at least a part of n determination voltages (n?3). The first circuit is configured to calculate an estimated value of each of n?m determination voltages based on values of m determination voltages (2?m?n?1) among the n determination voltages, and calculate a difference between a value of each of the n?m determination voltages and a corresponding estimated value. The second memory is configured to store values of the m determination voltages and the difference for each of the n?m determination voltages.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: December 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ryo Sekiguchi, Shingo Yanagawa, Yasuhiko Kurosawa, Eriko Akaihata
  • Patent number: 10846265
    Abstract: A method and an apparatus for accessing a file, and a storage system. The method includes: determining L first-file invoking request messages; separately adding, according to physical sector information in the L first-file invoking request messages, the L first-file invoking request messages to M first-file dispatch queues; and processing a first-file invoking request message included in each first-file dispatch queue, to obtain an invoking request message of each first-file dispatch queue, where the invoking request message is used to access a first file. By means of the method and apparatus for accessing a file and the storage system in the embodiments of the present disclosure, a corresponding dispatch queue is allocated to an invoking request message of a micro file, so that combination processing can be performed on invoking request messages of multiple micro files, and a quantity of times of invoking a micro file is reduced.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: November 24, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Guojun Shi, Zhigang Li, Fuzhou Xiao
  • Patent number: 10827081
    Abstract: Server receives a log from a client apparatus, the client apparatus generating the log after the client apparatus executes a function, the log including a function identifier identifying the function, execution start date-and-time and execution end date-and-time of the function, and a setting value of each of one or more setting items about the function, determines whether or not performance of the function identified by the function identifier included in the received log is lower than a certain criterion on a basis of the execution start date-and-time and the execution end date-and-time included in the received log, and if the server apparatus determines that the performance of the function is low, sends a setting value stored in the storage device to the client apparatus, the setting value being a setting value, with which the performance was high, of each of the one or more setting items about the function-low-in-performance.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: November 3, 2020
    Assignee: KYOCERA DOCUMENT SOLUTIONS INC.
    Inventor: Maya Hiwatari
  • Patent number: 10824513
    Abstract: An apparatus in one embodiment comprises at least one processing device having a processor coupled to a memory. The processing device is configured to maintain, for logical storage volumes of a storage system, device sequence numbers for snapshot and extent copy operations. The processing device is also configured to maintain, for at least one track of the logical storage volumes, a track sequence number representing the state of the track with respect to the snapshot and extent copy operations. The processing device is further configured to receive input/output operations directed to the logical storage volumes from host devices coupled to the storage system while at least one snapshot or extent copy operation for the logical storage volumes is in progress, and to utilize the track sequence numbers and the device sequence numbers to determine processing of the received input/output operations while the snapshot or extent copy operations are in progress.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: November 3, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Sandeep Chandrashekhara, David T. Tsang, Michael Ferrari, Jeffrey Wilson, Mark J. Halstead
  • Patent number: 10817501
    Abstract: Embodiments are provided for managing shared states of objects associated with a distributed database. According to certain aspects, a reactor machine interfaces with a coordination service that is in communication with the distributed database to coordinate the shared states of the objects. The coordination service notifies the reactor machine when a shared state of an object has changed and, in response, the reactor machine determines a desired state of the object by executing a reactor function. The reactor machine provides the desired state of the object to the coordination service, and the coordination service updates the shared state of the object to reflect the desired state of the object. Accordingly, the logic of the reactor machine is de-coupled from the complexities of the coordination service.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: October 27, 2020
    Assignee: Twitter, Inc.
    Inventors: Peter Schuller, Sumeet Lahorani, Stuart Hood
  • Patent number: 10809946
    Abstract: An optional array in a memory includes an array having blocks each including an address word and a data word, and a boundary that is a position where a ratio between the numbers of unwritten blocks in M area and written blocks in W area is an integer ratio. The controlling process includes when a second write for writing a special value in a written block in the second area is invoked, executing a shrink process of shifting the boundary to shrink the first area; in a case where the first adjacent block at the boundary is a written block, storing an address of the first adjacent block and of a first link destination block forming a link with the write destination block in address words of the first link destination block and of the first adjacent block respectively to form a link.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: October 20, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Takashi Katoh, Keisuke Goto
  • Patent number: 10795776
    Abstract: A computer program product, according to one embodiment, includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. Moreover, the program instructions readable and/or executable by a processor to cause the processor to perform a method which includes: maintaining, by the processor, a cascaded mapping relationship at a secondary system. The cascaded mapping relationship extends between the secondary system and a remote primary system.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andrea Sipka, John P. Wilkinson
  • Patent number: 10788988
    Abstract: A system and associated methodology for controlling block duplicates when deduplicating data (Dedup Blocks) to a storage space. The system includes a persistent database of known duplicates stored in the storage space (KD Table), and a non-persistent database of possible duplicates stored in the storage space (PD Table). Computer logic executes programming instructions stored in memory that are configured to index the KD Table according to a value derived from bits of a Dedup Block's hash signature, to index the PD Table according to another value derived by other bits of the Dedup Block's hash signature, to demote known duplicates from the KD Table to the PD Table, and to promote possible duplicates from the PD Table to the KD Table.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: September 29, 2020
    Assignee: VIOLIN SYSTEMS LLC
    Inventors: Richard F. Lary, Bill Wong
  • Patent number: 10778762
    Abstract: A service control system manages a set of storage clients operating within one or more computing hosts. Storage clients may access a consistent storage system regardless which cloud provider the computing hosts come from. To provide storage, each logical volume accessed by a container is associated with a microcontroller at the computing host. The microcontroller is managed by the service control system and stores data for the logical volume at two or more replicas on different computing hosts.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: September 15, 2020
    Assignee: Rancher Labs, Inc.
    Inventors: Sheng Liang, Oleg Smolsky
  • Patent number: 10769065
    Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: September 8, 2020
    Assignee: Apple Inc.
    Inventors: Ali Sazegari, Charles E. Tucker, Jeffry E. Gonion, Gerard R. Williams, III, Chris Cheng-Chieh Lee
  • Patent number: 10754767
    Abstract: The present disclosure discloses a method and an apparatus for loading a resource in a web page on a device as well as a computer-readable storage medium. Wherein, the method comprises: determining whether a current available memory level of the device is normal or low; loading the resource in the web page according to the current available memory level; wherein, if the current available memory level is low, loading the resource in the web page according to the current available memory level further comprises: loading a specified resource tailored from the resource in the web page. According to the embodiments of the present disclosure, lots of memory may be saved and the loading speed may be improved. Therefore the browser resided in the device may be prevented from being broken, and the user experiences may be improved.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: August 25, 2020
    Assignee: Guangzhou UCWeb Computer Technology Co., Ltd.
    Inventor: Xiaozhen Wang
  • Patent number: 10747672
    Abstract: Embodiments of the present disclosure relate to a method and device and computer readable medium for storage management. The method comprises determining a queuing condition of I/O requests of a cache of a first file system in a storage, the cache including at least one flash block. The method further includes determining a load condition of the cache based on the queuing condition of the I/O requests. Moreover, the method further includes in response to determining that the cache is in a busy status, allocating to the cache at least one additional flash block from a second file system in the storage, the second file system being different from the first file system.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: August 18, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Leon Zhang, Lester Zhang, Chen Gong
  • Patent number: 10732881
    Abstract: In some examples, region cloning may include obtaining a clone request to clone a logical range of a source backup. The clone request may specify the source backup, a logical start offset, and a logical end offset. A source manifest associated with the logical range of the source backup may be determined. A start entry of the source manifest may be identified based on the logical start offset. The start entry may represent a start data chunk. A determination may be made as to whether the logical start offset represents an intermediate position of the start data chunk, and if so, a start partial chunk entry representing a sub-range of the start data chunk may be appended to a destination manifest. A backup of the logical range of the source backup may be generated based on the destination manifest with the appended start partial chunk entry.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: August 4, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Richard Phillip Mayo, David Malcolm Falkinder
  • Patent number: 10705961
    Abstract: A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Yen-Cheng Liu, Bahaa Fahim, Erik G. Hallnor, Jeffrey D. Chamberlain, Stephen R. Van Doren, Antonio Juan
  • Patent number: 10705975
    Abstract: Methods, systems, and apparatus for determining whether an access bit is set for each page table entry of a page table based on a scan of the page table with at least one page table walker, the access bit indicating whether a page associated with the page table entry was accessed in a last scan period; incrementing a count for each page in response to determining that the access bit is set for the page table entry associated with the page; resetting the access bit after determining whether the access bit is set for each page table entry; receiving a request to access, from a main memory, a first page of data; initiating a page fault based on determining that the first page of data is not stored in the main memory; and servicing the page fault with a DMA engine.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: July 7, 2020
    Assignee: Google LLC
    Inventors: Joel Dylan Coburn, Albert Borchers, Christopher Lyle Johnson, Robert S. Sprinkle
  • Patent number: 10691595
    Abstract: A first request to perform an operation at an address associated with a media is obtained. The operation is issued to a plurality of cache divisions, wherein each cache division comprises a cache controller and a cache memory. A location in another memory associated with the first request is updated, the location in the other memory including a plurality of indicators corresponding to a status of the operation with each of the plurality of cache divisions. Based on one or more responses from the cache division(s), a response to the first request is sent.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 23, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Robert M. Walker, Ashay Narsale