Status Storage Patents (Class 711/156)
  • Patent number: 11119874
    Abstract: A memory fault detection method includes: receiving a first interrupt signal sent when a count value of a first leaky bucket counter of a server reaches a first threshold; disabling an interrupt switch of the first leaky bucket counter; enabling the interrupt switch of the first leaky bucket counter after the interrupt switch of the first leaky bucket counter has been disabled for a preset time and the count value of the first leaky bucket counter is reset to zero; receiving a second interrupt signal sent when a count value of a second leaky bucket counter reaches a second threshold; if the second leaky bucket counter and the first leaky bucket counter are a same leaky bucket counter, and the second rank and a first rank are a same rank, determining that a hardware fault occurs in the first rank.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: September 14, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Gang Song, Chengguo Ding, Fei Zhang
  • Patent number: 11099949
    Abstract: A method and apparatus for programming a one-time programmable (OTP) memory device is disclosed that allows for resuming and recovering from an interrupted programming cycle (e.g. due to loss of power or user interaction). Upon re-initiation of a programming cycle with the same memory range, a programming controller may detect the memory address where interruption occurred, and resume programming from that address. If the programming interruption resulted in an incorrectly programmed word at the interrupted address, a word repair register may be mapped to the corrupted address to enable correction of that word. The remainder of the memory range may then be programmed normally.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: August 24, 2021
    Assignee: Cirrus Logic, Inc.
    Inventors: Michael A Kost, Bradley A Lambert, John P Tourish, Girish Subramaniam
  • Patent number: 11086517
    Abstract: Memory management that includes allocating physical memory having an append-only permission associated therewith to requesting user space applications is described. If a page frame is append-only, then data written to the page frame cannot be overwritten. Rather, any new data written to an append-only page frame must be written beginning at the next available write location within the page frame. An MMU determines whether a write request is requesting an append-only page frame, in which case, the MMU reserves the append-only page frame for the write request and consults a corresponding entry in a page table append to determine whether an offset associated with the write request is larger than a stored value in the entry that indicates the next available write location in the page frame. If so, the write request is executed and the data is written to the page frame beginning at the next available write location.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: August 10, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Breno H. Leitao, Juscelino Candido De Lima Junior, Carlos Eduardo Seo
  • Patent number: 11061607
    Abstract: There are provided an electronic system and an operating method thereof. The electronic system includes: a host for queuing an external command to wait or to be output, based on a status of dies included in a storage device; a central processing unit for generating a command for controlling the storage device in response to a request received from the host or the external command; and a controller memory buffer for storing status information indicating whether the dies are in a status in which access is possible or a status in which access is impossible, wherein the central processing unit receives status information of the dies from the storage device, and stores status information matched to each of the dies in the controller memory buffer.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Duck Hoi Koo, Yong Jin
  • Patent number: 11062777
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: July 13, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Jun Nakai, Noboru Shibata
  • Patent number: 11048417
    Abstract: Techniques perform storage management. Such techniques involve: detecting a change of a size of storage space for a file system, the file system having one or more associated bitmaps, each active bit in the one or more bitmaps indicating data status in storage space not exceeding an upper size limit of the file system; in response to detecting the change, determining, based on the upper size limit, a first number of bits required for indicating the changed storage space; and in response to determining that the first number exceeds a second number of current active bits in the one or more bitmaps, allocating at least one additional active bit for the file system. Accordingly, the number of bits for indicating the file system can be dynamically adjusted based on the changes of the file system.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: June 29, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Yue Yang, Xin Zhong, Yangfeng Chen, Qinghua Ling, Yan Shao
  • Patent number: 11042435
    Abstract: A circuit apparatus 100 includes: an interface circuit 120 that receives setting data; and a control circuit 110 that controls the operations of the circuit apparatus 100 based on the setting data and also controls access to a nonvolatile memory 10. The control circuit 110 generates error detection data based on the setting data received by the interface circuit 120, and writes the setting data and the error detection data to the nonvolatile memory 10.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: June 22, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Atsushi Ishikawa
  • Patent number: 11017838
    Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: May 25, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee-Woong Kang, Dong-Hun Kwak, Jun-Ho Seo, Hee-Won Lee
  • Patent number: 11010074
    Abstract: Disclosed is a system and method for providing host adjustable performance parameters for SSDs. The method includes accessing a latency profile based on a determined device age of a solid state drive (SSD). The method also includes providing for display a user interface comprising a plurality of interface elements to adjust a respective plurality of performance specifications of the SSD, wherein the user interface is configured based on the latency profile. The method also includes receiving, via the user interface, an adjustment to the plurality of performance specifications. The method also includes sending an instruction to the SSD to configure the SSD with a parameter set based on the adjusted plurality of performance specifications.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: May 18, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Navneeth Kankani, Linh Tien Truong
  • Patent number: 11003642
    Abstract: Columnar storage provides many performance and space saving benefits for analytic workloads, but previous mechanisms for handling single row update transactions in column stores suffer from poor performance. A columnar data layout facilitates both low-latency random access capabilities together with high-throughput analytical access capabilities, simplifying Hadoop architectures for use cases involving real-time data. In disclosed embodiments, mutations within a single row are executed atomically across columns and do not necessarily include the entirety of a row. This allows for faster updates without the overhead of reading or rewriting larger columns.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: May 11, 2021
    Assignee: Cloudera, Inc.
    Inventor: Todd Lipcon
  • Patent number: 10983820
    Abstract: A computer-implemented method includes receiving a request for storage for a container and determining whether a suitable thin provisioned volume currently exists based on criteria in the request. In response to determining that a suitable thin provisioned volume currently exists, the method includes selecting an unused portion of the thin provisioned volume and creating a container volume in the selected unused portion of the thin provisioned volume. The method also includes permitting input/output (I/O) to the container volume and releasing the selected unused portion of the thin provisioned volume in response to determining the container volume is no longer needed.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sandeep Bangur, Pankaj Deshpande, Aakanksha Mathur, Pradip Waykos
  • Patent number: 10976928
    Abstract: Technologies for identifying data stored on a solid state drive (“SSD”) device that correspond to data associated with a delete event, and marking the deleted data stored on the SSD as invalid such that the SSD can avoid unnecessary operations on the invalid data. Included are interfaces operable to communicate invalid data information and providing a remove-on-delete command that provides invalid data information sufficient to identify the SSD data to be marked as invalid.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: April 13, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Frank J. Shu, Nathan S. Obr
  • Patent number: 10970227
    Abstract: A data processing apparatus is provided, comprising a processor configured to execute a process, in particular with at least one thread, a memory management unit component configured to access a page table, and a page fault handler configured to handle page faults by triggering a page fault in response to detecting one of a plurality of predefined bit patterns in the page table, and by assigning a different page fault operation for the process, in particular with the at least one thread, to each of the plurality of predefined bit patterns.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: April 6, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Jani Kokkonen
  • Patent number: 10949115
    Abstract: A Data Storage Device (DSD) includes a flash memory for storing data. Portions of the flash memory are grouped into logical groups based on at least one of a number of Program/Erase (P/E) cycles and a physical level location of the portions of the flash memory. A command performance latency is monitored for each logical group, and at least one polling time for each respective logical is set based on the monitored command performance latency for the logical group. The at least one polling time indicates a time to wait before checking whether a portion of the flash memory in the logical group has completed a command.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 16, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chao Sun, Xinde Hu, Dejan Vucinic
  • Patent number: 10929382
    Abstract: In general, embodiments of the invention relate to methods and systems for replicating data, which is stored in a source system, in a target system. More specifically, embodiments of the invention enable parallel transmission and verification of portions of the data. Once the portions of the data have been verified, embodiments of the invention combine the verified portions of the data to obtain the final combined data. The combined data is then verified.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: February 23, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Krithika Subramanian, Srisailendra Yallapragada, Harshadrai Parekh, Bhimsen Bhanjois
  • Patent number: 10929263
    Abstract: In one example implementation according to an embodiment described herein, a computer-implemented method includes detecting input/output (I/O) interrupts for executing I/O operations occurring over a period of time. The method further includes calculating an I/O interrupt delay time (IIDT) for each I/O interrupt occurring during the period of time. The method further includes binning the IIDT for each I/O interrupt occurring during the period of time into one of a plurality of bins based on a value of the IIDT, each of the plurality of bins storing a count of IIDT values within a defined range. The method further includes determining a highest IIDT value. The method further includes identifying a performance degradation based at least on one of the count of IIDT values of each of the plurality of bins or the highest IIDT value. The method further includes implementing a corrective action to mitigate the performance degradation.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: February 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Richard Paveza, Harry M Yudenfriend
  • Patent number: 10909029
    Abstract: Methods, computer program products, and systems for managing memory in a computer system in which memory locations in use at any given time are represented as a set of memory objects in a first object graph. The first object graph includes a system root object associated by references to each of the memory objects. A method includes creating a second root object for the memory to form a second object graph for the memory. The method also includes, in response to the dereferencing of a first object from the first object graph, associating the dereferenced first object with the second object graph so that the second object graph includes at least one dereferenced object.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: February 2, 2021
    Assignee: International Business Machines Corporation
    Inventor: Edward J. Slattery
  • Patent number: 10878898
    Abstract: A memory system includes a first memory, a second memory, and a first circuit. The first memory includes a memory cell array including memory cell transistors, and a peripheral circuit configured to read data of a plurality of bits stored in a memory cell transistor of the memory cell array based on a comparison between threshold voltages of the memory cell transistor and at least a part of n determination voltages (n?3). The first circuit is configured to calculate an estimated value of each of n?m determination voltages based on values of m determination voltages (2?m?n?1) among the n determination voltages, and calculate a difference between a value of each of the n?m determination voltages and a corresponding estimated value. The second memory is configured to store values of the m determination voltages and the difference for each of the n?m determination voltages.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: December 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ryo Sekiguchi, Shingo Yanagawa, Yasuhiko Kurosawa, Eriko Akaihata
  • Patent number: 10846265
    Abstract: A method and an apparatus for accessing a file, and a storage system. The method includes: determining L first-file invoking request messages; separately adding, according to physical sector information in the L first-file invoking request messages, the L first-file invoking request messages to M first-file dispatch queues; and processing a first-file invoking request message included in each first-file dispatch queue, to obtain an invoking request message of each first-file dispatch queue, where the invoking request message is used to access a first file. By means of the method and apparatus for accessing a file and the storage system in the embodiments of the present disclosure, a corresponding dispatch queue is allocated to an invoking request message of a micro file, so that combination processing can be performed on invoking request messages of multiple micro files, and a quantity of times of invoking a micro file is reduced.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: November 24, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Guojun Shi, Zhigang Li, Fuzhou Xiao
  • Patent number: 10827081
    Abstract: Server receives a log from a client apparatus, the client apparatus generating the log after the client apparatus executes a function, the log including a function identifier identifying the function, execution start date-and-time and execution end date-and-time of the function, and a setting value of each of one or more setting items about the function, determines whether or not performance of the function identified by the function identifier included in the received log is lower than a certain criterion on a basis of the execution start date-and-time and the execution end date-and-time included in the received log, and if the server apparatus determines that the performance of the function is low, sends a setting value stored in the storage device to the client apparatus, the setting value being a setting value, with which the performance was high, of each of the one or more setting items about the function-low-in-performance.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: November 3, 2020
    Assignee: KYOCERA DOCUMENT SOLUTIONS INC.
    Inventor: Maya Hiwatari
  • Patent number: 10824513
    Abstract: An apparatus in one embodiment comprises at least one processing device having a processor coupled to a memory. The processing device is configured to maintain, for logical storage volumes of a storage system, device sequence numbers for snapshot and extent copy operations. The processing device is also configured to maintain, for at least one track of the logical storage volumes, a track sequence number representing the state of the track with respect to the snapshot and extent copy operations. The processing device is further configured to receive input/output operations directed to the logical storage volumes from host devices coupled to the storage system while at least one snapshot or extent copy operation for the logical storage volumes is in progress, and to utilize the track sequence numbers and the device sequence numbers to determine processing of the received input/output operations while the snapshot or extent copy operations are in progress.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: November 3, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Sandeep Chandrashekhara, David T. Tsang, Michael Ferrari, Jeffrey Wilson, Mark J. Halstead
  • Patent number: 10817501
    Abstract: Embodiments are provided for managing shared states of objects associated with a distributed database. According to certain aspects, a reactor machine interfaces with a coordination service that is in communication with the distributed database to coordinate the shared states of the objects. The coordination service notifies the reactor machine when a shared state of an object has changed and, in response, the reactor machine determines a desired state of the object by executing a reactor function. The reactor machine provides the desired state of the object to the coordination service, and the coordination service updates the shared state of the object to reflect the desired state of the object. Accordingly, the logic of the reactor machine is de-coupled from the complexities of the coordination service.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: October 27, 2020
    Assignee: Twitter, Inc.
    Inventors: Peter Schuller, Sumeet Lahorani, Stuart Hood
  • Patent number: 10809946
    Abstract: An optional array in a memory includes an array having blocks each including an address word and a data word, and a boundary that is a position where a ratio between the numbers of unwritten blocks in M area and written blocks in W area is an integer ratio. The controlling process includes when a second write for writing a special value in a written block in the second area is invoked, executing a shrink process of shifting the boundary to shrink the first area; in a case where the first adjacent block at the boundary is a written block, storing an address of the first adjacent block and of a first link destination block forming a link with the write destination block in address words of the first link destination block and of the first adjacent block respectively to form a link.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: October 20, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Takashi Katoh, Keisuke Goto
  • Patent number: 10795776
    Abstract: A computer program product, according to one embodiment, includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. Moreover, the program instructions readable and/or executable by a processor to cause the processor to perform a method which includes: maintaining, by the processor, a cascaded mapping relationship at a secondary system. The cascaded mapping relationship extends between the secondary system and a remote primary system.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andrea Sipka, John P. Wilkinson
  • Patent number: 10788988
    Abstract: A system and associated methodology for controlling block duplicates when deduplicating data (Dedup Blocks) to a storage space. The system includes a persistent database of known duplicates stored in the storage space (KD Table), and a non-persistent database of possible duplicates stored in the storage space (PD Table). Computer logic executes programming instructions stored in memory that are configured to index the KD Table according to a value derived from bits of a Dedup Block's hash signature, to index the PD Table according to another value derived by other bits of the Dedup Block's hash signature, to demote known duplicates from the KD Table to the PD Table, and to promote possible duplicates from the PD Table to the KD Table.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: September 29, 2020
    Assignee: VIOLIN SYSTEMS LLC
    Inventors: Richard F. Lary, Bill Wong
  • Patent number: 10778762
    Abstract: A service control system manages a set of storage clients operating within one or more computing hosts. Storage clients may access a consistent storage system regardless which cloud provider the computing hosts come from. To provide storage, each logical volume accessed by a container is associated with a microcontroller at the computing host. The microcontroller is managed by the service control system and stores data for the logical volume at two or more replicas on different computing hosts.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: September 15, 2020
    Assignee: Rancher Labs, Inc.
    Inventors: Sheng Liang, Oleg Smolsky
  • Patent number: 10769065
    Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: September 8, 2020
    Assignee: Apple Inc.
    Inventors: Ali Sazegari, Charles E. Tucker, Jeffry E. Gonion, Gerard R. Williams, III, Chris Cheng-Chieh Lee
  • Patent number: 10754767
    Abstract: The present disclosure discloses a method and an apparatus for loading a resource in a web page on a device as well as a computer-readable storage medium. Wherein, the method comprises: determining whether a current available memory level of the device is normal or low; loading the resource in the web page according to the current available memory level; wherein, if the current available memory level is low, loading the resource in the web page according to the current available memory level further comprises: loading a specified resource tailored from the resource in the web page. According to the embodiments of the present disclosure, lots of memory may be saved and the loading speed may be improved. Therefore the browser resided in the device may be prevented from being broken, and the user experiences may be improved.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: August 25, 2020
    Assignee: Guangzhou UCWeb Computer Technology Co., Ltd.
    Inventor: Xiaozhen Wang
  • Patent number: 10747672
    Abstract: Embodiments of the present disclosure relate to a method and device and computer readable medium for storage management. The method comprises determining a queuing condition of I/O requests of a cache of a first file system in a storage, the cache including at least one flash block. The method further includes determining a load condition of the cache based on the queuing condition of the I/O requests. Moreover, the method further includes in response to determining that the cache is in a busy status, allocating to the cache at least one additional flash block from a second file system in the storage, the second file system being different from the first file system.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: August 18, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Leon Zhang, Lester Zhang, Chen Gong
  • Patent number: 10732881
    Abstract: In some examples, region cloning may include obtaining a clone request to clone a logical range of a source backup. The clone request may specify the source backup, a logical start offset, and a logical end offset. A source manifest associated with the logical range of the source backup may be determined. A start entry of the source manifest may be identified based on the logical start offset. The start entry may represent a start data chunk. A determination may be made as to whether the logical start offset represents an intermediate position of the start data chunk, and if so, a start partial chunk entry representing a sub-range of the start data chunk may be appended to a destination manifest. A backup of the logical range of the source backup may be generated based on the destination manifest with the appended start partial chunk entry.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: August 4, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Richard Phillip Mayo, David Malcolm Falkinder
  • Patent number: 10705961
    Abstract: A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Yen-Cheng Liu, Bahaa Fahim, Erik G. Hallnor, Jeffrey D. Chamberlain, Stephen R. Van Doren, Antonio Juan
  • Patent number: 10705975
    Abstract: Methods, systems, and apparatus for determining whether an access bit is set for each page table entry of a page table based on a scan of the page table with at least one page table walker, the access bit indicating whether a page associated with the page table entry was accessed in a last scan period; incrementing a count for each page in response to determining that the access bit is set for the page table entry associated with the page; resetting the access bit after determining whether the access bit is set for each page table entry; receiving a request to access, from a main memory, a first page of data; initiating a page fault based on determining that the first page of data is not stored in the main memory; and servicing the page fault with a DMA engine.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: July 7, 2020
    Assignee: Google LLC
    Inventors: Joel Dylan Coburn, Albert Borchers, Christopher Lyle Johnson, Robert S. Sprinkle
  • Patent number: 10691595
    Abstract: A first request to perform an operation at an address associated with a media is obtained. The operation is issued to a plurality of cache divisions, wherein each cache division comprises a cache controller and a cache memory. A location in another memory associated with the first request is updated, the location in the other memory including a plurality of indicators corresponding to a status of the operation with each of the plurality of cache divisions. Based on one or more responses from the cache division(s), a response to the first request is sent.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 23, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Robert M. Walker, Ashay Narsale
  • Patent number: 10684777
    Abstract: Embodiments of the invention relate to a storage system organized into a hierarchy of storage tiers, with at least one tier reflecting a high performance tier and at least one tier reflecting a lower performance tier. The high performance tier has a capacity restriction and has a limited quantity of blocks and pages may be placed in the tier. Assessments are conducted and a preferred selection of blocks and pages are recommended for placement; the recommendation is based on the assessment. The recommendation is converted to an actual placement, resulting in placement of at least one block, an in one embodiment at least one page, in the high performance tier.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: June 16, 2020
    Assignee: International Business Machines Corporation
    Inventors: David D. Chambliss, Nimrod Megiddo
  • Patent number: 10684969
    Abstract: In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data processing system includes a memory accessing agent for providing memory accesses requests, a memory system, and the memory controller coupled to the memory accessing agent and the memory system.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: June 16, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James R. Magro, Kedarnath Balakrishnan, Jackson Peng, Hideki Kanayama
  • Patent number: 10649784
    Abstract: A system includes a memory including a ring buffer having a plurality of slots, a processor in communication with the memory, a guest operating system, and a hypervisor. The hypervisor is configured to detect a request associated with a memory entry, retrieve up to a predetermined quantity of memory entries in the ring buffer from an original slot to an end slot, and test a respective descriptor of each successive slot from the original slot through the end slot while the respective descriptor of each successive slot in the ring buffer remains unchanged. Additionally, the hypervisor is configured to execute the request associated with the memory entries and respective valid descriptors. The hypervisor is also configured to walk the ring buffer backwards from the end slot to the original slot while clearing the valid descriptors.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: May 12, 2020
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 10642654
    Abstract: Methods and apparatus for a pipelined architecture for storage lifecycles are disclosed. A method includes identifying, during a transition candidate discovery iteration, storage objects of a multi-tenant service for which respective lifecycle transitions are to be scheduled, including a particular storage object identified as being a candidate for a particular lifecycle transition. The method includes generating transition job objects, each job comprising respective indications of one or more of the storage objects identified during the discovery iteration. The method includes assigning, during a transition execution iteration, resources to initiate storage operations for the particular lifecycle transition, and initiating, using the assigned resources, storage operations for the particular lifecycle transition.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: May 5, 2020
    Assignee: Amazon Technologies, inc.
    Inventors: Jeffrey Michael Barber, Derek Ernest Denny-Brown, II, Carl Yates Perry, Christopher Henning Elving, Praveen Kumar Gattu
  • Patent number: 10635547
    Abstract: Systems for multi-cluster virtualized computing system management. A method for performing virtual entity replication between source computing clusters and target computing clusters commences upon establishing a virtual entity naming convention that is observed by both the source computing clusters and the target computing clusters. A snapshot from a source cluster is associated with a global snapshot ID before being transmitted to a target computing cluster. At some point in time, the source cluster will initiate acts to replicate a virtual entity to a particular data state that is associated with a particular named snapshot. A second replication protocol then commences. The second replication protocol includes exchanges that serve to determine whether or not the target computing cluster has a copy of a particular named snapshot as named by the global snapshot ID, and if so, to then initiate virtual entity replication at the target computing cluster using the named snapshot.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: April 28, 2020
    Assignee: Nutanix, Inc.
    Inventors: Praveen Kumar Padia, Bharat Kumar Beedu, Kiran Tatiparthi, Krishnaveni Budati, Wangzi He
  • Patent number: 10628871
    Abstract: This disclosure relates generally to product promotions, and more particularly to method and system for providing customized product recommendations to consumers. In one embodiment, the method may include determining a location of a consumer and a target product segment of interest to the consumer, determining a plurality of field-installed products in the target product segment and in a geographic area of the location, gathering near real-time operational data from each of the plurality of field-installed products along with a plurality of associated parameters for the geographic region using application scripts pre-installed in each of the plurality of field-installed products, and dynamically analyzing the near real-time operational data and the plurality of associated parameters to determine and recommend a set of products in the target product segment.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 21, 2020
    Assignee: Wipro Limited
    Inventor: Kothamangala Anandaiah Shetty Nagaraja
  • Patent number: 10628051
    Abstract: A data storage device includes a data storage medium and a controller. The controller performs a boot-up sequence that includes operations that transition the data storage device from a lower operational state to a higher operational state in which the data storage device is ready to service host commands. The controller also carries out metadata updating operations independently of the boot-up sequence operations. Carrying out the metadata updating operations independently of the boot up sequence operations prevents the metadata updating operations from substantially contributing to a boot-up time.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: April 21, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Jian Qiang, Tan Choon Kiat, Shen Jin Quan, Chng Yong Peng
  • Patent number: 10613973
    Abstract: In a solid state drive, a journal may be associated with a cluster block, such that the journal stores updates to an indirection mapping data structure for that cluster block. The journals may be stored on the cluster block. During garbage collection these spatially coupled journals can be retrieved and used to determine the data written to each media location within the cluster block. Logical and physical address information can be determined from the journal content, and used to compare against the current mapping in the indirection mapping data structure, to determine the validity of each media location. Since the journals are physical media aware, this comparison can occur without the consultation of a bad block tracking structure. When a physical media address is deemed to hold valid data it will be relocated as part of garbage collection processing.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: April 7, 2020
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Leonid Baryudin, Phillip Peterson, Daniel Sladic
  • Patent number: 10606828
    Abstract: A method of and system for correlating data from among a disparate group of data sources and providing the correlated data to data consumers via API's and direct transmission of the data are disclosed. Once the validity of the data is verified, the data is translated from a format specific to the data source into a format that is usable by various other data repositories. Thereafter, the data may be provided to data consumers.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: March 31, 2020
    Assignee: JPMORGAN CHASE BANK, N.A.
    Inventors: Ashish M. Apte, Atul Suresh Dongre, Puneet Agarwal, Sreenu Daram
  • Patent number: 10606800
    Abstract: Some embodiments provide a system that provides a filesystem in a computer system. During operation, the system obtains a policy for the filesystem and separates the filesystem into a set of layers based on the policy. Next, the system processes input/output (I/O) operations to the filesystem by directing each of the I/O operations to one of the layers based on the policy. Finally, the system periodically maintains the layers using a master image of the filesystem.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: March 31, 2020
    Assignee: OPEN INVENTION NETWORK LLC
    Inventors: Thomas Joseph Purtell, II, John Whaley
  • Patent number: 10592340
    Abstract: A method for execution by a dispersed storage and task (DST) processing unit includes queuing authorization requests, corresponding to received operation requests, in response to determining that first system utilization data indicates a first utilization level that compares unfavorably to a normal utilization threshold. A first batched authorization request that includes the queued authorization requests is generated for transmission to an Identity and Access Management (IAM) system in response to determining that the first request queue compares unfavorably to a first queue limit condition. A second queue limit condition that is different from the first queue limit condition is determined based on second system utilization data. A second batched authorization request that includes a second plurality of authorization requests of a second request queue is generated in response to determining that the second request queue compares unfavorably to the second queue limit condition.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Amit H. Lamba, Brian F. Ober
  • Patent number: 10564880
    Abstract: A data deduplication method and apparatus are provided. The method includes receiving an overwrite request sent by an external device, where the overwrite request carries a data block and a first address into which the data block is to be stored; determining whether an overwrite quantity of the first address exceeds a first threshold within a time period [t1, t2], where both t1 and t2 are time points, and t2 is later than t1; and when the overwrite quantity of the first address exceeds the first threshold within the time period [t1, t2], skipping performing a deduplication operation on the data block; or when the overwrite quantity of the first address does not exceed the first threshold within the time period [t1, t2], performing a deduplication operation on the data block. Therefore, a large quantity of computing resources of a storage server are saved, and impact brought by a deduplication operation on storage server performance is also decreased.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: February 18, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yuguo Li, Jun You, Zongquan Zhang
  • Patent number: 10516732
    Abstract: A data storage system allowing for ingest of data when certain storage is unavailable is described herein. The storage system includes zones that are independent and autonomous from each other. The zones include nodes that are independent and autonomous. The nodes include storage devices. When data is to be stored in the data storage system according to a specified storage policy and the specified storage policy cannot be achieved, the data is stored according to a fallback storage policy. This allows a client to be able to continue executing without having to wait for a storage anomaly to be corrected or pass. After the data is stored according to a fallback storage policy, the data is at a later time stored according to the specified storage policy.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: December 24, 2019
    Assignee: DataDirect Networks, Inc.
    Inventors: Dan Olster, Adam Fried-Gintis, Donald J. Molaro
  • Patent number: 10503419
    Abstract: Embodiments provide a method and system for enabling access to a storage device. Specifically, a node may request admittance to a cluster that has read and write access to a storage device. The node seeking access to the storage device must be first be approved by other nodes in the cluster. As part of the request, the node seeking access to the storage device sends a registration key to a storage device. Upon expiration of a registration timer, the node seeking access to the storage device receives a registration table from the storage device and determines whether its registration key is stored in the registration table. If the registration key is stored in the registration table the node has been accepted in the cluster and as a result, has been granted read and write access to the storage device.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: December 10, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Vyacheslav Kuznetsov, Vinod R. Shankar, Andrea D'Amato, David Allen Dion
  • Patent number: 10459709
    Abstract: Functionality is disclosed for automated deployment of applications. A network-based deployment service provides functionality for deploying software components to physical or virtual hosts in a service provider network and/or to hosts in other types of networks external to the service provider network. A user of the deployment service creates an application revision that includes deployable content and an application specification defining how the application is to be deployed and one or more lifecycle events. The application revision is then uploaded to a storage service, source code repository, or other location. A deployment configuration is also created that defines the location of the application revision, a deployment group, and a schedule for the deployment. A deployment agent executing on hosts in the deployment group obtains the application revision from the specified location, deploys the deployable content according to the schedule, and performs the lifecycle events.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: October 29, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Andrew Thomas Troutman, Suryanarayanan Balasubramanian, Joshua William McFarlane
  • Patent number: 10437504
    Abstract: An apparatus in one embodiment comprises a storage system having at least first and second storage tiers each comprising a plurality of storage devices. The storage system implements a plurality of data mover modules for controlling movement of data objects between the first and second storage tiers. A given one of the data objects is transferred between the first and second storage tiers utilizing a distributed multi-part data movement protocol in which different portions of the given data object are transferred between the first and second storage tiers by different ones of the data mover modules. For example, each of the different portions may be transferred between the first and second storage tiers by its corresponding data mover module as a plurality of distinct non-overlapping parts. In such an arrangement, each of the plurality of distinct non-overlapping parts of each of the different portions may have a corresponding unique tag identifier.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: October 8, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Haiyun Bao, Sorin Faibish, Caiping Zheng, Sen Zhang
  • Patent number: 10416925
    Abstract: A distributed computation system comprising computation units and memory shared between computation units, comprises a hardware module for detecting conflicts of access of computation units to shared memory; each hardware module for detecting conflicts configured to: store a probabilistic data structure, indicative of the addresses of shared memory involved in the current transactions; receive at least one message indicative of request for access, by one computation unit to an address of shared memory; determine, from a probabilistic data structure, whether the address is already involved in a current transaction, and transmit a message indicating presence or absence of access conflicts; receive a message indicative or confirmative of reservation or releasing of an address of shared memory, and update the probabilistic data structure for the reserved addresses and the released addresses to be considered, as being/not being involved in a current transaction. A method for using the system is provided.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: September 17, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Julien Peeters, Nicolas Ventroux, Tanguy Sassolas, Marc Shapiro