Status Storage Patents (Class 711/156)
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Patent number: 11669454Abstract: A processor includes one or more cores having cache, a cache home agent (CHA), a near memory controller, to near memory, and a far memory controller, which is to: receive a first memory read operation from the CHA directed at a memory address; detect a miss for the first memory address at the near memory; issue a second memory read operation to the far memory controller to retrieve a cache line, having first data, from the memory address of far memory; receive the cache line from the far memory controller in response to the second memory read operation; and send the cache line to the CHA with a forced change to a directory state of the cache line at the CHA, the forced change to cause the CHA to snoop remote sockets to maintain data coherence for the cache line in an absence of directory state in the far memory.Type: GrantFiled: May 7, 2019Date of Patent: June 6, 2023Assignee: Intel CorporationInventors: Vedaraman Geetha, Jeffrey Baxter, Sai Prashanth Muralidhara, Sharada Venkateswaran, Daniel Liu, Nishant Singh, Bahaa Fahim, Samuel D. Strom
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Patent number: 11657857Abstract: Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.Type: GrantFiled: March 16, 2021Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventors: Theodore T. Pekny, Victor Y. Tsai
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Patent number: 11650883Abstract: A method includes, determining, for a batch rebuild process regarding a first batch threshold number of encoded data slices of a set of encoded data slices that need rebuilding, a target storage unit of target storage units of a set of storage units of the storage network is unavailable, where a data segment of data is dispersed storage error encoded into the set of encoded data slices, the set of encoded data slices is stored in the set of storage units, and the first batch threshold number of encoded data slices is to be stored in the target storage units. When the target storage unit becomes available before a second batch rebuild threshold number of encoded data slices of the set of encoded data slices is met, the method includes executing the batch rebuild process for the first batch threshold number of encoded data slices.Type: GrantFiled: April 27, 2022Date of Patent: May 16, 2023Assignee: Pure Storage, Inc.Inventors: Niall J. McShane, Andrew D. Baptist, Ravi V. Khadiwala
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Patent number: 11615826Abstract: A memory system includes a memory device and a processing device operatively coupled with the memory device. The processing device perform operations comprising: responsive to receiving a memory access command, determining that the memory access command is a dual-address command comprising a source address and a destination address; generating a first content addressable memory (CAM) entry associated with a read command of the dual-address command, wherein the first CAM entry references the source address; generating a second CAM entry associated with a write command of the dual-address command, wherein the second CAM entry references the destination address; inserting the first CAM entry and the second CAM entry into a CAM; and issuing, to the memory device, the read command associated with the first CAM entry.Type: GrantFiled: September 7, 2021Date of Patent: March 28, 2023Assignee: Micron Technology, Inc.Inventors: Fangfang Zhu, Chih-Kuo Kao, Yueh-Hung Chen, Jiangli Zhu
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Patent number: 11586508Abstract: A method for backing up data, that includes making a detection, by a volatile storage firmware, that data communication to a volatile storage component is degraded, initiating a direct memory access (DMA) engine to copy the data from the volatile storage component to a non-volatile storage device, and in response to initiating copying of the data, initiating a shutdown of the volatile storage component.Type: GrantFiled: September 29, 2020Date of Patent: February 21, 2023Assignee: EMC IP Holding Company LLCInventors: Yong Zou, Rajeev Tiwari
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Patent number: 11537290Abstract: There is provided a method for managing a solid state storage system with hybrid storage technologies. The method includes monitoring one or more storage request streams to identify operating mode characteristics therein from among a set of possible operating mode characteristics. The set of possible operating mode characteristics correspond to a set of available operating modes of the hybrid storage technologies. The method further includes identifying a current operating mode from among the set of available operating modes responsive to the identified operating mode characteristics. The method also includes predicting a likely future operating mode responsive to variations in workload requirements to generate at least one future operating mode prediction. The method additionally includes controlling at least one of data placement, wear leveling, and garbage collection, responsive to the at least one future operating mode prediction.Type: GrantFiled: March 20, 2014Date of Patent: December 27, 2022Assignee: International Business Machines CorporationInventors: Chen-Yong Cher, Michele M. Franceschini, Ashish Jagmohan
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Patent number: 11513712Abstract: Techniques for storage management involve: determining expected usage time of a first storage disk in a set of storage disks, at least a part of the set of storage disks being configured to form at least one redundant array of independent disks (RAID); moving data in a first storage block, associated with a first RAID in the at least one RAID, in the first storage disk to a second storage block in a second storage disk in the set of storage disks based on a determination that the expected usage time is less than a predetermined threshold value; and replacing the first storage block with the second storage block, so that the second storage block is associated with the first RAID. Based on this manner, the stability of a storage system can be improved.Type: GrantFiled: August 12, 2020Date of Patent: November 29, 2022Assignee: EMC IP Holding Company LLCInventors: Jianbin Kang, Geng Han, Jibing Dong, Hongpo Gao
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Patent number: 11487619Abstract: A first node group including at least three nodes is predefined in a distributed storage system. Each node of the first node group is configured to send data blocks stored in storage devices managed by the node to other nodes belonging to the first node group. A first node is configured to receive data blocks from two or more other nodes in the first node group. The first node is configured to create a redundant code using a combination of data blocks received from the two or more other nodes and store the created redundant code to a storage device different from storage devices holding the data blocks used to create the redundant code. Combinations of data blocks used to create at least two redundant codes in redundant codes created by the first node are different in combination of logical addresses of constituent data blocks.Type: GrantFiled: May 21, 2021Date of Patent: November 1, 2022Assignee: Hitachi, Ltd.Inventors: Hiroaki Akutsu, Shunji Kawamura, Kota Yasunaga, Takahiro Yamamoto, Atsushi Kawamura
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Patent number: 11474874Abstract: Systems and methods for automatically scaling a big data system. Methods include determining, at a first time, a first number of nodes for a cluster to process a request; assigning an amount of nodes equal to the first number of nodes to the cluster; determining a rate of progress of the request; determining, at a second time based on the rate of progress a second number of nodes; and modifying the amount of nodes to equal the second number of nodes. Systems include a cluster manager, to add and/or remove any nodes; the big data system, to process requests that utilize the cluster and nodes, and an automatic scaling cluster manager including a big data interface for communicating with the big data system; a cluster manager interface for communicating with the cluster manager; and a cluster state machine.Type: GrantFiled: August 14, 2014Date of Patent: October 18, 2022Assignee: QUBOLE, INC.Inventors: Joydeep Sen Sarma, Mayank Ahuja, Sivaramakrishnan Narayanan, Shrikanth Shankar
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Patent number: 11467875Abstract: Provided is a method for provisioning an application container volume (storage) in a cloud platform. The method takes provision requests and desired allocation capacity from users and provisions storage for an application container differently based on a determination of whether a cloud platform system generates a volume statically or dynamically, and based on a determination of whether the available space of storage space is sufficient or not to cover the desired allocation capacity. The method also notifies users about insufficient storage space to cover desired allocation capacity, and allows users to adjust desired allocation capacity to allow the provisioning proceed.Type: GrantFiled: July 15, 2019Date of Patent: October 11, 2022Assignees: NAMU TECH CO., LTD., ACORNSOFT CO., LTD.Inventor: Jae Hwan Kwon
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Patent number: 11461773Abstract: Systems and methods for blockchain-based node management. In an aspect, a system receives, by an existing node of a blockchain, a target transaction, wherein the target transaction comprises a certificate of a new node and a unique identifier of the new node; verifies the target transaction by the target transaction passing consensus verification of the blockchain; and after the target transaction passes consensus verification of the blockchain to verify the blockchain, records, in a node identity table that is used to record a certificate of a blockchain node and a unique identifier that is of the blockchain node and that corresponds to the certificate, the unique identifier and the certificate of the new node.Type: GrantFiled: January 29, 2021Date of Patent: October 4, 2022Assignee: Advanced New Technologies Co., Ltd.Inventor: Dong Pan
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Patent number: 11461265Abstract: A high speed intelligent network recorder for recording a plurality of flows of network data packets into and out of a computer network over a relevant data time window is disclosed. The high speed intelligent network recorder includes a printed circuit board; a high speed network switching device mounted to the printed circuit board; and an X column by Y row array of a plurality of intelligent hard drives with micro-computers mounted to the printed circuit board and coupled in parallel with the high speed network switching device.Type: GrantFiled: May 2, 2019Date of Patent: October 4, 2022Assignee: Endace Technology LimitedInventors: Anthony James Coddington, Stephen Frank Donnelly, David William Earl, Maxwell John Allen, Stuart Wilson, William Brier
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Patent number: 11442900Abstract: A method, system and computer program product for sharing resources among remote repositories. In a shared file system, a resource identifier and metadata are created for a resource, where the resource identifier is stored in a lock file in a shared volume accessible by the remote repositories. The lock file is then released in response to distributing the associated resource to the remote repositories. Alternatively, in a peer-to-peer system, a request is received to create, read, update or delete a resource stored in a content repository. A resource name, a resource version and/or a resource fingerprint are received in connection with the request to create, read, update or delete the resource in the content repository. A determination is then made as to whether the received resource name, resource version and/or resource fingerprint matches the respective resource name, resource version and/or resource fingerprint stored in a node graph for the resource.Type: GrantFiled: February 28, 2019Date of Patent: September 13, 2022Assignee: International Business Machines CorporationInventors: Barry P. Gower, Larry R. Hamann, Andrew S. Myers, Seth R. Peterson, Davanum M. Srinivas, Donald R. Woods
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Patent number: 11435919Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to perform operations comprising opening a block family associated with the memory device; initialize a timer associated with the block family; assigning a plurality of cursors to the block family; responsive to programming a first block associated with a first cursor of the memory device, associating the first block with the block family; responsive to programming a second block associated with a second cursor of the memory device, associating the second block with the block family; and responsive to detecting expiration of the timer, closing the block family.Type: GrantFiled: November 5, 2020Date of Patent: September 6, 2022Assignee: Micron Technology, Inc.Inventors: Michael Sheperek, Bruce A. Liikanen, Peter Feeley, Larry J. Koudele, Shane Nowell, Steven Michael Kientz
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Patent number: 11436105Abstract: A data processing method includes: configuring a predetermined memory space to record information regarding data to be backed up of a memory device, where the information is used to indicate data associated to which logical memory space is the data to be backed up; and updating the information according to commands received from a host device.Type: GrantFiled: January 7, 2021Date of Patent: September 6, 2022Assignee: Realtek Semiconductor Corp.Inventors: Yen-Chung Chen, Yi-Ting Wei, Tzu-Yu Chao, Ming-Yuh Yeh
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Patent number: 11409451Abstract: Systems, methods, and storage media for using the otherwise-unutilized storage space on a storage device without having a substantial effect on the normal operation of the storage device by one or more users accessing the storage device through one or more primary file organization architecture controllers of the storage device are disclosed.Type: GrantFiled: October 18, 2019Date of Patent: August 9, 2022Assignee: Veriblock, Inc.Inventors: Justin Fisher, Maxwell Sanchez
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Patent number: 11409707Abstract: A method, system and computer program product for sharing resources among remote repositories. In a shared file system, a resource identifier and metadata are created for a resource, where the resource identifier is stored in a lock file in a shared volume accessible by the remote repositories. The lock file is then released in response to distributing the associated resource to the remote repositories. Alternatively, in a peer-to-peer system, a request is received to create, read, update or delete a resource stored in a content repository. A resource name, a resource version and/or a resource fingerprint are received in connection with the request to create, read, update or delete the resource in the content repository. A determination is then made as to whether the received resource name, resource version and/or resource fingerprint matches the respective resource name, resource version and/or resource fingerprint stored in a node graph for the resource.Type: GrantFiled: February 28, 2019Date of Patent: August 9, 2022Assignee: International Business Machines CorporationInventors: Barry P. Gower, Larry R. Hamann, Andrew S. Myers, Seth R. Peterson, Davanum M. Srinivas, Donald R. Woods
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Patent number: 11360708Abstract: Technologies are provided for supporting storage device write barriers. A storage device can be configured to associate a data access command with a write barrier. The write barrier can be used to indicate that one or more data access commands should be processed before one or more other data access commands are processed. For example, a host computer can transmit one or more data access commands to a storage device. The storage device can determine that the one or more data access commands are associated with a write barrier. The host computer can continue to transmit additional data access commands to the storage device. However, the storage device will not process the additional data access commands until after the one or more data access commands associated with the write barrier have been processed.Type: GrantFiled: June 30, 2020Date of Patent: June 14, 2022Assignee: Amazon Technologies, Inc.Inventors: Munif M. Farhan, Keun Soo Jo, James Alexander Bornholt, Andrew Kent Warfield, Andrew C. Schleit, Seth W. Markle
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Patent number: 11347434Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a read command specifying an identifier of a logical block and a page number; translate the identifier of the logical block into a physical address of a physical block stored on the memory device, wherein the physical address comprises an identifier of a memory device die; identify, based on block family metadata associated with the memory device, a block family associated with the physical block and the page number; determine a threshold voltage offset associated with the block family and the memory device die; compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the memory device die; and read, using the modified threshold voltage, data from a physical page identified by the page number within the physical block.Type: GrantFiled: April 21, 2020Date of Patent: May 31, 2022Assignee: Micron Technology, Inc.Inventor: Mark Ish
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Patent number: 11301149Abstract: Embodiments of the present disclosure relate to an electronic apparatus that includes a metadata generator, to generate an extents table (ET) that lists one or more extents pages (EPs), where an EP is a fixed size, and where the one or more EPs store one or more extents. An extent includes an allocation indication for a cluster in a memory device, where a number of the extents corresponds to a number of clusters of the memory device, where a subset number of the extents is stored in one of the one or more EPs, and where the subset number is based on the fixed size of the EP. The electronic apparatus further includes a metadata updater, to modify the allocation indication in the extent stored in the one of the one or more EPs, based on a corresponding change in an allocation of the cluster in the memory device.Type: GrantFiled: March 7, 2019Date of Patent: April 12, 2022Assignee: Intel CorporationInventors: James Harris, Benjamin Walker, Tomasz Zawadzki
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Patent number: 11232073Abstract: Example methods and apparatuses for file compaction in a key-value store system relating to the field of data processing technologies are described. One example method for file compaction in a key-value store (KV-Store) system includes compacting, according to a to-be-deleted log (Delete Log) that corresponds to a to-be-compacted sorted string table (SSTable), the to-be-compacted SSTable to generate a new SSTable. A key corresponding to a non-latest value in the KV-Store system and stored in the to-be-compacted SSTable is recorded in the Delete Log, and the new SSTable does not include a key-value pair that corresponds to the key in Delete Log. The to-be-compacted SSTable is then deleted.Type: GrantFiled: January 24, 2018Date of Patent: January 25, 2022Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Shimin Chen, Liangchang Zhu, Jun Zhang
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Patent number: 11231991Abstract: An SOC includes a security processor. The security processor includes an encryption/ECC encoding processor configured to perform an encryption operation on data using Metadata and to generate ECC data by performing ECC encoding processing on encrypted data and the Metadata, a decryption/ECC decoding processor configured to extract the encrypted data and the Metadata by performing ECC decoding processing using the ECC data and to recover the data by performing a decryption operation on the encrypted data using the Metadata, and an address controller configured to receive a first address related to storage of the data, to generate a second address based on the first address, and to perform an address generating operation identifying a same region in memory for storing the Metadata and the ECC data based on the second address.Type: GrantFiled: April 18, 2019Date of Patent: January 25, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: In-goo Heo, Yoon-bum Seo, Young-jin Chung, Jin-su Hyun
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Patent number: 11228574Abstract: The disclosure describes systems, methods and devices relating to a sign-on and management hub or service for users of multiple internal, external or Software-as-a-Service (SaaS) software applications (Apps), with options for centralized management and sharing of accounts without needing to provide login credentials to individual users.Type: GrantFiled: July 30, 2018Date of Patent: January 18, 2022Assignee: Google LLCInventors: Erik Gustavson, Scott Kriz, Aaron Eisenberger, Garrett Brown, Jason Carulli, Andrew Arrow, Prashant Nadarajan, Fong Woh Fai, Chung Weng Wai, Saw Kee Wooi
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Patent number: 11227661Abstract: A controller controls an operation of a semiconductor memory device. The controller includes an erased page search controller, a command generator, and a data receiver. The erased page search controller determines a search mode of the semiconductor memory device, selects a page to search for, among a plurality of pages, based on the search mode, and generates a search control signal corresponding to a selected page. The command generator generates a search read command for the selected page based on the search control signal. The data receiver receives, from the semiconductor memory device, search read data corresponding to the search read command. The search read command is a command for controlling the semiconductor memory device to perform a read operation by applying a read voltage to multiple word lines including a word line corresponding to the selected page.Type: GrantFiled: July 10, 2019Date of Patent: January 18, 2022Assignee: SK hynix Inc.Inventor: Jiman Hong
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Patent number: 11216211Abstract: Technology is described for controlling different types of physical devices in a device farm hosted in a service provider environment. A removable storage slot adapter may be physically inserted into a removable storage slot of a physical device. The removable storage slot adapter may present an emulated removable storage device using a removable storage configuration obtained over a network from a management service hosted by the service provider environment. The removable storage slot adapter may interpret commands from the device to access data blocks of the emulated removable storage device. The removable storage slot adapter may access a storage service hosted by the service provider environment to fulfill the commands and data access operations requested from the device.Type: GrantFiled: September 25, 2018Date of Patent: January 4, 2022Assignee: Amazon Technologies, Inc.Inventors: Mauricio Da Silva Miranda, Calvin Yue-Ren Kuo, Jonathan I. Turow
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Patent number: 11182294Abstract: A data processing apparatus 2 includes a cache memory 8 for storing data items to be accessed. Coherency control circuitry 20 controls coherency between data items stored within the cache memory and one or more other copies of the data items stored outside the cache memory. A data access buffer 6 buffers a plurality of data access to respective data items stored within the cache memory. Access control circuitry 20 is responsive to coherency statuses managed by the coherency control circuitry for the plurality of data items to be subject to data access operations to be performed together atomically as an atomic set of data accesses to ensure that the coherency statuses for all of these data items permit all of the atomic set of data accesses to be performed within the cache memory before the set of atomic data accesses are commenced.Type: GrantFiled: August 18, 2017Date of Patent: November 23, 2021Assignee: ARM LimitedInventors: Jason Parker, Graeme Peter Barnes
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Patent number: 11182363Abstract: A method for validating data in a copy repository is disclosed. In one embodiment, such a method includes establishing a template that designates valid fields within a data set, as well as valid values and types of data within the fields. The method further establishes a timeframe over which to validate versions of the data set residing in a copy repository. Starting at a first end of the timeframe and proceeding to a second end, the method validates each version of the data set residing in the copy repository. To accomplish this, the method configures a computing system to a state that existed when the version was created in the copy repository. The method then opens the version on the computing system and validates the version against the template. A corresponding system and computer program product are also disclosed.Type: GrantFiled: June 29, 2018Date of Patent: November 23, 2021Assignee: International Business Machines CorporationInventors: David C. Reed, Gregory E. McBride
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Patent number: 11176032Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving a first write command from a host, the controller determines a first physical address indicative of a physical storage location of the nonvolatile memory to which first write data associated with the first write command is to be written, and updates an address translation table such that the first physical address is associated with a logical address of the first write data. The controller starts updating the address translation table before the transfer of the first write data is finished or before the write of the first write data to the nonvolatile memory is finished.Type: GrantFiled: March 11, 2020Date of Patent: November 16, 2021Assignee: Kioxia CorporationInventor: Shinichi Kanno
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Patent number: 11151031Abstract: Methods and systems are disclosed for optimizing record placement in defragmenting a graph database. Issues with fragmented data within a graph database are addressed on the record level by placing data that is frequently accessed together contiguously within memory. For example, a dynamic rule set may be developed based on dynamically analyzing access patterns of the graph database, policies, system characteristics and/or other heuristics. Based on statistics regarding normal query patterns, the systems and methods may identify an optimal position for certain types of edges that are often traversed with respect to particular types of nodes.Type: GrantFiled: June 29, 2017Date of Patent: October 19, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Åge Kvalnes, Jan-Ove Karlberg, Tor Kreutzer, Amund Kronen Johansen, Steffen Viken Valvåg
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Patent number: 11119874Abstract: A memory fault detection method includes: receiving a first interrupt signal sent when a count value of a first leaky bucket counter of a server reaches a first threshold; disabling an interrupt switch of the first leaky bucket counter; enabling the interrupt switch of the first leaky bucket counter after the interrupt switch of the first leaky bucket counter has been disabled for a preset time and the count value of the first leaky bucket counter is reset to zero; receiving a second interrupt signal sent when a count value of a second leaky bucket counter reaches a second threshold; if the second leaky bucket counter and the first leaky bucket counter are a same leaky bucket counter, and the second rank and a first rank are a same rank, determining that a hardware fault occurs in the first rank.Type: GrantFiled: January 21, 2020Date of Patent: September 14, 2021Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Gang Song, Chengguo Ding, Fei Zhang
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Patent number: 11099949Abstract: A method and apparatus for programming a one-time programmable (OTP) memory device is disclosed that allows for resuming and recovering from an interrupted programming cycle (e.g. due to loss of power or user interaction). Upon re-initiation of a programming cycle with the same memory range, a programming controller may detect the memory address where interruption occurred, and resume programming from that address. If the programming interruption resulted in an incorrectly programmed word at the interrupted address, a word repair register may be mapped to the corrupted address to enable correction of that word. The remainder of the memory range may then be programmed normally.Type: GrantFiled: August 1, 2019Date of Patent: August 24, 2021Assignee: Cirrus Logic, Inc.Inventors: Michael A Kost, Bradley A Lambert, John P Tourish, Girish Subramaniam
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Patent number: 11086517Abstract: Memory management that includes allocating physical memory having an append-only permission associated therewith to requesting user space applications is described. If a page frame is append-only, then data written to the page frame cannot be overwritten. Rather, any new data written to an append-only page frame must be written beginning at the next available write location within the page frame. An MMU determines whether a write request is requesting an append-only page frame, in which case, the MMU reserves the append-only page frame for the write request and consults a corresponding entry in a page table append to determine whether an offset associated with the write request is larger than a stored value in the entry that indicates the next available write location in the page frame. If so, the write request is executed and the data is written to the page frame beginning at the next available write location.Type: GrantFiled: October 30, 2018Date of Patent: August 10, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Breno H. Leitao, Juscelino Candido De Lima Junior, Carlos Eduardo Seo
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Patent number: 11061607Abstract: There are provided an electronic system and an operating method thereof. The electronic system includes: a host for queuing an external command to wait or to be output, based on a status of dies included in a storage device; a central processing unit for generating a command for controlling the storage device in response to a request received from the host or the external command; and a controller memory buffer for storing status information indicating whether the dies are in a status in which access is possible or a status in which access is impossible, wherein the central processing unit receives status information of the dies from the storage device, and stores status information matched to each of the dies in the controller memory buffer.Type: GrantFiled: August 28, 2018Date of Patent: July 13, 2021Assignee: SK hynix Inc.Inventors: Duck Hoi Koo, Yong Jin
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Patent number: 11062777Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.Type: GrantFiled: May 11, 2020Date of Patent: July 13, 2021Assignee: Toshiba Memory CorporationInventors: Jun Nakai, Noboru Shibata
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Patent number: 11048417Abstract: Techniques perform storage management. Such techniques involve: detecting a change of a size of storage space for a file system, the file system having one or more associated bitmaps, each active bit in the one or more bitmaps indicating data status in storage space not exceeding an upper size limit of the file system; in response to detecting the change, determining, based on the upper size limit, a first number of bits required for indicating the changed storage space; and in response to determining that the first number exceeds a second number of current active bits in the one or more bitmaps, allocating at least one additional active bit for the file system. Accordingly, the number of bits for indicating the file system can be dynamically adjusted based on the changes of the file system.Type: GrantFiled: September 12, 2019Date of Patent: June 29, 2021Assignee: EMC IP Holding Company LLCInventors: Yue Yang, Xin Zhong, Yangfeng Chen, Qinghua Ling, Yan Shao
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Patent number: 11042435Abstract: A circuit apparatus 100 includes: an interface circuit 120 that receives setting data; and a control circuit 110 that controls the operations of the circuit apparatus 100 based on the setting data and also controls access to a nonvolatile memory 10. The control circuit 110 generates error detection data based on the setting data received by the interface circuit 120, and writes the setting data and the error detection data to the nonvolatile memory 10.Type: GrantFiled: May 28, 2019Date of Patent: June 22, 2021Assignee: SEIKO EPSON CORPORATIONInventor: Atsushi Ishikawa
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Patent number: 11017838Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.Type: GrantFiled: August 12, 2020Date of Patent: May 25, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hee-Woong Kang, Dong-Hun Kwak, Jun-Ho Seo, Hee-Won Lee
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Patent number: 11010074Abstract: Disclosed is a system and method for providing host adjustable performance parameters for SSDs. The method includes accessing a latency profile based on a determined device age of a solid state drive (SSD). The method also includes providing for display a user interface comprising a plurality of interface elements to adjust a respective plurality of performance specifications of the SSD, wherein the user interface is configured based on the latency profile. The method also includes receiving, via the user interface, an adjustment to the plurality of performance specifications. The method also includes sending an instruction to the SSD to configure the SSD with a parameter set based on the adjusted plurality of performance specifications.Type: GrantFiled: March 23, 2020Date of Patent: May 18, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Navneeth Kankani, Linh Tien Truong
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Patent number: 11003642Abstract: Columnar storage provides many performance and space saving benefits for analytic workloads, but previous mechanisms for handling single row update transactions in column stores suffer from poor performance. A columnar data layout facilitates both low-latency random access capabilities together with high-throughput analytical access capabilities, simplifying Hadoop architectures for use cases involving real-time data. In disclosed embodiments, mutations within a single row are executed atomically across columns and do not necessarily include the entirety of a row. This allows for faster updates without the overhead of reading or rewriting larger columns.Type: GrantFiled: January 26, 2018Date of Patent: May 11, 2021Assignee: Cloudera, Inc.Inventor: Todd Lipcon
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Patent number: 10983820Abstract: A computer-implemented method includes receiving a request for storage for a container and determining whether a suitable thin provisioned volume currently exists based on criteria in the request. In response to determining that a suitable thin provisioned volume currently exists, the method includes selecting an unused portion of the thin provisioned volume and creating a container volume in the selected unused portion of the thin provisioned volume. The method also includes permitting input/output (I/O) to the container volume and releasing the selected unused portion of the thin provisioned volume in response to determining the container volume is no longer needed.Type: GrantFiled: March 6, 2019Date of Patent: April 20, 2021Assignee: International Business Machines CorporationInventors: Sandeep Bangur, Pankaj Deshpande, Aakanksha Mathur, Pradip Waykos
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Patent number: 10976928Abstract: Technologies for identifying data stored on a solid state drive (“SSD”) device that correspond to data associated with a delete event, and marking the deleted data stored on the SSD as invalid such that the SSD can avoid unnecessary operations on the invalid data. Included are interfaces operable to communicate invalid data information and providing a remove-on-delete command that provides invalid data information sufficient to identify the SSD data to be marked as invalid.Type: GrantFiled: November 12, 2018Date of Patent: April 13, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Frank J. Shu, Nathan S. Obr
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Patent number: 10970227Abstract: A data processing apparatus is provided, comprising a processor configured to execute a process, in particular with at least one thread, a memory management unit component configured to access a page table, and a page fault handler configured to handle page faults by triggering a page fault in response to detecting one of a plurality of predefined bit patterns in the page table, and by assigning a different page fault operation for the process, in particular with the at least one thread, to each of the plurality of predefined bit patterns.Type: GrantFiled: April 9, 2018Date of Patent: April 6, 2021Assignee: Huawei Technologies Co., Ltd.Inventor: Jani Kokkonen
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Patent number: 10949115Abstract: A Data Storage Device (DSD) includes a flash memory for storing data. Portions of the flash memory are grouped into logical groups based on at least one of a number of Program/Erase (P/E) cycles and a physical level location of the portions of the flash memory. A command performance latency is monitored for each logical group, and at least one polling time for each respective logical is set based on the monitored command performance latency for the logical group. The at least one polling time indicates a time to wait before checking whether a portion of the flash memory in the logical group has completed a command.Type: GrantFiled: June 24, 2019Date of Patent: March 16, 2021Assignee: Western Digital Technologies, Inc.Inventors: Chao Sun, Xinde Hu, Dejan Vucinic
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Patent number: 10929263Abstract: In one example implementation according to an embodiment described herein, a computer-implemented method includes detecting input/output (I/O) interrupts for executing I/O operations occurring over a period of time. The method further includes calculating an I/O interrupt delay time (IIDT) for each I/O interrupt occurring during the period of time. The method further includes binning the IIDT for each I/O interrupt occurring during the period of time into one of a plurality of bins based on a value of the IIDT, each of the plurality of bins storing a count of IIDT values within a defined range. The method further includes determining a highest IIDT value. The method further includes identifying a performance degradation based at least on one of the count of IIDT values of each of the plurality of bins or the highest IIDT value. The method further includes implementing a corrective action to mitigate the performance degradation.Type: GrantFiled: November 13, 2018Date of Patent: February 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Richard Paveza, Harry M Yudenfriend
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Patent number: 10929382Abstract: In general, embodiments of the invention relate to methods and systems for replicating data, which is stored in a source system, in a target system. More specifically, embodiments of the invention enable parallel transmission and verification of portions of the data. Once the portions of the data have been verified, embodiments of the invention combine the verified portions of the data to obtain the final combined data. The combined data is then verified.Type: GrantFiled: July 31, 2017Date of Patent: February 23, 2021Assignee: EMC IP HOLDING COMPANY LLCInventors: Krithika Subramanian, Srisailendra Yallapragada, Harshadrai Parekh, Bhimsen Bhanjois
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Patent number: 10909029Abstract: Methods, computer program products, and systems for managing memory in a computer system in which memory locations in use at any given time are represented as a set of memory objects in a first object graph. The first object graph includes a system root object associated by references to each of the memory objects. A method includes creating a second root object for the memory to form a second object graph for the memory. The method also includes, in response to the dereferencing of a first object from the first object graph, associating the dereferenced first object with the second object graph so that the second object graph includes at least one dereferenced object.Type: GrantFiled: April 25, 2019Date of Patent: February 2, 2021Assignee: International Business Machines CorporationInventor: Edward J. Slattery
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Memory system and method of controlling memory system for calculating voltage value for reading data
Patent number: 10878898Abstract: A memory system includes a first memory, a second memory, and a first circuit. The first memory includes a memory cell array including memory cell transistors, and a peripheral circuit configured to read data of a plurality of bits stored in a memory cell transistor of the memory cell array based on a comparison between threshold voltages of the memory cell transistor and at least a part of n determination voltages (n?3). The first circuit is configured to calculate an estimated value of each of n?m determination voltages based on values of m determination voltages (2?m?n?1) among the n determination voltages, and calculate a difference between a value of each of the n?m determination voltages and a corresponding estimated value. The second memory is configured to store values of the m determination voltages and the difference for each of the n?m determination voltages.Type: GrantFiled: March 4, 2019Date of Patent: December 29, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Ryo Sekiguchi, Shingo Yanagawa, Yasuhiko Kurosawa, Eriko Akaihata -
Patent number: 10846265Abstract: A method and an apparatus for accessing a file, and a storage system. The method includes: determining L first-file invoking request messages; separately adding, according to physical sector information in the L first-file invoking request messages, the L first-file invoking request messages to M first-file dispatch queues; and processing a first-file invoking request message included in each first-file dispatch queue, to obtain an invoking request message of each first-file dispatch queue, where the invoking request message is used to access a first file. By means of the method and apparatus for accessing a file and the storage system in the embodiments of the present disclosure, a corresponding dispatch queue is allocated to an invoking request message of a micro file, so that combination processing can be performed on invoking request messages of multiple micro files, and a quantity of times of invoking a micro file is reduced.Type: GrantFiled: May 27, 2015Date of Patent: November 24, 2020Assignee: Huawei Technologies Co., Ltd.Inventors: Guojun Shi, Zhigang Li, Fuzhou Xiao
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Patent number: 10824513Abstract: An apparatus in one embodiment comprises at least one processing device having a processor coupled to a memory. The processing device is configured to maintain, for logical storage volumes of a storage system, device sequence numbers for snapshot and extent copy operations. The processing device is also configured to maintain, for at least one track of the logical storage volumes, a track sequence number representing the state of the track with respect to the snapshot and extent copy operations. The processing device is further configured to receive input/output operations directed to the logical storage volumes from host devices coupled to the storage system while at least one snapshot or extent copy operation for the logical storage volumes is in progress, and to utilize the track sequence numbers and the device sequence numbers to determine processing of the received input/output operations while the snapshot or extent copy operations are in progress.Type: GrantFiled: April 30, 2019Date of Patent: November 3, 2020Assignee: EMC IP Holding Company LLCInventors: Sandeep Chandrashekhara, David T. Tsang, Michael Ferrari, Jeffrey Wilson, Mark J. Halstead
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Patent number: 10827081Abstract: Server receives a log from a client apparatus, the client apparatus generating the log after the client apparatus executes a function, the log including a function identifier identifying the function, execution start date-and-time and execution end date-and-time of the function, and a setting value of each of one or more setting items about the function, determines whether or not performance of the function identified by the function identifier included in the received log is lower than a certain criterion on a basis of the execution start date-and-time and the execution end date-and-time included in the received log, and if the server apparatus determines that the performance of the function is low, sends a setting value stored in the storage device to the client apparatus, the setting value being a setting value, with which the performance was high, of each of the one or more setting items about the function-low-in-performance.Type: GrantFiled: September 4, 2019Date of Patent: November 3, 2020Assignee: KYOCERA DOCUMENT SOLUTIONS INC.Inventor: Maya Hiwatari