Abstract: Described are embodiments of mediums, methods, and systems for application-reserved use of cache for direct I/O. A method for using application-reserved cache may include reserving, by one of a plurality of cores of a processor, use of a first portion of one of a plurality of levels of cache for an application executed by the one of the plurality of cores, and transferring, by the one of the plurality of cores, data associated with the application from an input/output (I/O) device of a computing device directly to the first portion of the one of the plurality of levels of the cache. Other embodiments may be described and claimed.

Abstract: Aspects relate to executing a run-time-instrumentation EMIT (RIEMIT) instruction. A processor is configured to capture the run-time-instrumentation information of a stream of instructions. The RIEMIT instruction is fetched and executed. It is determined if the current run-time-instrumentation controls are configured to permit capturing and storing of run-time-instrumentation information in a run-time-instrumentation program buffer. If the controls are configured to store run-time-instrumentation instructions, then a RIEMIT instruction specified value is stored as an emit record of a reporting group in the run-time-instrumentation program buffer.

Abstract: A social networking system notifies its users of different events and actions taking place inside the social networking system. To present notifications that are most likely to be of interest to the user, the social networking system observes the interactions of the user with notifications presented to the user and suggests an option to opt-out of notifications associated with a source based on the observed interactions. The option to opt-out of notifications associated with the source may be presented if the users interactions with the notifications presented are below a threshold. Notifications associated with a social group are presented to the user based on factors describing the group and the relation between the user and other users of the social group, for example, seniority of the user, size of the group, and the rate at which user actions associated with the group are received.

Abstract: A data processing system includes a cache memory 58 and cache control circuitry 56 for applying a cache replacement policy based upon a retention priority value PV stored with each cache line 66 within the cache memory 58. The initial retention priority value set upon inserting a cache line 66 into the cache memory 58 is dependent upon either or both of which of a plurality of sources issued the access memory request that resulted in the insertion or the privilege level of the memory access request resulting in the insertion. The initial retention priority level of cache lines resulting from instruction fetches may be set differently from cache lines resulting from data accesses.

Abstract: The present invention relates to a method, system, and computer program product for determining storage device weight values to use to select one of the storage devices to use as a target storage to which data from a source storage is migrated. A determination is made, for each of the storage devices, of static parameter values for static parameters comprising attributes of the storage device and dynamic parameter values for dynamic parameters providing device health information determined by accessing the storage device to determine operational conditions at the storage device. Storage device weight values are determined as a function of the static parameter values and the dynamic parameter values of the device. The determined storage device weight values are used to select one of the storage devices as the target storage to which data from the source storage is migrated.

Abstract: A mechanism for zeroed logical volume management is disclosed. A method includes assigning, by a computing device, a bit value to each of storage blocks in a data volume of an operating system. The method also includes permitting, by the computing device, data in the storage blocks of the data volume to be read if the bit value is set to 1. The method further includes preventing, by the computing device, the data in the storage blocks of the data volume to be read if the bit value is set to 0.

Abstract: A wireless network device includes operating system layer buffers used by an operating system and driver layer buffers used by a wireless network interface driver in the device. Memory stores a capacity bitmap managed by the wireless network interface driver. The capacity bitmap identifies a current capacity of each of the driver layer buffers and the capacity bitmap may be provided to the operating system.

Abstract: A method, computer program product, and computing system for grouping storage blocks within a file system into a plurality of storage pools including a free-backed storage pool, a free-unbacked storage pool, and an allocated-backed storage pool. The free-backed storage pool identifies unused storage blocks within the file system that are already associated with physical storage space within a backend storage system. The free-unbacked storage pool identifies unused storage blocks within the file system that are not yet associated with physical storage space within the backend storage system. The allocated-backed storage pool identifies used storage blocks within the file system that are already associated with physical storage space within the backend storage system. A request is received for one or more unused storage blocks within the file system.

Abstract: A system and method of performing electronic transactions between a server computer and a client computer. The method implements a communication protocol with encrypted data transmission and mutual authentication between a server and a hardware device via a network, performs a decryption of encrypted server responses, forwards the decrypted server responses from the hardware device to the client computer, displays the decrypted server responses on a client display, receives requests to be sent from the client computer to the server, parses the client requests for predefined transaction information by the hardware device, encrypts and forwards client requests, displays the predefined transaction information upon detection, forwards and encrypts the client request containing the predefined transaction information to the server if a user confirmation is received, and cancels the transaction if no user confirmation is received.

Abstract: According to an embodiment, a memory device includes a nonvolatile first memory, a nonvolatile second memory, a first controller, and a second controller. The first controller is configured to write, to the first memory, data received over a short-range radio communication by using power generated in the short-range radio communication. The second controller is configured to execute, at a startup of the memory device, a transfer process of reading a file written in the first memory and storing the read file to the second memory.

Abstract: A method of operating a semiconductor storage device is provided. A memory space of a buffer memory is allocated into a data area for storing user data and a map area for storing map data. The user data and the map data are read from a nonvolatile memory. A size of the user data to be stored in the data are compared with a size of the data area. The size of the data area and the size of the map area are adaptively varied according to the comparison result.

Abstract: Systems and methods for performing memory management among a plurality of devices in a network are described. In one implementation, the method for performing memory management comprises obtaining memory requirements for execution of an application. The memory requirements indicate memory space needed for executing the application. Further, the method comprises creating at least one memory pool, based on the memory requirements, by aggregating physical memories of the plurality of devices. Further, the method comprises executing the application in the at least one memory pool using semaphores and a mutex application programming interface (API).

Abstract: A multiplexer tree operable to control an output a sequence of data stored in a plurality of storage units in accordance with a non-linear address sequence that has less bit transition counts than a linear address sequence. The non-linear address sequence is provided to the selection inputs of the multiplexer tree and causes the levels having greater numbers of multiplexers to toggle less frequently than the levels having smaller numbers of multiplexers. The non-linear address sequence may comprise a Gray code sequence where every two adjacent addresses differ by a single bit. The non-linear address sequence may be optimized to minimize transistor switching in the multiplexer tree.

Abstract: An apparatus and method is described herein for providing instantaneous, efficient cache state recover upon an end of speculative execution. Speculatively accessed entries of a cache memory are marked as speculative, which may be on a thread specific basis. Upon an end of speculation, the speculatively marked entries are transitioned in parallel by a speculative port to their appropriate, thread specific, non-speculative coherency state; these parallel transitions allow for instantaneous commit or recovery of speculative memory state.

Abstract: A method for performing a cryptographic function on text to generate converted text comprises producing a random key stream having a first block size in a first frequency domain; converting the random key stream having a first block size in the first frequency domain to a random key stream in a second frequency domain; converting the random key stream having the first block size in the second frequency domain into smaller block sizes, thereby producing smaller block-sized random key stream of the second frequency domain; and converting the text using the smaller block-sized random key stream of the second frequency domain to produce the converted text. The frequency in the first frequency domain is preferably lower than the frequency in the second frequency domain.

Abstract: A particular device includes a resistance-based memory device, a tag random-access memory (RAM), and a bit recovery (BR) memory. The resistance-based memory device is configured to store a data value and error-correcting code (ECC) data associated with the data value. The tag RAM is configured to store information that maps memory addresses of a main memory to wordlines of a cache memory, where the cache memory includes the resistance-based memory device. The BR memory is configured to store additional error correction data associated with the data value, where the BR memory corresponds to a volatile memory device.

Abstract: A slice consistency check method is presented including, for each slice of a plurality of slices (a) obtaining a first vote for ownership of that slice according to a filesystem manager configured to manage a set of filesystems stored on a set of sparse metavolumes, (b) obtaining a second vote for the ownership of that slice according to a first driver, the first driver being independent of the filesystem manager, (c) obtaining a third vote for the ownership of that slice according to a second driver, the second driver being independent of the filesystem manager and the first driver, and (d) assigning ownership of that slice based on a majority vote of the first vote for the ownership of that slice, the second vote for the ownership of that slice, and the third vote for the ownership of that slice.

Abstract: An enhanced dynamic address translation facility is provided. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.

Abstract: A host based caching technique may be used to determine caching policies for a hybrid hard disk drive. Because the host based caching may make use of knowledge about what data is being cached, improved performance may be achieved in some cases.

Abstract: The present disclosure provides storage management systems and methods. A hierarchical configuration information process includes accessing information regarding hierarchical relationships of components associated with a storage environment. A storage resource consumption detection process includes detecting consumption of storage resources included in the storage environment. A coordinated consumption analysis process is coordinated across multiple levels of an active spindle hierarchy. A reaction process includes performing an automated consumption notification process and an automated reclamation process based upon results of the storage resource consumption detection process.

Abstract: In various embodiments, a single virtualized error correcting code (ECC) NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack. In various embodiments, a controller manages a plurality of NAND memory devices. The controller provides power to a select one of the plurality of NAND memory devices at a time to conserve overall power consumption of the storage system.

Abstract: A director node of a plurality of nodes determines a plurality of data arrays, where the plurality of data arrays have been discovered at boot time. The director node determines global metadata information, based on reading boot sectors of at least one of the plurality of data arrays discovered at boot time. A determination is made from the global metadata information as to how many data arrays had been previously configured. In response to determining that the plurality of data arrays discovered at boot time is not equal in number to the previously configured data arrays, the director node determines that all configured data arrays have not been discovered.

Abstract: In accordance with one embodiment, an information processing apparatus comprises an acquisition module configured to acquire an image of a commodity, a detection module configured to detect the commodity from the image acquired by the acquisition module, a recognition module configured to compare the feature amount of the commodity detected by the detection module with the feature amount of each reference commodity to recognize the reference commodity of which the similarity degree is greater than a threshold value as a commodity candidate, a commodity candidate display module configured to display the commodity candidates recognized before a given waiting time period elapses in the descending order of similarity degree, and then successively display the commodity candidates recognized after the waiting time period elapses in sequence, and a reception module configured to receive an operation of selecting one from the displayed commodity candidates.

Abstract: A system including a non-volatile semiconductor memory (NVSM), an interface module and a control module. The NVSM stores first and second blocks of data. The first or second block of data is non-page based such that a size of the first block of data or a size of the second block of data is not an integer multiple of a page of data. The interface module transfers the first and second blocks of data during respectively a first data transfer event and a second data transfer event. The control module, based on descriptors, controls the first and second data transfer events such that the interface module transfers the first block of data between the interface module and the NVSM while transferring the second block of data between the interface module and the NVSM. The descriptors include respective sets of instructions for transferring the first and second blocks of data.

Abstract: A computer-implemented method for securing storage space may include 1) identifying a block map that indicates whether each of a plurality of blocks within a storage system is to return zeroed data in response to read operations, 2) identifying a read operation directed to a block of the storage system that includes non-zeroed data, 3) determining, in response to identifying the read operation, that the block map indicates that the block is to return zeroed data in response to the read operation, and 4) returning zeroed data in response to the read operation based on determining that the block map indicates that the block is to return zeroed data. Various other methods, systems, and computer-readable media are also described.

Abstract: A method is used in managing provisioning of storage in storage systems. Whether a logical object requires a slice for recovering the logical object is determined. Based on the determination, storage for the slice is provisioned. The slice is provided to the logical object.

Abstract: Embodiments of methods, systems, and apparatuses for configuring a hardware device in a platform are described. In an exemplary method, a configuration message is received that indicates that the hardware device is to be upgraded from a first configuration to a second configuration, wherein the first and second configurations were pre-determined based on previous testing of the hardware device and are stored in the hardware device. The hardware device is then configured to the second configuration.

Abstract: Disclosed is a content interchange bus that is configured for (i) receiving a first content creation request from a client, the first content creation request including a first content object that includes data intended for distribution, a first metadata name/value pair describing the first content object, and a second metadata name/value pair describing a first content container; (ii) creating the first content container in the cloud storage platform; (iii) storing the first content object in the cloud storage platform; (iv) receiving a first message from the client, the first message including the first content container's uniform resource identifier and/or the first content object's uniform resource identifier, the message including a topic string that includes a first routing string; and (v) routing the first message to a first subscriber based at least partially on the topic string including the first routing string.

Abstract: An image forming apparatus according to the present disclosure includes: a first IC chip; a second IC chip connected to the first IC chip via a serial bus; and a memory that is either connected to or included in the first IC chip. The first IC chip includes: a first internal bus; a memory controller of the memory; a first processing circuit which outputs an access request to the memory; plural buffers corresponding to plural arbitration priority degrees of the first internal bus, and a request classifying circuit which identifies an arbitration priority degree of a requester of the access request received from the second IC chip and causes a buffer corresponding to the identified arbitration priority degree to buffer the access request. The first internal bus performs arbitration of access requests from the first processing circuit and the plural buffers in accordance with the arbitration priority degrees.

Abstract: The present invention provides a method and system to reduce the impact of errors introduced in flash devices while providing improved system performance through optimized activities with limited impact to overhead using a predetermined threshold value or threshold device value. In an embodiment, a device threshold value is compared with the cumulative number of data bits having a zero value of a target page and an error type of the target page is assessed to determine whether the target page is available to be written to. Therefore for a highly effective method for is provided for determining the availability of a page, having a block address and page address, to be identified, in one instance, as being an erased page that is available to be written to.

Abstract: Various embodiments for storage initialization and data destage in a computing storage environment are provided. At least a portion of data on a storage device is initialized using a background process, while one of simultaneously and subsequently destaging the at least the portion of the data to the storage device using a foreground process is performed. A persistent metadata bitmap, adapted to indicate whether the at least the portion of the data has been initialized, is staged to cache, the cache operable in the computing storage environment. The background process maintains a volatile bitmap indicating a status of the initialization of the at least the portion of the data in direct correspondence to the metadata bitmap. As the background process initializes the at least the portion of the data, an applicable bit on the persistent metadata bitmap is cleared and a corresponding bit is set on the volatile bitmap.

Abstract: One or more embodiments are directed a solid state storage device for maintaining versions of data. The solid state storage device comprises a processor and a solid state memory communicatively coupled to the processor. A flash translation layer receives at least one request from a file system to write at least one dataset to a logical page of the solid state memory. At least one physical page in a data block of the solid state memory associated with the logical page is identified. At least one dataset in the physical page is stored. At least one data versioning tag is associated with the dataset in a data structure associated with the logical page. The data versioning tag identifies the dataset as a given version of the logical page. The dataset is maintained as accessible from the physical page irrespective of subsequent write operations to the logical page.

Abstract: The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

Abstract: Various embodiments are directed to maintaining versions of data within a solid state memory. At least one request to write at least one dataset to a logical page of a solid state memory is received from a file system. At least one physical page in a data block of the solid state memory associated with the logical page is identified. A processor stores the dataset in the at least one physical page. At least one data versioning tag is associated with the at least one dataset in a data structure associated with the logical page. The data versioning tag identifies the at least one dataset as a given version of the logical page. The at least one dataset is maintained as accessible from the at least one physical page irrespective of subsequent write operations to the logical page in response to associating the at least one data versioning tag.

Abstract: A method and apparatus dynamically allocates and deallocates a portion of a cache for use as a dedicated local storage. Cache lines may be dynamically allocated and deallocated for inclusion in the dedicated local storage. Cache entries that are included in the dedicated local storage may not be evicted or invalidated. Additionally, coherence is not maintained between the cache entries that are included in the dedicated local storage and the backing memory. A load instruction may be configured to allocate, e.g., lock, a portion of the data cache for inclusion in the dedicated local storage and load data into the dedicated local storage. A load instruction may be configured to read data from the dedicated local storage and to deallocate, e.g., unlock, a portion of the data cache that was included in the dedicated local storage.

Abstract: Embodiments of the invention are directed to providing detailed error reporting of data operations performed on a NVM storage device. In one embodiment, a controller interfaces with a NVM storage device including NVM storage coupled with a bridge. In one embodiment, the controller is provided physical, page-level access to the NVM via the bridge, and the bridge provides detailed error reporting of the data operations that the bridge performs on the NVM on behalf of the controller. For example, the bridge may provide page level reporting indicating which page(s) failed during a read operation. Detailed error reporting allows the controller to better understand the failures that occurred in a data access operation in the NVM. It also enables the controller to manage the flash media at the physical page/block level. In one embodiment, detailed error reporting also enables the return of discontinuous ranges of data with the error portions removed.

Abstract: A method and apparatus dynamically allocates and deallocates a portion of a cache for use as a dedicated local storage. Cache lines may be dynamically allocated and deallocated for inclusion in the dedicated local storage. Cache entries that are included in the dedicated local storage may not be evicted or invalidated. Additionally, coherence is not maintained between the cache entries that are included in the dedicated local storage and the backing memory. A load instruction may be configured to allocate, e.g., lock, a portion of the data cache for inclusion in the dedicated local storage and load data into the dedicated local storage. A load instruction may be configured to read data from the dedicated local storage and to deallocate, e.g., unlock, a portion of the data cache that was included in the dedicated local storage.

Abstract: Among other things, one or more techniques and/or systems are provided for storing data within a hybrid storage aggregate comprising a lower-latency storage tier and a higher-latency storage tier. In particular, frequently accessed data, randomly accessed data, and/or short lived data may be stored (e.g., read caching and/or write caching) within the lower-latency storage tier. Infrequently accessed data and/or sequentially accessed data may be stored within the higher-latency storage tier. Because the hybrid storage aggregate may comprise a single logical container derived from the higher-latency storage tier and the lower-latency storage tier, additional storage and/or file system functionality may be implemented across the storage tiers. For example, deduplication functionality, caching functionality, backup/restore functionality, and/or other functionality may be provided through a single file system (or other type of arrangement) and/or a cache map implemented within the hybrid storage aggregate.

Abstract: Systems, methods, and other embodiments associated with a distributed cache coherency protocol are described. According to one embodiment, a method includes receiving a request from a requester for access to one or more memory blocks in a block storage device that is shared by at least two physical computing machines and determining if a caching right to any of the one or more memory blocks has been granted to a different requester. If the caching right has not been granted to the different requester, access is granted to the one or more memory blocks to the requester.

Abstract: A partition manager relocates a logical partition from a primary shared processor pool to a secondary shared processor pool in response to a predetermined condition, such as a hardware failure. The relocated logical partition is allocated a smaller quantity of processing units from the secondary pool than it was allocated from the primary pool. A quantity of processing units reserved for a second logical partition is identified in the secondary shared processor pool, and a portion of those reserved processing units are allocated to the relocated logical partition. The reserved processing units may be redistributed among multiple relocated logical partitions.

Abstract: A flash memory management method for managing a plurality of physical units of a flash memory chip is provided. The flash memory management method includes grouping a portion of the physical units into a data area and a spare area; configuring a plurality of logical units and setting mapping relationships between the logical units and the physical units of the data area. The flash memory management method further includes receiving data and writing the data into the physical unit mapped to a second logical unit among the logical units, and the data belongs to a first logical unit among logical units. Accordingly, the flash memory management method can effectively reduce the number of times for organizing valid data, thereby reducing the time for executing a host write-in command.

Abstract: In one embodiment, snapshots and/or clones of storage objects are created and managed by a volume layer of a storage input/output (I/O) stack executing on one or more nodes of a cluster. Illustratively, the snapshots and clones may be represented as independent volumes, and embodied as respective read-only copies (snapshots) and read-write copies (clones) of a parent volume. Volume metadata is illustratively organized as one or more multi-level dense tree metadata structures, wherein each level of the dense tree metadata structure (dense tree) includes volume metadata entries for storing the metadata. Each snapshot/clone may be derived from a dense tree of the parent volume (parent dense tree). Portions of the parent dense tree may be shared with the snapshot/clone.

Abstract: For analyzing and reducing dump data, an analysis module identifies each abending task of a job and identifies each stack block of each abending task. A dump module saves only stack block data from the identified stack blocks as dump data.

Abstract: A primary processing unit entitlement is determined for a logical partition. A smaller secondary processing unit entitlement is also determined. A partition manager allocates primary processing units to the logical partition from a primary shared processor pool, and the logical partition is activated. The secondary processing units are reserved for the logical partition from a secondary shared processor pool, and the logical partition can be relocated to the secondary shared processor pool in response to a condition such as a hardware failure. The logical partition can continue to process its workload with the fewer processor resources, and can be restored to the primary processing unit entitlement.

Abstract: Activity level of memory pages is classified in virtual machine environment, so that processes such as live VM migration and checkpointing, among others, can be carried out more efficiently. The method includes the steps of scanning page table entries of hypervisor-managed page tables continuously over repeating scan periods to determine whether memory pages have been accessed or not, and for each memory page, determining an activity level of the memory page based on whether the memory page has been accessed or not since a prior scan and storing the activity level of the memory page. The activity level of the memory page may be represented by one or more bits of its page table entry and may be classified as having at least two states ranging from hot to cold.

Abstract: A semiconductor memory system includes a memory controller and memory apparatus. The memory controller provides a first data having a first level and a second data having a second level. The memory apparatus adjusts a level of a reference voltage by comparing the reference voltage with each of the first data and the second data.

Abstract: A mechanism is provided in a cache subsystem for cache prefetching based on non-sequential access. The mechanism determines frequently accessed non-sequential cache records in the cache subsystem. The mechanism collects trailing record statistics for the frequently accessed non-sequential cache records. The mechanism determines a caching strategy. The caching strategy comprises prefetching a set of trailing records responsive to a read of a given frequently accessed non-sequential cache record. The mechanism applies the caching strategy to the cache subsystem.

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being emulated. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field or the fetch protection field is not enabled.

Abstract: In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened processor activity, thus ensuring that processing efficiency is not significantly impacted by a reduced cache size. In some embodiments, the cache size is increased based on a measured processor performance metric, such as an eviction rate of the cache. In some embodiments, the cache size is increased at regular intervals until a maximum size is reached.

Abstract: A method for writing updated data into a flash memory module having a plurality of physical pages is provided, wherein each physical page is the smallest writing unit of the flash memory module. The method includes partitioning a physical page into storage segments and configuring a state mark for each storage segment, wherein the state marks indicate the validity of data stored in the storage segments. The method also includes writing the updated data into at least one of the storage segments and changing the state mark corresponding to the storage segment containing the updated data, wherein the state mark corresponding to the storage segment containing the updated data indicates a valid state, and the state marks corresponding to the other storage segments of the physical page not containing the updated data indicate an invalid state. Thereby, the time for writing data into a physical page is effectively shortened.