Abstract: Techniques are provided for assigning read requests to storage devices in a manner that reduces the likelihood that any storage device will become overloaded or underutilized. Specifically, a read-request handler assigns read requests that are directed to each particular item among the storage devices that have copies of the item based on how busy each of those storage devices is. Consequently, even though certain storage devices may have copies of the same item, there may be times during which one storage device is assigned a disproportionate number of the reads of the item because the other storage device is busy with read requests for other items, and there may be other times during which other storage device is assigned a disproportionate number of the reads of the item because the one storage device is busy with read request for other items.

Abstract: A method and system for dynamic distributed data caching is presented. The system includes one or more peer members and a master member. The master member and the one or more peer members form cache community for data storage. The master member is operable to select one of the one or more peer members to become a new master member. The master member is operable to update a peer list for the cache community by removing itself from the peer list. The master member is operable to send a nominate master message and an updated peer list to a peer member selected by the master member to become the new master member.

Abstract: Methods, systems, and apparatus for storing and accessing data stored in a data array are presented. In one embodiment, data is stored in a data array that includes a plurality of nodes. The nodes of the data array are segmented into one or more standard and priority pages. The pages are represented in a packed index. The priority pages are then cached and the standard pages are saved to disk. In another embodiment, data stored in a node of a data array may be accessed wherein the data array is segmented into at least one priority page and at least one standard page and the data array includes a plurality of nodes. A request for data stored in the node may be received. A priority page and/or a standard page may be searched for the node and, when found, the node may be accessed.

Abstract: A method begins by a processing module receiving an encoded data slice for storage. The method continues with the processing module obtaining metadata associated with the encoded data slice and interpreting the metadata to determine whether the encoded data slice is to be stored in a first access speed memory or a second access speed memory, wherein the first access speed memory has a higher data access rate than the second access speed memory. The method continues with the processing module storing the encoded data slice in a memory device of the first access speed memory when the encoded data slice is to be stored in the first access speed memory and storing the encoded data slice in a memory device of the second access speed memory when the encoded data slice is to be stored in the second access speed memory.

Abstract: An information processing apparatus and an information processing method are capable of correctly selecting data to be deleted, without a user having to perform a troublesome operation. In a backup operation, a determination is made for each image file as to whether a predetermined condition is satisfied. If the condition is satisfied, image files are backed up, and storage priority levels defined for these image files are reduced in accordance with a rule predefined by a user. The storage priority level is a measure indicating the priority of keeping an image file in a storage unit. The higher the storage priority, the lower the probability that image files are deleted. The storage priority levels are changed depending on whether image files have been backed up and depending on the number of times image files were backed up.

Abstract: Systems and methods for controlling memory access operations are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines a destination bank, and the request is placed in an appropriate bank queue. An ordering unit determines if the current request can be reordered relative to the received order and generates a new memory cycle order based on the reordering determination. The reordering may be based on whether there are multiple requests to the same memory page, multiple reads, or multiple writes. A memory interface executes each memory request in the memory cycle order. A data buffer holds write data until it is written to the memory and read data until it is returned to the requestor. The data buffer also may hold memory words used in read-modify-write operations.

Abstract: Interrupts and code threads are assigned in a particular way to the core CPUs of a network file server in order to reduce latency for processing client requests for file access. Threads of the network stack are incorporated into real time threads that are scheduled by a real-time scheduler and executed exclusively by a plurality of the core CPUs that are not interrupted by disk adapter interrupts so that the disk adapter interrupts do not interrupt execution of the network stack. Instances of a storage access driver are hard affinity threads, and soft affinity threads include a multitude of instances of a thread of the file system stack for file access request processing so that file access request processing for a multitude of concurrent file access requests is load balanced over the core CPUs.

Abstract: A transactional memory system is described for reporting memory access violations which occur when memory accesses made from instructions within a transaction conflict with memory accesses to the same memory location made from a non-transactional instruction. In an embodiment this is achieved by creating two mappings of a physical heap being used by a thread. The thread (which may be part of a multi-threaded process) comprises instructions for both transactional and non-transactional accesses to the physical heap which may execute concurrently as part of that thread. One of the mappings is used for non-transactional memory accesses to the physical heap. The other mapping is used for transactional memory accesses to the physical heap. Access permissions associated with the mappings are controlled to enable attempted memory access violations to be detected and reported.

Abstract: A “request scheduler” provides techniques for batching and scheduling buffered thread requests for access to shared memory in a general-purpose computer system. Thread-fairness is provided while preventing short- and long-term thread starvation by using “request batching.” Batching periodically groups outstanding requests from a memory request buffer into larger units termed “batches” that have higher priority than all other buffered requests. Each “batch” may include some maximum number of requests for each bank of the shared memory and for some or all concurrent threads. Further, average thread stall times are reduced by using computed thread rankings in scheduling request servicing from the shared memory. In various embodiments, requests from higher ranked threads are prioritized over requests from lower ranked threads. In various embodiments, a parallelism-aware memory access scheduling policy improves intra-thread bank-level parallelism.

Abstract: A method and apparatus to utilize a strong ordering scheme to be performed on memory operations in a processor to prevent performance degradation caused by out-of-order memory operations is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes storing information associated with a first load operation in a load queue, the first load operation being executed out-of-order with respect to one or more second load operations. The method also includes detecting a snoop hit on the first load operation. The method further includes re-executing the first load operation in response to detecting the snoop hit.

Abstract: A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.

Abstract: Multi-write coding of non-volatile memories including a method that receives write data, and a write address of a memory page. The memory page is in either an erased state or a previously written state. If the memory page is in the erased state: selecting a first codeword from a code such that the first codeword encodes the write data and is consistent with a target set of distributions of electrical charge levels in the memory page; and writing the first codeword to the memory page. If the memory page is in the previously written state: selecting a coset from a linear code such that the coset encodes the write data and includes one or more words that are consistent with previously written content of the memory page; selecting a subsequent codeword from the one or more words in the coset; and writing the subsequent codeword to the memory page.

Abstract: Enhanced write performance for non-volatile memories including a memory system that includes a receiver for receiving a data rate of a data sequence to be written to a non-volatile flash memory device. The memory system also includes a physical page selector for selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, and for determining if the number of free bits in the invalid previously written memory page at the selected physical address is greater than or equal to the data rate. The memory system also includes a transmitter for outputting the selected physical address of the invalid previously written memory page, the outputting in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate.

Abstract: A memory system is operated by maintaining a queue of memory commands to be executed, maintaining a list of previously executed memory commands, comparing local information associated with the commands to be executed with local information associated with the list of previously executed commands, and selecting one of the commands for execution from the queue of memory commands to be executed based on a result of the comparison.

Abstract: A system having memory access capabilities, the system includes: (i) a dynamic voltage and frequency scaling (DVFS) controller, adapted to determine a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to the first memory access requester and to generate a DVFS indication that is indicative of the determination; (ii) a hardware access request determination module, adapted to determine a priority of memory access request issued by the first memory access requester in response to the DVFS indication; and (iii) a direct memory access arbitrator, adapted to arbitrate between memory access requests issued by the first memory access requester and another memory access requester in response to priorities associated with the memory access requests.

Abstract: A portable data storage device compatible with both standard and high definition digital video cameras is provided. The device includes at least one SDI I/O, and preferably at least one audio I/O and preferably at least one medium speed I/O interface. A device controller takes the high speed serial data, packetizes it, and then sends it out to a plurality of memory modules. Preferably each memory module includes four NAND clusters, each NAND cluster consisting of a flash memory controller and two NAND flash memories. Interposed between the device controller and the memory modules are a plurality of memory controllers, each memory controller controlling a group of memory modules. A user interface is coupled to the device controller, the interface including a display capable of at least two user-selectable orientations, record/playback controls and a four-way directional control pad.

Abstract: Techniques are provided for enabling execution of a process employing a cache Method steps can include obtaining a first probability of accessing a given artifact in a state Si, obtaining a second probability of using a predicate from a current state Sc in the state Si, determining a benefit of prefetching the given artifact using the predicate based on at least the first probability and the second probability, and whether and/or when a cache replacement should be conducted, based at least on the benefit determined.

Abstract: A memory control apparatus, a memory control method and an information processing system are disclosed. Fetch response data retrieved from a main storage unit is received, while bypassing a storage unit, by a first port in which the received fetch response data can be set. The fetch response data retrieved from the main storage unit, if unable to be set in the first port, is set in a second port through the storage unit. A transmission control unit performs priority control operation to send out, in accordance with a predetermined priority, the fetch response data set in the first port or the second port to the processor. As a result, the latency is shortened from the time when the fetch response data arrives to the time when the fetch response data is sent out toward the processor in response to a fetch request from the processor.

Abstract: A solid-state storage subsystem, such as a non-volatile memory card or drive, includes multiple interfaces and a memory area storing information used by a data arbiter to prioritize data commands received through the interfaces. As one example, the information may store a priority ranking of multiple host systems that are connected to the solid-state storage subsystem, such that the data arbiter may process concurrently received data transfer commands serially according to their priority ranking. A host software component may be configured to store and modify the priority control information in solid-state storage subsystem's memory area.

Abstract: Methods and systems for allowing access to computer storage systems. Multiple requests from multiple applications can be received and processed efficiently to allow traffic from multiple customers to access the storage system concurrently.

Abstract: The present invention discloses a memory sharing mechanism based on priority elevation. In accordance with the present invention, there is provided an apparatus and method for transporting packets of data in a communication device, wherein each packet is assigned one of several priorities and received based on memory state information. The method comprises the steps of storing the received packets in a memory and modifying the assigned priority of any of the packets causing congestion within the memory.

Abstract: The invention relates generally to computer memory access. Embodiments of the invention provide a multi-level page-walk apparatus and method that enable I/O devices to execute multi-level page-walks with an out-of-order memory controller. In embodiments of the invention, the multi-level page-walk apparatus includes a demotion-based priority grant arbiter, a page-walk tracking queue, a page-walk completion queue, and a command packetizer.

Abstract: A system includes a memory controller adapted to output address signals, command signals and select signals; a plurality of memory modules; and a plurality of buses each corresponding to one of the memory modules. Each bus is adapted to transmit corresponding ones of the address signals, the command signals, and the select signals to the corresponding memory module. Each of the memory modules includes: a plurality of memory devices; and a register adapted to receive and buffer the corresponding command and address signals transmitted to the memory module, and adapted to transmit the buffered command signal to the memory devices which are to be accessed, in response to the corresponding select signal for accessing the memory devices.

Abstract: Embodiments in accordance with the invention permit a virtualization application to interact with a SuperFetch feature of an operating system so that on creation of a virtualization layer the SuperFetch feature is provided the opportunity to act on the newly available file system objects of the virtualization layer. Further, when the virtualization layer is removed, embodiments in accordance with the invention remove the file system objects associated with the virtualization layer from utilization by the SuperFetch feature.

Abstract: A memory access control apparatus includes a plurality of memory access request generating modules and an arbitrator. When one of the memory access request generating modules receives a second memory access event while a memory device is performing a first memory access operation according to a first memory access request in response to a first memory access event, the memory access request generating module outputs a second memory access request corresponding to the second memory access event to the memory device after a delay time. The arbitrator is implemented for arbitrating memory access requests respectively outputted from the memory accessing request generating modules.

Abstract: An I/O Optimizer receives an I/O request specifying a plurality of disk blocks of the disk drive for access. A plurality of I/O sub-requests is determined from the I/O request, each I/O sub-request specifying a set of one or more adjacent disk blocks of the plurality of disk blocks along the same cylinder. A plurality of execution sequences for performing the plurality of I/O sub-requests is determined. For each of the plurality of execution sequences, a total estimated execution time for performing the I/O sub-requests according to the execution sequence is calculated. One of the plurality of execution sequences for performing the I/O sub-requests is selected based, at least in part, on the total estimated execution times for the plurality of execution sequences. A disk drive controller is instructed to perform the I/O sub-requests according to the selected execution sequence.

Abstract: A method begins by a processing module determining a priority access level of an encoded data slice stored on a memory device. The method continues with the processing module determining an end-of-life memory level for the memory device. The method continues with the processing module determining whether to migrate the encoded data slice from the memory device based on the priority access level and the end-of-life memory level. The method continues with the processing module identifying another memory device. The method continues with the processing module facilitating migration of the encoded data slice to another memory device.

Abstract: Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.

Abstract: A method and an apparatus for determining a dependency relationship between graphics commands based on availability of graphics hardware resources to perform graphics processing operations according to the dependency relationship are described. The graphics commands may be received from graphics APIs (application programming interfaces) for rendering a graphics object. A graphics driver may transmit a portion or all of the received graphics commands to a graphics processing unit (GPU) or a media processor based on the determined dependency relationship between the graphics commands.

Abstract: A display control circuit capable of performing arbitration with the use of a simple configuration. The display control circuit exchanges, with a plurality of masters, attribute information defining conditions for displaying video on a display, and includes a memory for storing the attribute information, a plurality of channels associated with the respective masters for accepting, from the masters, access requests to access the memory, and an arbitration controller configured by hardware. The arbitration controller arbitrates the access requests accepted via the respective channels and permits a selected one of the access requests to access the memory.

Abstract: A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.

Abstract: An apparatus, system, and method are disclosed for enqueue prioritization. The apparatus for enqueue prioritization is provided with a plurality of modules configured to functionally execute the necessary steps of anticipating a need to access a computing resource, generating a dummy request, the dummy request configured to hold a place for an actual request in a queue of requests to access the computing resource, and generating an actual request to access the computing resource, wherein the actual request is configured to replace the dummy request in the queue. These modules in the described embodiments include a forecast module, a dummy generator, and a request generator.

Abstract: Concurrent threads in a multithreaded processor share access to a memory, with any location in the shared memory being accessible by any thread. In one embodiment, the shared memory has multiple independently-addressable memory banks, and one location per bank can be accessed in parallel. Parallel processing engines executing the threads generate a group of parallel memory access requests. Address conflict logic determines whether the requests can be satisfied in parallel (e.g., based on bank access constraints) and serializes the requests to the extent needed to avoid conflicts. In some embodiments, data read from one address in the shared memory can be broadcast to multiple processing engines.

Abstract: A method and a host processing device are provided for background formatting, or de-icing, an optical medium with no de-icing assistance from an optical drive upon which the optical medium is mounted. In a foreground mode, an optical medium may be initially formatted, volume structures may be recorded on the optical medium, file system information may be written thereto, and quick grow formatting may be performed to make the optical medium writable, at least sequentially. Under initiation and control of a file system, executing on a host processing device, the optical medium may be formatted, or de-iced, in a background mode with no assistance from an optical drive, upon which the optical medium is mounted. Under control of the file system, blocked input or output activity, may be allowed to access the optical medium upon pausing the formatting, or de-icing.

Abstract: The present invention discloses a method for scheduling queues based on a chained list.

Abstract: A technique for accessing a memory array includes receiving, from multiple requesters, memory access requests directed to a single port of the memory array. The memory access requests associated with each of the multiple requesters are serviced, based on a priority assigned to each of the multiple requesters, while maintaining a fixed timing for the memory access requests.

Abstract: An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is included that comprises a plurality of queue entries coupled in series, with a top queue entry coupled to the read/write module. Each queue entry is capable of storing a memory command. Each queue entry includes its own queue control logic that functions to control storage of new memory commands into the command queue to reduce latency of commands in the command queue.

Abstract: The memory access device includes: a plurality of command division sections provided for a plurality of masters; a plurality of inter-master arbitration sections provided for a plurality of banks; and a memory control section. Each of the command division sections divides a command issued by the corresponding master into a plurality of micro-commands when the access region of the command is over two or more banks among the plurality of banks, each of the micro-commands being a command accessing only one of the two or more banks, and gives each of the micro-commands to an inter-master arbitration section corresponding to the bank including the access region of the micro-command. Each of the inter-master arbitration sections arbitrates micro-commands given from the command division sections to select one. The memory control section selects one of a plurality of micro-commands selected by the inter-master arbitration sections to perform memory access.

Abstract: Methods and systems are provided for delivering content from a website to a computer device. The website and computer device negotiate terms for use of a cache memory coupled to the computer device. The computer device requests content, such as web page objects, from the website. In addition to transmitting the requested content, the website transmits non-requested content to the computer device. The non-requested content is stored in the cache memory for later retrieval by the computer device.

Abstract: A computer includes a memory that stores data, a cache memory that stores a copy of the data, a directory storage unit that stores directory information related to the data and includes information indicating that the data is copied to the cache memory, a directory cache storage unit that stores a copy of the directory information stored in the directory storage unit, and a control unit that controls storage of data in the directory cache storage unit, manages the data copied from the memory to the cache memory by dividing the data into an exclusive form and a shared form, and sets a priority of storage of the directory information related to the data fetched in the exclusive form in the directory cache storage unit higher than a priority of storage of the directory information related to the data fetched in the shared form in the directory cache storage unit.

Abstract: In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.

Abstract: A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device. The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.

Abstract: In an IC card, an operating system manages the access order of each channel for each file using a channel management table. An application controls access to each file based on the access order managed in the channel management table. The channel management table stores, as an access order, an order that each logical channel has set a file in a current state. If current setting by a specific logical channel is canceled, a table updating function deletes the logical channel from the channel management table and moves up the access order of each logical channel next to the deleted logical channel.

Abstract: The most important data in a first memory of a data processing system are stored in a limited second data memory given upon a transfer thereof. The demarcation between important (and still storable) data on the one hand and less important (and therefore no longer storable) data is made dependent on the available storage volume (SV) of the target data memory. This achieves that an optimal amount of the most important data can be stored on the target data memory.

Abstract: A method, and corresponding system and software, is described for writing data to a plurality of queues, each portion of the data being written to a corresponding one of the queues. The method includes, without requiring concurrent locking of more than one queue, determining if a space is available in each queue for writing a corresponding portion of the data, and if available, reserving the spaces in the queues. The method includes writing each portion of the data to a corresponding one of the queues.

Abstract: An adaptive input/output (I/O) scheduler for storage arrays is disclosed. In one embodiment, a method of a redundant array of independent disks (RAID) controller for deploying an optimal I/O scheduler type per a storage array configuration includes generating performance data by assessing respective performances of a plurality of I/O scheduler types on different RAID level test volumes with at least one I/O pattern generated internally within a storage subsystem which comprises the RAID controller. The method also includes storing the associativeness of the performance data with respect to a particular I/O scheduler most suited for a given I/O workload to a nonvolatile memory of the RAID controller. The method further includes deploying an optimal one of the plurality of I/O scheduler types and at least one performance parameter for at least one subsequent I/O operation associated with the storage subsystem based on the performance data.

Abstract: File system disaster recovery techniques provide automated monitoring, failure detection and multi-step failover from a primary designated target to one of a designated group of secondary designated targets. Secondary designated targets may be prioritized so that failover occurs in a prescribed sequence. Replication of information between the primary designated target and the secondary designated targets allows failover in a manner that maximizes continuity of operation. In addition, user-specified actions may be initiated on failure detection and/or on failover operations and/or on failback operations.

Abstract: A multi-cell disk drive test system that provides a power recovery mode is disclosed. The multi-cell disk drive test system includes a test platform having a plurality of cells configured to receive and to provide communication with disk drives loaded therein, respectively, and test logic. The test logic is coupled to a cell and is configured to operate a test application to: execute a series of test modules to test a disk drive loaded in the cell; switch from a normal mode to a power recovery mode responsive to a power recovery flag relating to a power failure; and in the power recovery mode, read a test sequence index identifying a last completed test module before the power failure and execute a subsequent series of test modules following the last completed test module for the disk drive.

Abstract: Provided are a relocation system and a relocation method capable of relocating a virtual volume that is formed based on thin provisioning while ensuring security against exhaustion of pools. A database stores attribute information for pools and virtual volumes for thin provisioning that exist in a storage device as well as parameters for predicting time period till exhaustion of the pools. When a virtual volume is to be relocated between a plurality of pools, a relocation control section predicts time periods till exhaustion of the pools before and after relocation based on information in the database and determines the relocation is possible or not based on the result of prediction or determines an appropriate relocation plan. This enables control of relocation of virtual volumes.

Abstract: A disk is divided into K angular regions. A log write request is replicated K times and K number of identical log writes are issued to the disk to be written to each of the angular regions of the log. Upon completion of the first write, the application requesting the log write is informed of its completion resulting in a reduction of rotational latency by a factor of K.