Abstract: A RAID group of RAID 1 series comprises one or more pairs of first storage devices and second storage devices. A storage apparatus reads data from the entire area of a first storage block group including the write destination of write target data in the first storage device. The storage apparatus, in accordance with the write target data and staging data which is the read data, generates one or more data units each of which is the data configured of the write target data or the copy of the same and the staging data part or the copy of the same and of the same size as the first storage block group. The controller writes any of the one or more data units to the first storage block group in the first storage device and, at the same time, writes any of the one or more data units to the second storage block group corresponding to the first storage block group and of the same size as the same in the second storage device.

Abstract: A method for optimizing a plurality of volume records stored in cache may include monitoring a volume including multiple data sets, wherein each data set is associated with a volume record, and each volume record is stored in a volume record data set. The method may include tracking read and write operations to each of the data sets over a period of time. The method may further include reorganizing the volume records in the volume record data set such that volume records for data sets with a larger number of read operations relative to write operations are grouped together, and volume records for data sets with a smaller number of read operations relative to write operation are grouped together. A corresponding apparatus and computer program product are also disclosed.

Abstract: Disclosed is a device, method and computer-readable medium relocating Remote Procedure Call (RPC) data in a heterogeneous multiprocessor System-on-Chip (MPSoC). The method, for example, includes determining a memory where data is to be stored based on a use of a parameter of a function, and data access patterns of a function caller and a function callee, and storing the data in the determined memory.

Abstract: High availability (HA) protection is provided for an executing virtual machine. At a checkpoint in the HA process, the active server suspends the virtual machine; and the active server copies dirty memory pages to a buffer. During the suspension of the virtual machine on the active host server, dirty memory pages are copied to a ring buffer. A copy process copies the dirty pages to a first location in the buffer. At a predetermined benchmark or threshold, a transmission process can begin. The transmission process can read data out of the buffer at a second location to send to the standby host. Both the copy and transmission processes can operate asynchronously on the ring buffer. The ring buffer cannot overflow because the transmission process continues to empty the ring buffer as the copy process continues. This arrangement allows for using smaller buffers and prevents buffer overflows, and thereby, it reduces the VM suspension time and improves the system efficiency.

Abstract: The present application is directed to a memory-access-multiplexing memory controller that can multiplex memory accesses from multiple hardware threads, cores, and processors according to externally specified policies or parameters, including policies or parameters set by management layers within a virtualized computer system. A memory-access-multiplexing memory controller provides, at the physical-hardware level, a basis for ensuring rational and policy-driven sharing of the memory-access resource among multiple hardware threads, cores, and/or processors.

Abstract: A storage unit includes one or more storage devices. In one embodiment, it is determined whether a temperature associated with the storage unit is below a minimum threshold. In another embodiment, it is determined whether a predicted heat load of the storage unit is below a minimum threshold. A predicted heat load for the storage unit is increased by initiating a data operation in the storage devices in response to determining that the temperature, or the predicted heat load, is below the minimum threshold.

Abstract: An input/output (I/O) device includes a host interface for connection to a host device having a memory, and a network interface, which is configured to transmit and receive, over a network, data packets associated with I/O operations directed to specified virtual addresses in the memory. Processing circuitry is configured to translate the virtual addresses into physical addresses using memory keys provided in conjunction with the I/O operations and to perform the I/O operations by accessing the physical addresses in the memory. At least one of the memory keys is an indirect memory key, which points to multiple direct memory keys, corresponding to multiple respective ranges of the virtual addresses, such that an I/O operation referencing the indirect memory key can cause the processing circuitry to access the memory in at least two of the multiple respective ranges.

Abstract: A system and method for scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency.

Abstract: A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.

Abstract: A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Abstract: A method and apparatus for detecting and preemptively ameliorating potential logic unit thrashing in a storage system having multiple I/O requesters is disclosed. In response to detecting that each of two requesters has usable access to both of the active-passive pair of controllers, one of the active-passive pair of controllers is selected to be designated as an active resource controller. In response to detecting that one of the two requesters has usable access to only one of the active-passive pair of controllers, only one of the active-passive pair of controllers is selected to be designated as an active resource controller. In response to detecting that each of the two requesters has usable access only to different ones of the active-passive pair of controllers, one of the active-passive pair of controllers is selected to be designated as an active resource controller.

Abstract: A memory protection unit (MPU) is configured to store a plurality of region descriptor entries, each region descriptor entry defining an address region of a memory, an attribute corresponding to the region, and an attribute override control corresponding to the attribute. A memory access request to a memory address is received and determined to be within a first address region defined by a first region descriptor entry and within a second address region defined by a second region descriptor entry. When the attribute override control of the first region descriptor entry indicates that override is to be performed, the value of the attribute of the first region descriptor entry is applied for the memory access. When the attribute override control of the second region descriptor entry indicates that override is to be performed, the value of the attribute of the second region descriptor entry is applied for the memory access.

Abstract: The exemplary embodiments provide a computer-implemented method, apparatus, and computer-usable program code for managing memory. A notice of a shortage of real memory is received. For each active thread, the thread classification of the active thread is compared to a global hierarchy of thread classifications to determine a thread to affect. The global hierarchy of thread classifications defines the relative importance of each thread classification. An action to take for the determined thread is determined. The determined action is performed for the determined thread.

Abstract: An information processing apparatus and an information processing method are capable of correctly selecting data to be deleted, without a user having to perform a troublesome operation. In a backup operation, a determination is made for each image file as to whether a predetermined condition is satisfied. If the condition is satisfied, image files are backed up, and storage priority levels defined for these image files are reduced in accordance with a rule predefined by a user. The storage priority level is a measure indicating the priority of keeping an image file in a storage unit. The higher the storage priority, the lower the probability that image files are deleted. The storage priority levels are changed depending on whether image files have been backed up and depending on the number of times image files were backed up.

Abstract: According to an embodiment, a memory system includes a memory unit, a memory controller, a timer and a timer control unit. The memory unit has nonvolatile first and second chips capable of holding data. The memory controller transfers data received from host equipment simultaneously to the first and second chips. The timer measures a lapse of preset shift time. The timer control unit starts writing of data into the second chip immediately after the lapse of the shift time.

Abstract: A data read/write system includes a system clock, a single port memory, a cache memory that is separate from the single port memory, and a controller coupled to an instruction pipeline. The controller receives, via the instruction pipeline, first data to write to an address of the single port memory, and further receives, via the instruction pipeline, a request to read second data from the single port memory. The controller stores the first data in the cache memory, and retrieves the second data from either the cache memory or the single port memory during one or more first clock cycles of the system clock. The controller copies the first data from the cache memory and stores the first data at the address in the single port memory during a second clock cycle of the system clock that is different than the one or more first clock cycles.

Abstract: Memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard. If the memory manager detects the computing device is experiencing memory pressure, the memory manager may address the memory pressure by selecting memory space available for discard and discarding the content of the memory space. Before a process reuses content made available for discard, the process may notify the memory manager of the intent to reuse and, in response, receive empty memory and an indication that the content was discarded or receive an indication that the content is still available for use.

Abstract: A method for managing operation of a memory includes determining a status of data stored at a memory address, assigning a code based on the status of the data, and selectively performing a power management operation for an area of a memory that includes the memory address based on the code.

Abstract: A system comprises a first storage system including a first storage controller, which receives input/output commands from host computers and provides first storage volumes to the host computers; and a second storage system including a second storage controller which receives input/output commands from host computers and provides second storage volumes to the host computers. A first data storing region of one of the first storage volumes is allocated from a first pool by the first storage controller. A second data storing region of another one of the first storage volumes is allocated from a second pool by the first storage controller. A third data storing region of one of the second storage volumes is allocated from the first pool by the second storage controller. A fourth data storing region of another one of the second storage volumes is allocated from the second pool by the second storage controller.

Abstract: A method begins by a processing module identifying a memory device having an expired useable memory life with respect to a legacy storage protocol. The method continues with the processing module extracting data from the memory device. The method continues with the processing module reprovisioning the memory device from the legacy storage protocol to a dispersed storage error coding storage protocol.

Abstract: Embodiments of the present invention provide a system for scheduling memory accesses for one or more memory devices. This system includes a set of queues configured to store memory access requests, wherein each queue is associated with at least one memory bank or memory device in the one or more memory devices. The system also includes a set of hierarchical levels configured to select memory access requests from the set of queues to send to the one or more memory devices, wherein each level in the set of hierarchical levels is configured to perform a different selection operation.

Abstract: An apparatus comprising a controller and an array. The controller may be configured to generate control signals in response to one or more input requests. The array may comprise a plurality of solid state devices. The solid state devices may be configured to (i) read and/or write data in response to the control signals received from the controller and (ii) distribute writes across the plurality of solid state devices such that each of said solid state devices has a similar number of writes.

Abstract: A memory device includes a pad that provides an interface with an exterior, a first setting unit that generates a termination setting signal for setting the pad for a purpose of termination data strobe using a first specific code of a mode register set operation, a second setting unit that generates a mask setting signal for setting the pad for a purpose of data mask using a second specific code of the mode register set operation, and a third setting unit that generates a write inversion setting signal for setting the pad for a purpose of write data bus inversion using third specific code of the mode register set operation. When a setting signal with a higher priority is activated, a setting signal with a lower priority is deactivated regardless of a value of the corresponding code.

Abstract: In one embodiment, the present invention includes a method for identifying a memory request corresponding to a load instruction as a critical transaction if an instruction pointer of the load instruction is present in a critical instruction table associated with a processor core, sending the memory request to a system agent of the processor with a critical indicator to identify the memory request as a critical transaction, and prioritizing the memory request ahead of other pending transactions responsive to the critical indicator. Other embodiments are described and claimed.

Abstract: A system and method for use in an automated data storage cartridge library defines cartridges for use with an external host computer (“open” cartridges), and cartridges for use only internal to the library (“closed” cartridges). Cartridges may be “virtualized” by storing data from them on disk or closed cartridges, and then “realized” by writing data to physical cartridges. Virtual cartridges may be logically exported from one library to another. When new cartridges are introduced to the library, they may be designated with one of multiple designations or uses.

Abstract: An apparatus, system, and method are disclosed for determining prefetch data. A start module communicates a start of a target software process to a storage device. A learning module learns data blocks accessed for the target software process. In one embodiment, a prefetch module prefetches the learned data blocks in response to the start of the target software process. An end module communicates the end of the target software process to the storage device. In one embodiment, the prefetch module terminates prefetching data blocks and the learning module terminates learning the data blocks accessed for the target software process in response to the end module's communication of the end of the target software process.

Abstract: A method for resource management of a data processing system is described herein. According to one embodiment, a token is periodically pushed into a memory usage queue, where the token includes a timestamp indicating time entering the memory usage queue. The memory usage queue stores a plurality of memory page identifiers (IDs) identifying a plurality of memory pages currently allocated to a plurality of programs running within the data processing system. In response to a request to reduce memory usage, a token is popped from the memory usage queue. A timestamp of the popped token is then compared with current time to determine whether a memory usage reduction action should be performed.

Abstract: A method begins by a dispersed storage (DS) processing module monitoring processing status of a plurality of pending dispersed storage network (DSN) access requests, where less than a desired number of DS units have favorably responded to a set of access requests. The method continues with the DS processing module interpreting the processing status of the plurality of pending DSN access requests to detect a processing anomaly. The method continues with the DS processing module reprioritizing further processing of at least one of the plurality of pending DSN access requests having the processing anomaly and another one or more of the plurality of pending DSN access requests. The method continues with the DS processing module sending notice of the reprioritized further processing to one or more DS units.

Abstract: Information system, including: first and second storage apparatuses connected to a host computer and including volumes designated by a common volume identifier, but being accessible via differing paths of differing priorities. A failure detection storage apparatus connected to the storage apparatuses includes a third volume. Any I/O request designating the common volume identifier, is first sent to the first volume though the first access path, but upon error is then sent to the second volume thorough the second access path. The first or second storage apparatus detecting failure stores, in the third volume, a failure information flag. Upon receiving an I/O request through the second access path, the second storage apparatus determines whether the failure information flag is stored in the third volume, and sends an error reply of the I/O request to the host computer if the failure information flag is stored in the third volume.

Abstract: A method for caching data in a storage medium implementing tiered data structures may include storing a first portion of critical data at the instruction of a storage control module. The first portion of critical data may be separated into data having different priority levels based upon at least one data utilization characteristic associated with a file system implemented by the storage control module. The method may also include storing a second portion of data at the instruction of the storage control module. The second storage medium may have at least one performance, reliability, or security characteristic different from the first storage medium.

Abstract: A memory hub includes a local queue that stores local memory responses, a bypass path that passes downstream memory responses, and a buffered queue coupled to the bypass path that stores downstream memory responses from the bypass path. A multiplexer is coupled to the local queue, buffered queue, and the bypass path and outputs responses from a selected one of the queues or the bypass path responsive to a control signal. Arbitration control logic is coupled to the multiplexer and the queues and develops the control signal to control the response output by the multiplexer.

Abstract: A file server has a conversion table that stores therein, in a corresponding manner, logical addresses specified by a higher-level layer and physical addresses specified by a disk driver that are address information indicative of a storage area in a disk device. The file server accesses the disk device with a storage area indicated by a physical address as an access destination and counts up the number of access requests to each storage area in a given period of time for each of the logical addresses. The file server then updates the conversion table such that the physical addresses are lined up in a descending order of the logical addresses of a higher number of the access requests counted. Thereafter, the file server changes storage areas of data stored in the storage device based on the conversion table updated.

Abstract: A method, in one embodiment, can include allowing storage allocation of data of a file system within an object based storage system. Furthermore, the method can include determining if storage allocation usage for the file system is below a threshold. If the storage allocation usage for the file system is not below the threshold, a client is requested to flush its dirty data associated with the file system. After requesting a client flush, the method can include determining the storage allocation usage for the file system. In addition, the method can include determining periodically if the storage allocation usage has reached a quota. If the quota is reached, the quota is enforced for the data of the file system.

Abstract: A method (1400) of storage access scheduling for a memory device for a workload of different priority access requests including access requests having a real-time priority. The method includes characterizing the memory device (1402) including determining a balanced number (N) of concurrent access requests associated with a concurrent access maximum throughput associated with the memory device. The method also includes characterizing the workload (1404). The method also includes receiving a real-time access request (1406) associated with an access request storage location value. The method also includes processing the real-time access request (1408), utilizing a processor, based on the access request storage location value and the values obtained from characterizing the memory device and the workload.

Abstract: A method and system for dynamic distributed data caching is presented. The method includes establishing a cache community of members for data storage. A request for data at a particular member of the cache community is generated. A cache location in the cache community where the data would be located is determined. A determination is made as to whether the data is stored at the cache location. The data is requested from a source of the data in response to the data not being cached at the cache location. A determination is made as to whether the source is currently unavailable to provide the data. The data is continuously requested from the source while waiting for the source to become available. The particular member is allowed to request other data while waiting for data to become available from the source.

Abstract: Systems, methods and devices for management of instances of virtual memory components for storing computer readable information for use by at least one first computing device, the system comprising at least one physical computing device, each physical computing device being communicatively coupled over a network and comprising: a physical memory component, a computing processor component, an operating system, a virtual machine monitor, and virtual memory storage appliances; at least one of the virtual memory storage appliances being configured to (a) accept memory instructions from the at least one first computing device, (b) instantiate instances of at least one virtual memory component, (c) allocate memory resources from at least one physical memory component for use by any one of the least one virtual memory components, optionally according to a pre-defined policy; and (d) implement memory instructions on the at least one physical memory component.

Abstract: Requests from a plurality of different agents (10) are passed to a request handler via a request concentrator. In front of the request concentrator the requests are queued in a plurality of queues (12). A first one of the agents is configured to issue a priority changing command with a defined position relative to pending requests issued by the first one of the agents (10) to the first one of the queues (12). An arbiter (16), makes successive selections selecting queues (12) from which the request concentrator (14) will pass requests to the request handler (18), based on relative priorities assigned to the queues (12). The arbiter (16) responds to the priority changing command by changing the priority of the first one of the queues (12), selectively for a duration while the pending requests up to the defined position are in the first one of the queues (12). Different queues may be provided for read and write requests from the first one of the agents.

Abstract: Various systems and methods for performing tiering-aware data defragmentation. One method can involve receiving tiering information from a storage device that comprises multiple tiers. The information specifies a tiering attribute and tiering attribute value for the tiers. The method involves establishing zones that have zone attribute values corresponding to the received tiering attribute values. The method then involves storing a given block in a particular zone in response to detecting that a block attribute value of the block corresponds to a zone attribute value for the zone.

Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.

Abstract: A priority control register 104 dynamically controls the internal transition state based on the issuability state of a memory request obtained in the memory request issuability signal generation unit 106 and retaining state of the memory request in the REQ_BUF 102 obtained by each of determination circuits 105 #2 through #5. Thus, the jump control of the priorities corresponding to the access regulation of the DRAM module 109 can be realized.

Abstract: An access control apparatus which establishes a connection based on connection establishment requests from connected devices and controls accesses to a connection target device. The access control apparatus includes a connection information managing unit which manages connect wait conditions to the connection target device of the connected devices based on criterion information in a connection request transmitted from the connected devices and determination for selecting one connected device from the connected devices. The access control apparatus includes a selecting unit which selects one of the connected devices which has a delay tendency related to connection based on adjustment information which is set in accordance with the connect wait conditions of the connected devices and increases a delay tendency in connection of the connected device, and a determining unit which determines the connected device selected by the selecting unit as one to be connected to the connection target device.

Abstract: A computer-implemented method that includes receiving a plurality of stores in a store queue, via a processor, comparing a fetch request against the store queue to search for a target store having a same memory address as the fetch request, determining whether the target store is ahead of the fetch request in a same pipeline, and processing the fetch request when it is determined that the target store is ahead of the fetch request.

Abstract: A data storage device accepts queued read and write commands that have deadlines. The queued read and write commands are requests to access the data storage device. The deadlines of the queued read and write commands can be advisory deadlines or mandatory deadlines.

Abstract: A proactive, resilient and self-tuning memory management system and method that result in actual and perceived performance improvements in memory management, by loading and maintaining data that is likely to be needed into memory, before the data is actually needed. The system includes mechanisms directed towards historical memory usage monitoring, memory usage analysis, refreshing memory with highly-valued (e.g., highly utilized) pages, I/O pre-fetching efficiency, and aggressive disk management. Based on the memory usage information, pages are prioritized with relative values, and mechanisms work to pre-fetch and/or maintain the more valuable pages in memory. Pages are pre-fetched and maintained in a prioritized standby page set that includes a number of subsets, by which more valuable pages remain in memory over less valuable pages. Valuable data that is paged out may be automatically brought back, in a resilient manner.

Abstract: A method and system for preloading data is provided. Resources are preloaded on a client before they are needed by an application. Application hints and static resources lists may be used to indicate resources are needed. The application may begin execution before receiving all of the resources associated with the application. Preloading may be done during execution of an application, or when the application is not executing. Preloading allows an application to run smoothly without consuming more resources than are needed by an application. A prediction graph may be generated that is used in predicting the resources that are likely to be needed by the application. An analyzer may also be used to simulate the system and adjust parameters used in creating the prediction graph.

Abstract: Techniques are disclosed relating to maximizing utilization of memory systems within power constraints of the memory systems. In one embodiment, an integrated circuit may include multiple memory controllers and an arbitration unit. Each memory controller may be configured to generate requests to perform memory operations on one or more portions of memory. The arbitration unit may be configured to grant no more than a specified number of requests during a time window TW. In some embodiments, a voltage converter that supplies power to the memory system may be configured to supply power to perform no more than the specified number of requests during the time window TW. The arbitration unit may thus be used, in some embodiments, to ensure that the greatest possible number of the specified number of memory requests are granted during a given time window TW (without exceeding the specified number).

Abstract: There is provided a content reproduction apparatus including a reproduction request receiving unit that receives from a first external device conforming to a first communication standard a request to reproduce content data selected by the first external device, a content data obtaining unit that obtains from a second external device conforming to the first communication standard, which stores the content data selected by the first external device, the content data in response to the received request, a content reproduction unit that reproduces the obtained content data, and a data converting unit that converts data which can be transmitted according to the first communication standard into data which can be transmitted according to a second communication standard different than the first communication standard.

Abstract: A control method of a virtual memory is adapted for using in a computer. The control method includes the following steps. First, a plurality of application programs executed in the computer are monitored. Second, the application programs are compared with at least a predetermined program, respectively. Third, the virtual memory of a solid state disk (SSD) is controlled to be turned on or turned off according to a comparing result. Herein, the virtual memory of the SSD is controlled to be turned on or turned off to enhance both lifetime of the SSD and operation efficiency of the computer.

Abstract: A generation section periodically generates access frequency information for identifying an access frequency of each data item according to a status of write access of the data item transmitted from a host device to a storage device. Whenever access frequency information is generated by the generation section, a determination section determines whether to write data saved in a hard disk into the storage medium, or to hold a saved state of the data. A write section writes data into the storage device according to determination by the determination section.

Abstract: A method for measuring latencies caused by processing performed within a common resource is provided. A current latency value representing a time of residency of an IO request in a queue prior to receipt of acknowledgment from the common resource of completion of the IO request is received from a device comprising the queue, which maintains entries for IO requests that have been dispatched to and are pending at the common resource. An average latency value is calculated based in part on the current latency value. An adjusted capacity size for the queue is calculated based in part on the average latency value and the queue's capacity is set to the adjusted capacity size. IO requests are held in a buffer if the queue's capacity is full to reduce the effect of an amount of work transmitted to the common resource on current latency values provided by the device.