Abstract: A more efficient technique is provided in an information processing apparatus which executes processing using pipelines. An information processing apparatus according to this invention includes a first pipeline, second pipeline, processing unit, and reorder unit. The first pipeline has a plurality of first nodes, and shifts first data held in a first node to a first node. The second pipeline has a plurality of second nodes respectively corresponding to the first nodes of the first pipeline, and shifts second data held in a second node to a second node. The processing unit executes data processing using the first data and the second data. The reorder unit holds one of the output second data based on attribute information of the second data output from the second pipeline, and outputs the held second data to the second pipeline.

Abstract: Solid state storage devices and methods for populating a hot memory block look-up table (HBLT) are disclosed. In one such method, an indication to an accessed page table or memory map of a non-volatile memory block is stored in the HBLT. If the page table or memory map is already present in the HBLT, the priority location of the page table or memory map is increased to the next priority location. If the page table or memory map is not already stored in the HBLT, the page table or memory map is stored in the HBLT at some priority location, such as the mid-point, and the priority location is incremented with each subsequent access to that page table or memory map.

Abstract: A storage system having a plurality of storage devices including a first type storage device and a second type storage device, a reliability attribute and/or a performance attribute of the first type storage device being different from a reliability attribute and/or a performance attribute of the second type storage device. The storage system also has a control unit and managing a plurality of virtual volumes. If necessary, a storage area allocated to a first portion of a virtual volume of the plurality of virtual volumes is changed from a first type storage area of the plurality of first type storage areas to a second type storage area of the plurality of second type storage areas while another first type storage area of the plurality of first type storage areas is allocated to a second portion of the virtual volume.

Abstract: A storage device includes a memory; and a processor coupled to the memory, wherein the processor executes a process comprising: calculating an upper limit value of the number of input/output processings determined based on priority set to an information processing device, a port that is an interface between the information processing device and the storage device and a memory device of the storage device; scheduling an execution order of input/output processings based on the number of input/output processings received from the information processing device and the calculated upper limit value; and executing the input/output processings in the scheduled execution order.

Abstract: Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detected, and the received order of the memory access requests is rearranged to avoid or minimize the conflicts or delays and to optimize the flow of data to and from the memory data bus. The memory access requests are executed in the reordered sequence, while the originally received order of the requests is tracked. After execution, data read from the memory device by the execution of the read-type memory access requests are transferred to the respective requestors in the order in which the read requests were originally received.

Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.

Abstract: An information processing apparatus includes a calculator configured to perform a calculation, a plurality of system boards, each of the plurality of system boards including a first storage unit that stores a first program of a first type, the first program being to be used to operate the calculator, a preliminary board including a plurality of second storage units, at least one of the plurality of second storage units storing a second program of a second type, the second program corresponding to the first programs, and a controller configured to compare any one of the first types of the first programs with the second type of the second program and to write, when any one of the first types does not match the second type, the first program of the any one of the first types into the second storage unit.

Abstract: Provided are a computer program product, system, and method for using an attribute of a write request to determine where to cache data in a storage system having multiple caches including non-volatile storage cache in a sequential access storage device. Received modified tracks are cached in the non-volatile storage device integrated with the sequential access storage device in response to determining to cache the modified tracks. A write request having modified tracks is received. A determination is made as to whether an attribute of the received write request satisfies a condition. The received modified tracks for the write request are cached in the non-volatile storage device in response to determining that the determined attribute does not satisfy the condition. A destage request is added to a request queue for the received write request having the determined attribute not satisfying the condition.

Abstract: A system includes a source storage device, a target storage device, a host coupled to the source storage device and the target storage device, and a first migration device coupled to the source storage device and the target storage device. The first migration device includes a first virtual storage device. The first migration device is configured to migrate data from the source storage device to the target storage device, and the first virtual storage device is configured to receive write access requests for the data from the host during the data migration and send the access request to the source storage device and target storage device.

Abstract: File system disaster recovery techniques provide automated monitoring, failure detection and multi-step failover from a primary designated target to one of a designated group of secondary designated targets. Secondary designated targets may be prioritized so that failover occurs in a prescribed sequence. Replication of information between the primary designated target and the secondary designated targets allows failover in a manner that maximizes continuity of operation. In addition, user-specified actions may be initiated on failure detection and/or on failover operations and/or on failback operations.

Abstract: Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems are disclosed. A heterogeneous memory system is comprised of a plurality of homogeneous memories that can be accessed for a given memory access request. Each homogeneous memory has particular power and performance characteristics. In this regard, a memory access request can be advantageously routed to one of the homogeneous memories in the heterogeneous memory system based on the memory access request, and power and/or performance considerations. The heterogeneous memory access request policies may be predefined or determined dynamically based on key operational parameters, such as read/write type, frequency of page hits, and memory traffic, as non-limiting examples. In this manner, memory access request times can be optimized to be reduced without the need to make tradeoffs associated with only having one memory type available for storage.

Abstract: Methods, articles of manufacture, and apparatus are disclosed to manage workload memory allocation. An example method includes identifying a primary memory and a secondary memory associated with a platform, the secondary memory having first performance metrics different from second performance metrics of the primary memory, identifying access metrics associated with a plurality of data elements invoked by a workload during execution on the platform, prioritizing a list of the plurality of data elements based on the access metrics associated with corresponding ones of the plurality of data elements, and reallocating a first one of the plurality of data elements from the primary memory to the secondary memory based on the priority of the first one of the plurality of memory elements.

Abstract: Memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard. If the memory manager detects the computing device is experiencing memory pressure, the memory manager may address the memory pressure by selecting memory space available for discard and discarding the content of the memory space. Before a process reuses content made available for discard, the process may notify the memory manager of the intent to reuse and, in response, receive empty memory and an indication that the content was discarded or receive an indication that the content is still available for use.

Abstract: Embodiments of the present invention relate to a method, apparatus and computer product for managing memory space. In one aspect of the present invention, there is provided a method for managing memory space that is organized into pages, the pages being divided into a plurality of page sets, each page set being associated with one of a plurality of upper-layer systems, by: performing state monitoring to the plurality of upper-layer systems to assign priorities to the plurality of upper-layer systems; and determining an order of releasing the pages of the memory space based on the priorities of the plurality of upper-layer systems with the page sets as units. Other aspects and embodiments of invention are also disclosed.

Abstract: A crossbar switch device for a processor block ASIC core and a method for a flush-posted-write(s)-before-read mode thereof are described. Operation for the flush-posted-write(s)-before-read mode is set in a first processor block interface coupled to programmable logic fabric. At least one write command is sent from a transaction initiating device instantiated using the programmable logic fabric to the first processor block interface. The at least one write command is posted in the first processor block interface. At least one write command received is stored in a command queue of the crossbar switch device. A read command initiated by a microprocessor is sent to the crossbar switch device. The at least one write command has an address overlap with the read command with respect to a destination target. The read command is temporarily blocked in the crossbar switch device until a command phase of the at least one write command is completed.

Abstract: A modular system for acquiring biometric data includes a plurality of data acquisition modules configured to sample biometric data from at least one respective input channel at a data acquisition rate. A representation of the sampled biometric data is stored in memory of each of the plurality of data acquisition modules. A central control system is in communication with each of the plurality of data acquisition modules through a bus. The central control system is configured to collect data asynchronously, via the bus, from the memory of the plurality of data acquisition modules according to a relative fullness of the memory of the plurality of data acquisition modules.

Abstract: A set of physical input/output adapters (PIOAs) is configured such that each PIOAs in the set of PIOAs is a functional equivalent of another PIOAs in the set of PIOAs. A utilization of each PIOA in the set of PIOAs is measured. A number of PIOAs needed to service a workload is determined. A first subset of PIOAs from the set of PIOAs is powered down if the number of PIOAs needed to service the workload is smaller than a number of operational PIOAs. The I/O operations associated with the first subset of PIOAs are transferred to a second subset of PIOAs remaining operational in the set of PIOAs.

Abstract: Apparatus, computer readable medium, and method of servicing memory requests are presented. A first plurality of memory requests are associated together, wherein each of the first plurality of memory requests is generated by a corresponding one of a first plurality of processors, and wherein each of the first plurality of processors is executing a first same instruction. A second plurality of memory requests are associated together, wherein each of the second plurality of memory requests is generated by a corresponding one of a second plurality of processors, and wherein each of the second plurality of processors is executing a second same instruction. A determination is made to service the first plurality of memory requests before the second plurality of memory requests and the first plurality of memory requests is serviced before the second plurality of memory requests.

Abstract: Embodiments relate to sequential location accesses in an active memory device that includes memory and a processing element. An aspect includes a method for sequential location accesses that includes receiving from the memory a first group of data values associated with a queue entry at the processing element. A tag value associated with the queue entry and specifying a position from which to extract a first subset of the data values is read. The queue entry is populated with the first subset of the data values starting at the position specified by the tag value. The processing element determines whether a second subset of the data values in the first group of data values is associated with a subsequent queue entry, and populates a portion of the subsequent queue entry with the second subset of the data values.

Abstract: A primary storage controller is configured to communicate with a secondary storage controller via a system data mover. In response to receiving a command to perform a point in time copy of a source volume of the primary storage controller to a target volume of the primary storage controller, a determination is made as to whether the target volume of the primary storage controller is a source for an asynchronous data replication operation, initiated by the system data mover, between the primary storage controller and the secondary storage controller. In response to determining that the target volume of the primary storage controller is the source for the asynchronous data replication operation, initiated by the system data mover, the point in time copy of the source volume of the primary storage controller to the target volume of the primary storage controller is performed.

Abstract: Among other things, one or more techniques and/or systems are provided for storing data within a hybrid storage aggregate comprising a solid state storage tier and a non-solid state storage tier. In particular, frequently accessed data and/or randomly accessed data may be identified and stored within the solid state storage tier to mitigate mechanical latency that may arise from accessing such data from the non-solid state storage tier. Infrequently accessed data and/or sequentially accessed data may be identified and stored within the non-solid state storage tier to utilize cost effective storage space while mitigating undesirable mechanical latency associated with accessing such data.

Abstract: A primary storage controller is configured to communicate with a secondary storage controller via a system data mover. In response to receiving a command to perform a point in time copy of a source volume of the primary storage controller to a target volume of the primary storage controller, a determination is made as to whether the target volume of the primary storage controller is a source for an asynchronous data replication operation, initiated by the system data mover, between the primary storage controller and the secondary storage controller. In response to determining that the target volume of the primary storage controller is the source for the asynchronous data replication operation, initiated by the system data mover, the point in time copy of the source volume of the primary storage controller to the target volume of the primary storage controller is performed.

Abstract: To reduce the number of data copies between volume pools by preventing occurrence of unevenness of resource usage between the pools, provided is a computer system including: storage apparatus; and host computer coupled to the storage apparatus, the storage apparatus including physical storage device, the storage apparatus holding information associating virtual volumes and pools each including real storage areas of the physical storage device, the storage apparatus allocating, to the virtual volume of a write destination designated by the host computer, the real storage areas included in each of the plurality of pools corresponding to the virtual volume of the write destination, and storing the data therein, the computer system being configured to: determine, based on the information held by the storage apparatus, orders of priority of the volumes of the write destination by the host computers; and hold the determined orders of priority.

Abstract: In a computer system supporting execution of virtualization software and at least one instance of virtual system hardware, an interface is provided into the virtualization software to allow a program to directly define the access characteristics of its program data stored in physical memory. The technique includes providing data identifying memory pages and their access characteristics to the virtualization software which then derives the memory access characteristics from the specified data. Optionally, the program may also specify a pre-defined function to be performed upon the occurrence of a fault associated with access to an identified memory page. In this manner, programs operating both internal and external to the virtualization software can protect his memory pages, without intermediation by the operating system software.

Abstract: A method and system for improving access to network content are described. Aspects of the disclosure minimize the delay between a navigation event and a network response by prerendering the next navigation event. For example, the method and system may predict a likely next uniform resource locator during web browsing to preemptively request content from the network before the user selects the corresponding link on a web page. The methods and systems describe a variety of manners for prerendering content and managing and configuring prerendering operations.

Abstract: A computing device employs a cooperative memory management technique to dynamically balance memory resources between host and guest systems running therein. According to this cooperative memory management technique, memory that is allocated to the guest system is dynamically adjusted up and down according to a fairness policy that takes into account various factors including the relative amount of readily freeable memory resources in the host and guest systems and the relative amount of memory allocated to hidden applications in the host and guest systems.

Abstract: Some embodiments of the present invention provide a system that avoids deadlock while attempting to acquire store-marks on cache lines. During operation, the system keeps track of store-mark requests that arise during execution of a thread, wherein a store-mark on a cache line indicates that one or more associated store buffer entries are waiting to be committed to the cache line. In this system, store-mark requests are processed in a pipelined manner, which allows a store-mark request to be initiated before preceding store-mark requests for the same thread complete. Next, if a store-mark request fails, within a bounded amount of time, the system removes or prevents store-marks associated with younger store-mark requests for the same thread, thereby avoiding a potential deadlock that can arise when one or more other threads attempt to store-mark the same cache lines.

Abstract: In one embodiment, a method receives current latency values from a plurality of host computers where a current latency value is calculated by a respective host computer based on an amount of time spent in the respective host computer's issue queue by an IO request most recently removed from the issue queue of the respective host computer. The issue queue of the respective host computer is used to transmit IO requests from the respective host computer to a storage system. The method then calculates a combined average latency value based on the current latency values and sends the combined average latency value to the plurality of host computers. Each respective host computer adjusts a size of the respective host computer's issue queue based on the combined average latency value, and the size controls a number of IO requests that are added to the respective host computer's issue queue.

Abstract: A storage section controlling apparatus includes a queuing section adapted to retain a processing order of write requests and readout requests from a data processing apparatus to plural storage sections to, and a processing order controlling section adapted to change, where a readout request for a target region of a duplexing process of a second storage section of the plural storage sections by a duplexing controlling section is issued from the data processing apparatus and a write request for a target region of at least one first storage section of the plural storage sections of a copying source corresponding to the target region of the readout request exists later than a processing turn of the readout request in a processing order in the queuing section, the processing turn of the readout request in the processing order so as to be later than the writing request in the processing order.

Abstract: An information processing device includes a storage device that stores information, and a controller that adjusts a consumption of read time of reading information to be read per unit data amount according to the priority of the information to be read from the storage device and a permitted read time during which read of information from the storage device is permitted. The permitted read time varies according to the processing time of another control different from the control of the read.

Abstract: Requests from a plurality of different agents (10) are passed to a request handler via a request concentrator. In front of the request concentrator the requests are queued in a plurality of queues (12). A first one of the agents is configured to issue a priority changing command with a defined position relative to pending requests issued by the first one of the agents (10) to the first one of the queues (12). An arbiter (16), makes successive selections selecting queues (12) from which the request concentrator (14) will pass requests to the request handler (18), based on relative priorities assigned to the queues (12). The arbiter (16) responds to the priority changing command by changing the priority of the first one of the queues (12), selectively for a duration while the pending requests up to the defined position are in the first one of the queues (12). Different queues may be provided for read and write requests from the first one of the agents.

Abstract: Embodiments of the invention provide a storage subsystem comprising a non-volatile solid-state memory array and a system operation module for managing memory operations. The system operation module is configured to store system operation data in a data structure that includes linked lists for storing system operation data, with at least some lists including entries referencing blocks in the solid-state memory array belonging to a category. The system operation module is further configured to (1) move a particular entry from a first linked list to a second linked list when a block referenced by the particular entry in the first linked list has met a condition for being classified in a new category that is different from that of the blocks referenced by entries in the first linked list, and (2) update entries within the first and second linked lists so that the dependencies in the linked lists are maintained.

Abstract: Multiprocessor systems often share access to a centralized memory and experience conflicting access requests. An arbitration unit mediates priorities of requestor preferably ensuring both priority and fairness. In this invention upon an access conflict the arbitrator grants access to one requestor having the highest priority level and stalls other conflicting requestors. If plural requestors have the same priority level, the arbiter grants access to one and stalls the others. The arbiter then adjusts the priority levels of the requestors. The priority of the requestor granted access is decreased by the number of stalled requestors. The stalled requestors have their priority levels increased by one. The arbitration decision is thus based on the stall history and the caused stall history of each requestor.

Abstract: A method manages a flash memory having a plurality of physical blocks. The blocks of the memory are addressed by logic block addresses which are converted into physical block addresses. In each block a deletion counter is run in which the number of deletions of the block is counted, and two regions having different types of flash chips are present. A first region contains single-level flash chips with a large maximum deletion frequency, and a second region contains multi-level flash chips with a lower maximum deletion frequency. When writing to the memory the address conversion of the logic addresses into physical addresses is carried out such that all blocks of the first region are written, when all blocks of the first region have been written and a further writing process is initiated, the block in the first region having the lowest deletion counter is copied into a blank block in the second region.

Abstract: In one embodiment, a configuration adviser provides configuration options for a multi-tiered storage system that includes a number of different storage tiers, each of which include storage devices of a particular storage type. Data access information for storage extents to be stored in the storage system are received. Resource information for available storage tiers in the storage system to place the storage extents on are also received. A cost incurred by the storage system for placing each of the storage extents on each of the storage tiers is determined. Each storage extent is assigned to a particular one of the storage tiers that would incur the lowest cost to the storage system for storing the storage extent. For each storage tier, a minimum number of storage devices are selected, within the assigned storage tier, that would satisfy data access and capacity requirements for all storage extents assigned to that tier.

Abstract: A computer includes a memory that stores data, a cache memory that stores a copy of the data, a directory storage unit that stores directory information related to the data and includes information indicating that the data is copied to the cache memory, a directory cache storage unit that stores a copy of the directory information stored in the directory storage unit, and a control unit that controls storage of data in the directory cache storage unit, manages the data copied from the memory to the cache memory by dividing the data into an exclusive form and a shared form, and sets a priority of storage of the directory information related to the data fetched in the exclusive form in the directory cache storage unit higher than a priority of storage of the directory information related to the data fetched in the shared form in the directory cache storage unit.

Abstract: A storage subsystem capable of processing time-critical control commands while suppressing deterioration of the system performance to a minimum. When various commands are received in a multiplex manner via the same port from plural host devices, the channel adapter of the storage subsystem extracts commands of a first kind from the received commands. Then, the adapter executes the extracted commands of the first kind with high priority within a given unit time until a given number of guaranteed activations is reached. At the same time, commands of a second kind are enqueued in a queue of commands. After the commands of the first kind are executed as many as the number of guaranteed activations, the commands of the second kind are executed in the unit time.

Abstract: An image processing apparatus for managing a memory device having a plurality of storage areas including a storage area storing out-of-use information and a free area storing no information, the image processing apparatus comprises memory control unit adapted to determine whether or not there is a storage area storing the out-of-use information based on a request for storing information and determining the storage area storing the out-of-use information as an area for storing the information, in a case where the storage area exists; and information writing unit adapted to overwrite generated information to the storage area determined by the memory control unit.

Abstract: An apparatus and method are described for performing history-based prefetching. For example a method according to one embodiment comprises: determining if a previous access signature exists in memory for a memory page associated with a current stream; if the previous access signature exists, reading the previous access signature from memory; and issuing prefetch operations using the previous access signature.

Abstract: A prefetch controller implements an upgrade when a real read access request hits the same memory bank and memory address as a previous prefetch request. In response per-memory bank logic promotes the priority of the prefetch request to that of a read request. If the prefetch request is still waiting to win arbitration, this upgrade in priority increases the likelihood of gaining access generally reducing the latency. If the prefetch request had already gained access through arbitration, the upgrade has no effect. This thus generally reduces the latency in completion of a high priority real request when a low priority speculative prefetch was made to the same address.

Abstract: A tier identification (TID) is to indicate a characteristic of a memory region associated with a virtual address in a tiered memory system. A thread may be serviced according to a first path based on the TID indicating a first characteristic. The thread may be serviced according to a second path based on the TID indicating a second characteristic.

Abstract: Arbitrating memory access between a central processing unit CPU and a peripheral device to main memory. The memory access to and from the main memory by the CPU and memory access to and from the main memory by the peripheral device is prioritized respectively according to a CPU priority level and a peripheral device priority level. An arbitration module is provided externally to the CPU, to the peripheral device and to the memory controller. The arbitration module receives the peripheral device priority level. When the CPU priority level and the peripheral device priority level are both set at the highest available priority level, the arbitration module outputs to the memory controller a new CPU priority level less than the highest available priority level.

Abstract: Accesses to a memory divided into a plurality of units of operation are controlled. First and second units of operation from among the plurality of units of operation constitute a memory mirror. A reception circuit receives a plurality of read requests including bank identification information corresponding to both a first bank included in a first unit of operation and a second bank included in a second unit of operation, respectively. A determination circuit determines an access target of each read access so that the plurality of read accesses based on the plurality of read requests are made to the first and second units of operation alternately. The control circuit controls each read request so that each read access is made to a unit of operation determined as the access target.

Abstract: According to an aspect of the present invention, provided is a storage control device including a processor. The processor monitors a load value of a first storage device or a second storage device during copy processing in which a copy of data stored in the first storage device is stored in the second storage device. The processor controls, in a case where the load value exceeds a predetermined threshold, the first storage device and the second storage device so that input/output processing to/from the second storage device is executed with priority over the copy processing.

Abstract: A method for controlling memory refresh operations in dynamic random access memories. The method includes determining a count of deferred memory refresh operations for a first memory rank. Responsive to the count approaching a high priority threshold, issuing an early high priority refresh notification for the first memory rank, which indicates the pre-determined time for performing a high priority memory refresh operation at the first memory rank. Responsive to the early high priority refresh notification, the behavior of a read reorder queue is dynamically modified to give priority scheduling to at least one read command targeting the first memory rank, and one or more of the at least one read command is executed on the first memory rank according to the priority scheduling. Priority scheduling removes these commands from the re-order queue before the refresh operation is initiated at the first memory rank.

Abstract: A method of communicating over a bus is disclosed. The bus includes a write address channel, a write channel, and a read address channel. The method includes sending an address from a sending device to a receiving device via the write address channel. The method further includes concurrently sending a portion of a payload to the receiving device via the write channel and another portion of the payload to the receiving device via the read address channel. When sending multiple sequential portions of the payload via the bus concurrently, the sending device is configured to give data ordering preference to the write channel over the read address channel by sending a first sequential portion of the multiple sequential portions via the write channel and sending a subsequent sequential portion of the multiple sequential portions via the read address channel.

Abstract: According to an aspect of the embodiment, an FP includes a plurality of entries which holds requests to be processed, and each of the plurality of entries includes a requested flag indicating that data transfer is once requested. An FP-TOQ holds information indicating an entry holding the oldest request. A data transfer request prevention determination circuit checks the requested flag of a request to be processed and the FP-TOQ, and when a transfer request of data as a target of the request to be processed has already been issued and the entry holding the request to be processed is not the entry indicated by the FP-TOQ, transmits a signal which prevents the transfer request of the data to a data transfer request control circuit. Even when a cache miss occurs in a primary cache RAM, the data transfer request control circuit does not issue a data transfer request when the signal which prevents the transfer request is received.

Abstract: A tracking buffer apparatus is disclosed. A tracking buffer apparatus includes lookup logic configured to locate entries having a transaction identifier corresponding to a received request. The lookup logic is configured to determine which of the entries having the same transaction identifier has a highest priority and thus cause a corresponding entry from a data buffer to be provided. When information is written into the tracking buffer, write logic writes a corresponding transaction identifier to the first free entry. The write logic also writes priority information in the entry based on other entries having the same transaction identifier. The entry currently being written may be assigned a lower priority than all other entries having the same transaction identifier. The priority information for entries having a common transaction identifier with one currently being read are updated responsive to the read operation.

Abstract: A method for writing updated data into a flash memory module having a plurality of physical pages is provided, wherein each physical page is the smallest writing unit of the flash memory module. The method includes partitioning a physical page into storage segments and configuring a state mark for each storage segment, wherein the state marks indicate the validity of data stored in the storage segments. The method also includes writing the updated data into at least one of the storage segments and changing the state mark corresponding to the storage segment containing the updated data, wherein the state mark corresponding to the storage segment containing the updated data indicates a valid state, and the state marks corresponding to the other storage segments of the physical page not containing the updated data indicate an invalid state. Thereby, the time for writing data into a physical page is effectively shortened.

Abstract: A data access device provided with a sequence storage unit which stores in advance a sequence for accessing the data contained in each of the multiple data units stored in a data storage section. The data access device receives and stores in the data access request storage section multiple data access requests for any of the multiple stored data units, determines an execution sequence for the multiple stored data access requests that corresponds to the aforementioned sequence stored in the sequence storage unit, locks the data units to be accessed as per the data access requests, sequentially implements the data access requests in the determined execution sequence, and removes all the locks after implementing all of the stored data access requests.