Access Limiting Patents (Class 711/163)
  • Patent number: 10091241
    Abstract: A method of making a “zero knowledge” connection between a computer (2) and an electronic unit (5). At the start of the method, the configuration unit (1) is connected with the computer (2), and a web server is initiated in the configuration unit (1) via the trusted execution environment. A secure network connection is made to a server (3) by the configuration unit (1) and, via the network connection, the items of information required for connection with the electronic units, to which a connection can be made, are synchronized with the trusted execution environment. After synchronization occurs, an electronic unit (5) is selected by the web server via an input of the computer (2), to which electronic unit (5) a connection is made via the trusted execution environment using the stored, synchronized items of information, and via the web server prescribed menu-driven maintenance or configuration steps can be executed.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: October 2, 2018
    Assignee: SKIDATA AG
    Inventor: York Keyser
  • Patent number: 10075446
    Abstract: Embodiments described herein provide systems and methods to streamline the mechanism by which data users access differently regulated data through the use of one or more integrated identifiers. The integrated identifiers lessen or eliminate the need to separately maintain one set of identifiers for regulated data and another set for non-regulated data. The methods and systems may be applicable in various credit and healthcare contexts where regulations over data use are prevalent. In one or more embodiments, a data user receives a unique integrated identifier for each of the data user's current or prospective customers, and the integrated identifiers can be used to persistently identify and track the customers over time and across applications that access regulated and/or non-regulated data. In the healthcare context, a healthcare provider may utilize a patient ID as the integrated identifier. To protect privacy, the integrated identifier may not include social security numbers or birthdates.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: September 11, 2018
    Assignee: EXPERIAN MARKETING SOLUTIONS, INC.
    Inventors: Helen McMillan, John Lawrence Skurtovich, Anita Kress, Timothy Sumida, Michael Charles McVey
  • Patent number: 10073777
    Abstract: A data processing apparatus has a memory attribute unit having storage regions for storing attribute data for controlling access to a corresponding memory address range by processing circuitry. In response to a target memory address, the processing circuitry can perform a region identifying operation to output a region identifying value identifying which of the storage regions of the attribute unit corresponds to the target memory address. The region identifying value is made available to at least some software executed by the data processing apparatus. This can be useful for quickly checking access permissions of a range of addresses or for determining how to update the memory attribute unit.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: September 11, 2018
    Assignee: ARM Limited
    Inventor: Thomas Christopher Grocutt
  • Patent number: 10073734
    Abstract: An apparatus comprising a memory and a controller. The memory may be configured to store data. The controller may process a plurality of input/output requests to read/write to/from the memory. The controller may generate read data by performing a hard-decision decode on a codeword received from the memory. If the hard-decision decode fails, the controller may enter an error-recovery process comprising a plurality of recovery procedures. At least one of the recovery procedures may apply an inter-cell interference cancellation technique. The error-recovery process may (a) determine parameters for a soft-decision decode by performing one of the recovery procedures on the codeword, (b) execute the soft-decision decode using the parameters from the recovery procedure performed to generate the read data and (c) if the soft-decision decode fails, repeat (a) and (b) using a next one of the recovery procedures.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: September 11, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Erich F. Haratsch, Jeremy Werner, Zhengang Chen, Earl T. Cohen, Yunxiang Wu, Ning Chen
  • Patent number: 10073793
    Abstract: A data processor includes an access target with the address assigned to a memory space, an access subject that gains access to the access target while specifying address, identifier, and access type, and a memory protection resource including an associative memory to perform an access control. The memory protection resource includes a plurality of entries, each including a region setting unit, an identifier determination information unit, and an attribute setting unit. When the address specified by the access subject at the access is included in the region set in the region setting unit in the entry, the identifier agrees with at least one of the identifiers specified according to the identifier determination information, and the specified access type agrees with the access type set in the attribute setting unit, the memory protection resource permits the access.
    Type: Grant
    Filed: August 20, 2016
    Date of Patent: September 11, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Adachi, Yoichi Yuyama
  • Patent number: 10068110
    Abstract: A semiconductor device includes a first processing unit configured to perform a calculation by using data stored in a memory; and a memory path controller configured to communicate with the first processing unit and control the memory for the first processing unit to perform the calculation, wherein the memory path controller includes an address region control unit configured to divide an address space of the memory to include a secure address and a non-secure address and permit the first processing unit to access the secure address or the non-secure address, and a first content firewall unit connected with the address region control unit and configured to prevent the first processing unit from writing secure contents in the non-secure address.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: September 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woo-Hyung Chun, Min-Je Jun, Sim-Ji Lee, Eui-Cheol Lim, Seong-Min Jo, Sung-Min Hong
  • Patent number: 10048314
    Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: August 14, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Gary L. Swoboda, Robert A. McGowan
  • Patent number: 10049215
    Abstract: A method for providing malware protection in connection with processing circuitry including hardware resources and software resources managed by a primary operating system may include providing a trusted operating system to control access to a portion of a local storage area of the hardware resources. In this context, only the trusted operating system is configured to enable writing to the portion of the local storage area. The method may further include storing backup files for the primary operating system in the portion of the local storage area responsive to the trusted operating system granting access to write to the portion of the local storage area.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: August 14, 2018
    Assignee: The Johns Hopkins University
    Inventors: David C. Challener, Peter S. Kruus, Russell A. Fink, James F. Farlow
  • Patent number: 10043013
    Abstract: The disclosed computer-implemented method for detecting gadgets on computing devices may include (i) identifying, on a computing device, a process containing multiple modules, (ii) identifying, within the process, each module that does not implement a security protocol that randomizes, each time the module executes, a memory location of at least one portion of data accessed by the module, (iii) copying each module that does not implement the security protocol to a section of memory dedicated to security analyses, (iv) determining, based on detecting at least one gadget-specific characteristic within at least one copied module, that the process contains a gadget that is capable of being maliciously exploited, and then (v) performing a security action on the computing device to prevent the gadget from being maliciously exploited. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: August 7, 2018
    Assignee: Symantec Corporation
    Inventors: Peter Ferrie, Joseph Chen
  • Patent number: 10037287
    Abstract: A method of protecting software for embedded applications against unauthorized access. Software to be protected is loaded into a protected memory area. Access to the protected memory area is controlled by sentinel logic circuitry. The sentinel logic circuitry allows access to the protected memory area from only either within the protected memory area or from outside of the protected memory area but through a dedicated memory location within the protected memory area. The dedicated memory location then points to protected address locations within the protected memory area.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: July 31, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Johann Zipperer
  • Patent number: 10038444
    Abstract: A circuit includes combinational circuit and sequential circuit elements coupled thereto. The circuit includes a multiplexor coupled to the combinational and sequential circuit elements, and a system register is coupled to the multiplexor. At least one portion of the combinational and sequential circuit elements is configured to selectively switch to operate as a random access memory.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: July 31, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Salvatore Marco Rosselli, Daniele Mangano, Riccardo Condorelli
  • Patent number: 10033799
    Abstract: A data construct called a semcard is a semantic (meaning-based) software object including semantic meta-tags and meta-data that describes a target object or thing. A target object can be any type of digital or physical entity or identifier, or it can be tacit knowledge, such as ideas, concepts, processes or other data existing in a user's mind, provided that the user represents this knowledge in the semcard. A semcard embodies information about its own structure-rules, history, state, policies and goals regarding automation, display, access permissions, sharing and other operations of the semcard and any optional target object. It can also represent a semantic link between two semcards, or a semantically typed link or a standard Web hyperlink between a semcard and its referent target. A collection of semcards represents a knowledge network; single semcards, and knowledge networks, can be browsed, shared, searched, disseminated, manipulated, displayed, organized, and stored.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: July 24, 2018
    Assignee: ESSENTIAL PRODUCTS, INC.
    Inventors: Nova T. Spivack, Kristinn R. Thorisson
  • Patent number: 10031862
    Abstract: A memory protection unit including hardware registers for entering address tables, a configuration memory for storing the address tables, a preconfigured hardware logic for managing the configuration memory, a data connection between the configuration memory and the hardware logic for loading the hardware registers, a first interface for controlling the loading by a computing core, and a second interface for writing to the configuration memory by the computing core.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: July 24, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventors: Gunnar Piel, Nico Bannow, Simon Hufnagel, Jens Gladigau, Rakshith Amarnath
  • Patent number: 10027666
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating signed addresses. One of the methods includes receiving, by a component from a device, a plurality of first requests, each first request for a physical address and including a virtual address, determining, by the component, a first physical address using the virtual address, generating a first signature for the first physical address, and providing, to the device, a response that includes the first signature, receiving, from the device, a plurality of second requests, each second request for access to a second physical address and including a second signature, determining, by the component for each of the plurality of second requests, whether the second physical address is valid using the second signature, and for each second request for which the second physical address is determined to be valid, servicing the corresponding second request.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: July 17, 2018
    Assignee: Google LLC
    Inventor: Benjamin C. Serebrin
  • Patent number: 10001524
    Abstract: According to one embodiment, a semiconductor integrated circuit comprises: a tested block including a test control circuit; and a control circuit configured to output a first signal. The test control circuit performs a test of at least a first test pattern of the test patterns for the scan chain in accordance with the first signal during a first non-access state period of the tested block, and performs a test of at least a second test pattern following the first test pattern of the test patterns for the scan chain in accordance with the first signal during a second non-access state period of the tested block, and the test of the first test pattern and the test of the second test pattern are performed discontinuously.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: June 19, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenichi Anzou
  • Patent number: 10002652
    Abstract: Provided herein may be a memory system and a method of operating the same. A semiconductor memory device may include a write protect pin mode setting unit configured to set, depending on a parameter value stored therein, a write protect pin of the semiconductor memory device as any one of an input pin and an output pin and a control logic configured to output, when the write protect pin serves as the output pin, internal state information of the semiconductor memory device to an external device.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: June 19, 2018
    Assignee: SK Hynix Inc.
    Inventors: Jin Yong Seong, Gun Gi Song, Young Sang Ahn, Jae Won Cha
  • Patent number: 10002013
    Abstract: Techniques are described for facilitating sharing and reuse of executable software images between multiple execution environments. In at least some situations, the executable software images are virtual machine images (e.g., images that are bootable or otherwise loadable by a virtual machine in a particular virtualization environment, and that each include operating system software and/or software for one or more application programs, optionally along with one or more hard disks or other representations of stored data). The described techniques may include use of an image conversion tool that is configured to support interactions with multiple distinct types of source execution environments to extract executable software images from those environments, and to modify extracted software images for execution in one or more distinct types of destination execution environments, optionally as directed by one or more users via a GUI provided by the image conversion tool.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: June 19, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Avichai M. Lissack, Bashuman Deb
  • Patent number: 9996279
    Abstract: Various embodiments are directed to providing integrity protection for a system management mode. During initialization, a hash value of a system management mode control routine may be determined. Subsequently, during operation, the hash value may be compared to a hash value of a system management mode control routine to be executed. The system management mode control routine to be executed may be determined to be authentic if the hash values are the same.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: June 12, 2018
    Assignee: INTEL CORPORATION
    Inventors: Jorge E. Gonzalez Diaz, Juan Manuel Cruz Alcaraz
  • Patent number: 9990240
    Abstract: Disclosed is event processing a computing center, which may include receiving events from users of the computing center to be processed. Each received event may be stored in an event queue that is associated with a customer of the user. Events in an event queue may then be processed by an event processor that is associated with that event queue.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: June 5, 2018
    Assignee: SuccessFactors, Inc.
    Inventor: Wilko Dann
  • Patent number: 9973537
    Abstract: A method for updating security information is applied to a system including an information service provider and mobile devices. The information service provider includes a server and a database, in which the server provides security information to the mobile devices and each of the security information is related individually to a security code. The information service provider can transmit updated security information to the mobile devices in an active-push manner in communicative off-peak hours, and at the same time each of the mobile devices would be automatically waken up and connected with the service-provider so as to receive the updated security information. While the mobile device is to request additional information, the passive-pull transmission manner can then be applied by the mobile device to obtain the additional information from the information service provider. Thus, merits of both the active push transmission and the passive pull transmission can be obtained.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: May 15, 2018
    Assignee: Fonestock Technology Inc.
    Inventors: Albert Chu Tsung Chen, Jun Yih Lee, Pi Ping Wei
  • Patent number: 9959049
    Abstract: Techniques for aggregating background processing in a data storage system. Blocks are identified having contents on which a data operation was not performed in-line. The background data operation is prevented for blocks that will no longer be accessed by the host computer because they are only mapped to files implementing data objects that are scheduled for future deletion. A region of blocks may be selected that meets a criteria for performing a background free space operation, and the background data operation may be performed on the contents of blocks in the selected region while the contents of those blocks are being relocated to other blocks while performing the background free space operation. While performing the background data operation, blocks may be freed from files that implement data objects scheduled for future deletion.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: May 1, 2018
    Assignee: EMC IP Holding Company LLC
    Inventor: Philippe Armangau
  • Patent number: 9959386
    Abstract: An example method includes monitoring healthcare information employed by a local information system of a first healthcare entity via an edge device located at a facility of the first healthcare entity and in communication with a local information system. The edge device is to implement a local cloud system. The local cloud system is to be accessible by only the first healthcare entity and healthcare entities affiliated with the first healthcare entity. The example method also includes determining if the healthcare information has a first characteristic via the edge device, determining if the healthcare information has a second characteristic via the edge device, and automatically uploading the healthcare information onto the local cloud system if the healthcare information has the first characteristic. The example method also includes automatically uploading the healthcare information onto a remote cloud system if the healthcare information has the second characteristic.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: May 1, 2018
    Assignee: General Electric Company
    Inventors: Nimrod Ohad, Mark Alan Cole, Mike Lowell Sharland, Ronen Gans, Patrick Leo Hughes
  • Patent number: 9959060
    Abstract: A plurality of traffic profiles is determined for a plurality of traffic groups where each traffic profile includes a share of traffic and an address footprint size associated with a corresponding traffic group. A host write is received from a host and the traffic group that the host write belongs to is identified. Write data associated with the host write is stored in the solid state storage allocated to the traffic group that the host write is identified as belonging to where the amount of solid state storage allocated to each of the plurality of traffic groups is based at least in part on the traffic profile of a given traffic group.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: May 1, 2018
    Assignee: SK Hynix Inc.
    Inventors: Xiangyu Tang, Lingqi Zeng
  • Patent number: 9954875
    Abstract: Protection from malware download is provided. A first input is received to access one of an email attachment or a web site link using an application. A newly generated secure virtual machine is obtained from one of a network server or a cloud computing service. The one of the email attachment or the web site link is sent to the newly generated secure virtual machine for processing.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventor: Richard H. Boivie
  • Patent number: 9952789
    Abstract: A memory system includes a nonvolatile memory module and a memory controller. The nonvolatile memory module includes a plurality of memory chips and a module controller disposed on a printed circuit board. The module controller controls operations of the plurality of memory chips. Each of the plurality of memory chips includes a plurality of nonvolatile memory cells and operates in an operation mode. The operation mode is either a memory mode or a storage mode. The memory controller performs a write operation and a read operation on the nonvolatile memory module, and performs a first error check and correction (ECC) operation on data communicated with the nonvolatile memory module. One of the module controller or the plurality of memory chips performs a second ECC operation on data stored in the plurality of memory chips based on the operation mode of the plurality of memory chips.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: April 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kwang-Jin Lee
  • Patent number: 9953074
    Abstract: An operator tree is formed for a data processing plan, the operator tree containing a plurality of interconnected nodes and including a grouping of two or more duplicative portions, each of the two or more duplicative portions having identical nodes and structure such that when the operator tree is executed, operators executed in a first duplicative portion using a first thread perform same functions use different data than operators in a second duplicative portion using a second thread. One or more operators in the first portion and one or more operators in the second portion to be synchronized with each other are identified. A synchronization point is created for the identified operators in the first thread and one or more subsequent threads, wherein the synchronization point receives information from each of the identified operators to build an artifact to deliver to one or more operators that depend on the artifact.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: April 24, 2018
    Assignee: SAP SE
    Inventors: Daniel James Farrar, Evguenia Eflov
  • Patent number: 9946661
    Abstract: A command executing method for a memory storage apparatus is provided. The method includes grouping logical addresses into logical address groups and assigning a key for each of the logical address groups independently. The method also includes receiving a write command and write data corresponding to the write command and temporarily storing the write data into a buffer memory. The method further includes executing the write command, enabling a direct memory access once to transfer the write data from the buffer memory to a writable non-volatile memory module of the memory apparatus and encrypting each sector data of the write data with keys corresponding to the logical address groups that the logical address storing the sector data belong to.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: April 17, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ming-Hui Tseng, Chian-Hung Hou, Chao-Sung Yeh
  • Patent number: 9940458
    Abstract: Technologies are generally described for systems, devices and methods effective to generate an alert in a computing system. In some examples, a read request may be identified to read from a memory location in a memory. The memory location may include first data accessible by a virtual machine and an instance manager module. The first data may be allowed to be read from the memory location. A write request may be identified to write second data to the memory location. A flag may be identified in response to the identification of the write request. The flag may be associated with the memory location. An alert may be generated, based on the identification of the flag and the identification of the write request.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: April 10, 2018
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Ezekiel Kruglick
  • Patent number: 9927490
    Abstract: An integrated circuit senses attempts to access security-related data stored in registers connectable into a scan chain when the attempt includes locally and selectively asserting a scan-enable signal at a corresponding branch of the scan-enable tree when the integrated circuit is in a secure functional mode. When such an attempt is detected, the integrated circuit (i) generates a security warning that causes a reset of the security-related data and/or (ii) engages a bypass switch to disconnect the scan chain from the respective output terminal to preclude the security-related data from being shifted out of the IC via the scan chain.
    Type: Grant
    Filed: July 3, 2016
    Date of Patent: March 27, 2018
    Assignee: NXP USA, INC.
    Inventors: Pingli Hao, Wanggen Zhang
  • Patent number: 9927979
    Abstract: For a data copying operation, data compression using constant number-of-track-groups and a thinly provisioned target device facilitates incremental updates where the size of the compressed data on the target device changes. Compressed data is written to the same LBA as the beginning of the source device chunk cluster LBA (1:1 mapping of data start). A termination string or other demarking device is used to identify space freed on the target device resulting from compression. During an incremental update only changed chunk clusters are changed, and freed space is changed accordingly if necessary.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: March 27, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Arieh Don, Alexandr Veprinsky, Jeremy J. O'Hare, John T. Fitzgerald
  • Patent number: 9923562
    Abstract: Upon a first transition from a first state to a second state, a first bit in a memory unit comprising a plurality of bits is programmed. Upon a first transition from the second state to the first state, a second bit in the memory unit is programmed, the second bit being before the first bit in the sequence of the plurality of bits. Upon a second transition from the first state to the second state, a third bit in the memory unit is programmed, the third bit being subsequent to the first bit by at least two bits in the sequence of the plurality of bits. Upon a second transition from the second state to the first state, a fourth bit in the memory unit is programmed, the fourth bit being before the third bit in the sequence of the plurality of bits.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: March 20, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Wayne H. Vinson, Travis D. Fox
  • Patent number: 9910669
    Abstract: A processor includes a front end to receive an instruction, a decoder to decode the instruction, a core to execute the first instruction, and a retirement unit to retire the first instruction. The core includes logic to execute the first instruction, including logic to repeatedly record a translation lookaside buffer (TLB) until a designated number of records are determined, and flush the TLB after a flush interval.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: Kshitij A. Doshi, Christopher J. Hughes
  • Patent number: 9911000
    Abstract: A method, system and computer program product are provided for implementing block extent granularity authorization processing for a Coherent Accelerator Processor Interface (CAPI) adapter. An Application Client requests authorization to a File from a system processor file system. The file system validates the request, determines the location of each Extent that comprises the File, and requests authorization to each Extent from a System CAPI Authorization manager. The System CAPI Authorization manager requests the CAPI Client manager to assign a Child Client ID and CAPI Server Register range to the requesting Application Client and requests a previously authorized CAPI Parent Client to authorize the Child ID to the list of Extents. The CAPI Parent Client sends a Create Authorizations command to the CAPI Adapter via the Parent's CAPI Server Registers.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Brian E. Bakke, Adrian C. Gerhard, Daniel F. Moertl
  • Patent number: 9910736
    Abstract: According to embodiments described herein, a backup server maintains backup data for a set of data, which includes data for a first block and a second block. Backup data for the first and second block include backup data for a plurality of versions of the first and second block. A distinct watermark is stored for each version of the first block and each version of the second block. In response to a request to perform a restoration operation on the set of data, a particular version of the first block and a particular version of the second block are selected to use in the restoration operation by comparing a restoration target with the watermarks of the version of the first block and second block. The selected version of the first block has a different watermark than the selected version of the second block.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: March 6, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Steven Wertheimer, Muthu Olagappan, Raymond Guzman, William Fisher, Beldalker Anand, Sriram Nagaraja Rao, Chris Plakyda, Debjyoti Roy, Senad Dizdar
  • Patent number: 9904555
    Abstract: Described herein are mechanisms for continuous automatic tuning of code regions for optimal hardware configurations for the code regions. One mechanism automatically tunes the tunable parameters for a demarcated code region by calculating metrics while executing the code region with different sets of tunable parameters and selecting one of the different sets based on the calculated metrics.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: February 27, 2018
    Assignee: Intel Corporation
    Inventor: Ruchira Sasanka
  • Patent number: 9898349
    Abstract: Embodiments of the present invention provide systems, methods, and computer program products for managing requests for acquiring one or more resources in a computing environment. In one embodiment, successful acquisition of the one or more resources is determined. Embodiments of the present invention provide systems, methods, and computer program products for initiating a synchronous request to acquire the one or more resources, responsive to determining that the acquisition of the one or more resources is not successful.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joseph W. Gentile, Jie Hou, Andrew M. Sica, Douglas M. Zobre
  • Patent number: 9898327
    Abstract: The invention concerns a compute node comprising: one or more processors; one or more memory devices storing software enabling virtual computing resources and virtual memory to be assigned to support:—a virtual machines compartment (402) in which a plurality of virtual machines (VM) is enabled by a hypervisor; and—a services compartment (404) comprising an operating system (OS) enabling one or more of real time capabilities, security functionality, and hardware accelerators, wherein the services compartment further comprises a virtual machines service manager (412) adapted to manage service requests received from the virtual machines; and a hardware partition (418) providing access control between the virtual machines (408) and the virtual machines services compartment (404).
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: February 20, 2018
    Assignee: Virtual Open Systems
    Inventors: Michele Paolino, Salvatore Daniele Raho
  • Patent number: 9892037
    Abstract: A method, system and computer program product are disclosed for direct storage device sharing in a virtualized environment. In an embodiment, the method comprises assigning each of a plurality of virtual functions an associated memory area of a physical memory, and executing the virtual functions in a single root-input/output virtualization environment to provide each of a plurality of guests with direct access to the physical memory. In one embodiment, each of the guests is associated with a respective one of the virtual functions; and the assigning each of the plurality of virtual functions an associated memory area includes maintaining a per-virtual function mapping table identifying a respective one mapping function for each of the virtual functions, and each of the mapping functions mapping one of the memory areas of the physical area to an associated virtual memory.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Gheorghe Almasi, Hubertus Franke, Gokul B. Kandiraju, Davide Pasetto, Hartmut Penner
  • Patent number: 9886216
    Abstract: Systems and methods are disclosed for accessing data over a distributed data storage network. A network-attached storage device (NAS) includes a non-volatile memory module comprising a first portion of data storage for storing local user data associated with a host computing device and a second shared portion of data storage for storing third-party data. The NAS includes a controller configured to provide copies of a portion of the user data to one or more other NAS's for storage therein, receive third-party data from each of the one or more other NAS's, and store the received third-party data in the second portion of data storage. The NAS is configured to upload at least a portion of the user data to the host computing device and upload at least a portion of the third-party data to at least one of the one or more other NAS.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: February 6, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventor: Matthew Bennion
  • Patent number: 9881013
    Abstract: A system, apparatus, method, or computer program product of restricting file access is disclosed wherein a set of file write access commands are determined from data stored within a storage medium. The set of file write access commands are for the entire storage medium. Any matching file write access command provided to the file system for that storage medium results in an error message. Other file write access commands are, however, passed onto a device driver for the storage medium and are implemented. In this way commands such as file delete and file overwrite can be disabled for an entire storage medium.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: January 30, 2018
    Assignee: KOM Software Inc.
    Inventor: Kamel Shaath
  • Patent number: 9875366
    Abstract: Microprocessor system that is implemented or can be implemented in a mobile terminal and comprises: a normal operating system designed to generate and maintain a non-secure runtime environment and a security operating system designed to generate and maintain a secured runtime environment, and an operating system interface between the normal operating system and the security operating system, said operating interface being designed to control communication between the non-secure runtime environment and the secured runtime environment on the operating system level, and at least one filter interface that is designed to securely control communication between the non-secure runtime environment and a secured runtime environment on a level different from the operating system level.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: January 23, 2018
    Assignee: TRUSTONIC LIMITED
    Inventors: Stephen Spitz, Markus Kohler, Ullrich Martini
  • Patent number: 9870809
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 16, 2018
    Assignee: Unity Semiconductor Corporation
    Inventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau
  • Patent number: 9864879
    Abstract: An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations. An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: January 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Kenny T. Coker, David A. Pohm, Stephen P. Van Aken, Michael B. Danielson
  • Patent number: 9864691
    Abstract: The subject disclosure is generally directed towards caching property values in a sparse cache for use in translating notifications to contain property values related to a source instance, e.g., for use in SMI-S compliant notifications (deletion indications). When a deletion indication translation needs properties that are unavailable in the current source instance, a cache is accessed to obtain the previous related property values. The deletion indication is translated based upon the related property values, and output, e.g., as a translated deletion indication to a client subscriber.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: January 9, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Jeegn Chen, James O. Pendergraft, Norman D. Speciner, Yue Zhao
  • Patent number: 9842630
    Abstract: A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: December 12, 2017
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern
  • Patent number: 9842117
    Abstract: A method is used in managing replication of file systems. Metadata of a set of slices of a file system is updated upon performing an operation on a slice of the file system. The file system includes the set of slices. The metadata of the set of slices is used for recovering the file system.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: December 12, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Yingchao Zhou, Jean-Pierre Bono, Changxin Liu, William C. Davenport, Philippe Armangau, Jia Zhai
  • Patent number: 9836412
    Abstract: A plurality of processing elements (PEs) include memory local to at least one of the processing elements in a data packet-switched network interconnecting the processing elements and the memory to enable any of the PEs to access the memory. The network consists of nodes arranged linearly or in a grid to connect the PEs and their local memories to a common controller. The processor performs memory accesses on data stored in the memory in response to control signals sent by the controller to the memory. The local memories share the same memory map or space. The packet-switched network supports multiple concurrent transfers between PEs and memory. Memory accesses include block and/or broadcast read and write operations, in which data can be replicated within the nodes and, according to the operation, written into the shared memory or into the local PE memory.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: December 5, 2017
    Assignee: Rambus Inc.
    Inventor: Ray McConnell
  • Patent number: 9836330
    Abstract: A system and method for allocating software resources. Multiple tasks are received from a network in which each task requires at least one software resource. Each task is analyzed to determine the type of resource(s) required to execute each such task. The availability of the software resource(s) is determined and, if available, allocated to the requesting task. If the software resource(s) is not available, the task is stored in a queue until the software resource(s) becomes available.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: December 5, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Heming Chen, Donald J. McCune, Sujit Phatak, Can Wang
  • Patent number: 9824039
    Abstract: In some embodiments, an apparatus includes a processor that is configured to execute computer usable program code to perform operations. The operations include executing an atomic transaction in a system having a transactional memory. The operations include receiving a signal interrupt during executing of the atomic transaction. The operations include storing a state of the signal interrupt to enable subsequent execution of the signal interrupt. The operations include returning to executing the atomic transaction until the atomic transaction is at least one of completed and aborted. The operations include after executing the atomic transaction is at least one of completed and aborted, determining whether the signal interrupt is received during executing of the atomic transaction. The operations include after determining that the signal interrupt is received during executing of the atomic transaction, retrieving the state of the signal interrupt.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: November 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Paul E. McKenney, Maged M. Michael, Michael Wong
  • Patent number: 9824040
    Abstract: In some embodiments, a method includes executing an atomic transaction in a system having a transactional memory. The method includes receiving a signal interrupt during executing of the atomic transaction. The method includes storing a state of the signal interrupt to enable subsequent execution of the signal interrupt. The method includes returning to executing the atomic transaction until the atomic transaction is at least one of completed and aborted. The method includes after executing the atomic transaction is at least one of completed and aborted, determining whether the signal interrupt is received during executing of the atomic transaction. The method includes after determining that the signal interrupt is received during executing of the atomic transaction, retrieving the state of the signal interrupt. The method includes executing an interrupt handler for processing the signal interrupt and returning from executing of the atomic transaction.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: November 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Paul E. McKenney, Maged M. Michael, Michael Wong