Memory Access Pipelining Patents (Class 711/169)
  • Patent number: 10963611
    Abstract: A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 30, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Ashish Darbari, Iain Singleton
  • Patent number: 10747679
    Abstract: A contiguous region in memory may be configured to store data so that a first portion of the data is addressable using a first indexing scheme and a second portion of the data is addressable using a second indexing scheme. The first portion of the data may include information which may be used by one entity and the second portion of the data may include different information which may be used by another entity.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: August 18, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Steven Scott Larson, Thomas A. Volpe
  • Patent number: 10679227
    Abstract: A trend analysis computing device is provided. The computing device includes a receiver to receive online data, a trend determiner to determine a trend that is presently happening based on a word or a phrase included in the received online data, a processor to compare the determined trend with a dictionary database of the user to determine if the trend is of interest to the user, and, in response to determining the trend is a trend of interest, add additional data to the trend of interest based on the dictionary database, an analyzer configured to analyze the trend of interest, the added additional data, and user interest data, and generate impact data that the trend of interest is having on the user interest data, and a transmitter to transmit the impact data to the user.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: June 9, 2020
    Assignee: MASTERCARD INTERNATIONAL INCORPORATED
    Inventors: Chinmay Sharad Sagade, Srinivas Kosaraju, John Gerard Gamel
  • Patent number: 10656948
    Abstract: This invention provides a cache system and method based on instruction read buffer (IRB). When applied to the field of processor, it is capable of filling instructions to the instruction read buffer which can be directly accessed by processor core and the processor core outputs instruction to the processor core for execution autonomously and achieve a high cache hit rate.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: May 19, 2020
    Assignee: SHANGHAI XINHAO MICROELECTRONICS CO. LTD.
    Inventor: Kenneth Chenghao Lin
  • Patent number: 10599433
    Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache management operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: March 24, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORTED
    Inventors: Joseph Raymond Michael Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad, David M. Thompson
  • Patent number: 10489185
    Abstract: Example methods are provided for locating an operating system (OS) data structure on a host according to a hypervisor-assisted approach. The method may comprise a virtualized computing instance identifying a guest virtual memory address range in which the OS data structure is stored; and configuring the hypervisor to perform a safe read on the guest virtual memory address range to access data stored within the guest virtual memory address range. The method may further comprise the virtualized computing instance performing attribute matching by comparing the data stored within the guest virtual memory address range with attribute data associated with the OS data structure; and determining a location associated with the OS data structure based on the attribute matching.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: November 26, 2019
    Assignee: NICIRA, INC.
    Inventors: Prasad Dabak, Goresh Musalay
  • Patent number: 10467008
    Abstract: Methods and apparatus for identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor including receiving, by an instruction fetch unit of the processor, the interrupt ITAG; retrieving an effective address table (EAT) row from an EAT, wherein the EAT row comprises a range of EAs and a first ITAG of a range of ITAGs; accessing a processor instruction vector comprising a plurality of elements, each element corresponding to one of a plurality of ITAGs; applying a mask to the processor instruction vector to obtain a portion of the processor instruction vector that begins with an element corresponding to the first ITAG and is defined by an element corresponding to the interrupt ITAG; calculating an EA offset; and identifying the EA for the interrupt ITAG using the EA offset and the range of EAs in the retrieved EAT row.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: November 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: David S. Levitan, Mehul Patel, Albert J. Van Norstrand, Jr., Phillip G. Williams
  • Patent number: 10437748
    Abstract: Apparatus, methods, and computer-readable storage media are disclosed for core-to-core communication between physical and/or virtual processor cores. In some examples of the disclosed technology, application cores write notification data (e.g., to doorbell or PCI configuration memory space accesses via a memory interface), without synchronizing with the other application cores or the service cores. In one examples of the disclosed technology, a message selection circuit is configured to, serialize data from the plurality of user cores by: receiving data from a user core, selecting one of the service cores to send the data based on a memory location addressed by the sending user core, and sending the received data to a respective message buffer dedicated to the selected service core.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: October 8, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Leah Shalev, Adi Habusha, Georgy Machulsky, Nafea Bshara, Eric Jason Brandwine
  • Patent number: 10404622
    Abstract: Methods, systems, and computer programs are presented for networking communications. One embodiment of a system includes a switch module having one or more ports with a communications interface of a first type and a switch fabric. The system also includes a switch controller that is in communication with the switch module, the switch controller having a first network operating system (ndOS) for controlling packet switching policy in the switch module. The system further includes a server that executes a hypervisor for processing one or more virtual machines. The sever includes a communication interface of the first type for communicating with the switch module, one or more processors, a second ndOS, and one or more virtual network interface cards (VNIC) for communicating with the switch module via the communication interface of the first type.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 3, 2019
    Assignee: Pluribus Networks, Inc.
    Inventors: Sunay Tripathi, Robert James Drost, Chih-Kong Ken Yang
  • Patent number: 10263858
    Abstract: A system and method for generating a simulation environment are provided. In example aspects, in response to a request from a user of an environment simulation system, specifying a desired web performance metric to result from the execution of a particular content item, the environment simulation system constructs a simulation environment. The environment simulation system is configured to test the particular content item within the constructed simulation environment and compare a baseline web performance metric to the requested web performance metric. In some aspects, if the requested web performance metric is not achieved, the environmental simulation system is configured to perform tuning and continue simulating until the requested web performance metric is achieved. Once tuning is complete, a user can modify a content item and continue simulating to observe improvements in web performance of a content item for a user in a particular geographic region.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: April 16, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Prasanna Vijayanathan, Anant Rao, Sreedhar Veeravalli, Mark E. Pascual
  • Patent number: 10203956
    Abstract: A Vector Floating Point Test Data Class Immediate instruction is provided that determines whether one or more elements of a vector specified in the instruction are of one or more selected classes and signs. If a vector element is of a selected class and sign, an element in an operand of the instruction corresponding to the vector element is set to a first defined value, and if the vector element is not of the selected class and sign, the operand element corresponding to the vector element is set to a second defined value.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: February 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Eric M. Schwarz
  • Patent number: 10169009
    Abstract: Processor hardware detects when memory aliasing occurs, and assures proper operation of the code even in the presence of memory aliasing. Because the hardware can detect and correct for memory aliasing, this allows a compiler to make optimizations such as register promotion even in regions of the code where memory aliasing can occur. The result is code that is more optimized and therefore runs faster.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Srinivasan Ramani, Rohit Taneja
  • Patent number: 10157277
    Abstract: Technologies for memory management with memory protection extension include a computing device having a processor with one or more protection extensions. The processor may load a logical address including a segment base, effective limit, and effective address and generate a linear address as a function of the logical address with the effective limit as a mask. The processor may switch to a new task described by a task state segment extension. The task state extension may specify a low-latency segmentation mode. The processor may prohibit access to a descriptor in a local descriptor table with a descriptor privilege level lower than the current privilege level of the processor. The computing device may load a secure enclave using secure enclave support of the processor. The secure enclave may load an unsandbox and a sandboxed application in a user privilege level of the processor. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Michael LeMay, Barry E. Huntley, Ravi Sahita
  • Patent number: 10135714
    Abstract: One networking device includes a switch module, a server, and a switch controller. The switch module has ports with a communications interface of a first type (CI1) and ports with a communications interface of a second type (CI2). The server, coupled to the switch module via a first CI2 coupling, includes a virtual CI1 driver, which provides a CI1 interface in the server, defined to exchange CI1 packets with the switch module via the first CI2 coupling. The virtual CI1 driver includes a first network device operating system (ndOS) program. The switch controller, in communication with the switch module via a second CI2 coupling, includes a second ndOS program controlling, in the switch module, a packet switching policy defining the switching of packets through the switch module or switch controller. The first and second ndOS programs exchange control messages to maintain a network policy for the switch fabric.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: November 20, 2018
    Assignee: Pluribus Networks, Inc.
    Inventors: Sunay Tripathi, Robert James Drost, Chih-Kong Ken Yang
  • Patent number: 10057082
    Abstract: Described are systems and methods for processing data streams, e.g., to implement event flow programs in a manner that facilitate the co-existence of multiple independent event flow programs in a multi-tenant deployment. In various embodiments, an input data stream is partitioned into multiple primitive data streams that can be processed independently from each other, and portions of two or more primitive data streams are routed and combined to form a complex data stream, facilitating complex processing tasks that take the two or more primitive data streams as input.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: August 21, 2018
    Assignee: eBay Inc.
    Inventors: Jon Birchard Weygandt, Jagori Somadder, Rajiv Karuthethil
  • Patent number: 10049061
    Abstract: Embodiments relate to loading and storing of data. An aspect includes a method for transferring data in an active memory device that includes memory and a processing element. An instruction is fetched and decoded for execution by the processing element. Based on determining that the instruction is a gather instruction, the processing element determines a plurality of source addresses in the memory from which to gather data elements and a destination address in the memory. One or more gathered data elements are transferred from the source addresses to contiguous locations in the memory starting at the destination address. Based on determining that the instruction is a scatter instruction, a source address in the memory from which to read data elements at contiguous locations and one or more destination addresses in the memory to store the data elements at non-contiguous locations are determined, and the data elements are transferred.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: August 14, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, James A. Kahle, Jaime H. Moreno, Ravi Nair
  • Patent number: 9965342
    Abstract: A data processing apparatus is provided having a hierarchy of layers comprising at least two data processing layers, each data processing layer configured to receive data and to generate processed data for passing to a next lower layer in said hierarchy, according to a protocol specific to that data processing layer. Each data processing layer is configured intermittently to add synchronization information to its processed data, the synchronization information providing semantic information required to interpret the processed data. Each data processing layer is further configured to output its synchronization information in response to a synchronization request signal received from a lower layer in said hierarchy, and at least one data processing layer is configured, when outputting its synchronization information, to issue its synchronization request signal to a higher layer in the hierarchy.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: May 8, 2018
    Assignee: ARM Limited
    Inventors: John Michael Horley, Nebojsa Makljenovic, Katherine Elizabeth Kneebone, Michael John Williams, Ian William Spray
  • Patent number: 9959409
    Abstract: A processor of an aspect includes a decode unit to decode a user-level instruction. The user-level instruction is to indicate a page of a secure enclave and is to indicate a linear address. An execution logic is coupled with the decode unit. The execution logic is operable, in response to the user-level instruction, to change an initial linear address of the page of the secure enclave. The initial linear address is to be stored in an enclave page storage metadata unit. The initial linear address is to be changed by the execution logic to the linear address that is to be indicated by the user-level instruction. The change to the linear address is performed without contents of the page of the secure enclave being lost.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: May 1, 2018
    Assignee: Intel Corporation
    Inventors: Rebekah M. Leslie-Hurd, Carlos V. Rozas
  • Patent number: 9940264
    Abstract: A mechanism for simultaneous multithreading is provided. Responsive to performing a store instruction for a given thread of threads on a processor core and responsive to the core having ownership of a cache line in a cache, an entry of the store instruction is placed in a given store queue belonging to the given thread. The entry for the store instruction has a starting memory address and an ending memory address on the cache line. The starting memory addresses through ending memory addresses of load queues of the threads are compared on a byte-per-byte basis against the starting through ending memory address of the store instruction. Responsive to one memory address byte in the starting through ending memory addresses in the load queues overlapping with a memory address byte in the starting through ending memory address of the store instruction, the threads having the one memory address byte is flushed.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Khary J. Alexander, Jonathan T. Hsieh, Christian Jacobi, Martin Recktenwald
  • Patent number: 9886397
    Abstract: A mechanism for simultaneous multithreading is provided. Responsive to performing a store instruction for a given thread of threads on a processor core and responsive to the core having ownership of a cache line in a cache, an entry of the store instruction is placed in a given store queue belonging to the given thread. The entry for the store instruction has a starting memory address and an ending memory address on the cache line. The starting memory addresses through ending memory addresses of load queues of the threads are compared on a byte-per-byte basis against the starting through ending memory address of the store instruction. Responsive to one memory address byte in the starting through ending memory addresses in the load queues overlapping with a memory address byte in the starting through ending memory address of the store instruction, the threads having the one memory address byte is flushed.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: February 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Khary J. Alexander, Jonathan T. Hsieh, Christian Jacobi, Martin Recktenwald
  • Patent number: 9842058
    Abstract: Two translation lookaside buffers may be provided for simpler operation in some embodiments. A hardware managed lookaside buffer may handle traditional operations. A software managed lookaside buffer may be particularly involved in locking particular translations. As a result, the software's job is made simpler since it has a relatively simpler, software managed translation lookaside buffer to manage for locking translations.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: December 12, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Dennis M. O'Connor, Stephen J. Strazdus
  • Patent number: 9823931
    Abstract: Various embodiments of microprocessors and methods of operating a microprocessor during runahead operation are disclosed herein. One example method of operating a microprocessor includes identifying a runahead-triggering event associated with a runahead-triggering instruction and, responsive to identification of the runahead-triggering event, entering runahead operation and inserting the runahead-triggering instruction along with one or more additional instructions in a queue. The example method also includes resuming non-runahead operation of the microprocessor in response to resolution of the runahead-triggering event and re-dispatching the runahead-triggering instruction along with the one or more additional instructions from the queue to the execution logic.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: November 21, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris, Brad Hoyt, Sridharan Ramakrishnan, Hens Vanderschoot, Ross Segelken, Darrell D. Boggs, Magnus Ekman, Aravindh Baktha, David Dunn
  • Patent number: 9729469
    Abstract: Methods, systems, and computer programs are presented for networking communications. One method includes an operation for receiving a packet in a first format by a virtual driver providing a communications interface of a first type (CI1), the first format being for CI1. Further, the method includes an operation for encapsulating the packet in a second format by a processor, the second format being for a communications interface of a second type (CI2) different from CI1. In addition, the method includes an operation for sending the encapsulated packet in the second format to a switch module. The switch module includes a switch fabric, one or more CI1 ports, and one or more CI2 ports, and the switch module transforms the packet back to the first format to send the packet in the first format to a CI1 network via one of the CI1 ports in the switch module.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: August 8, 2017
    Assignee: Pluribus Networks, Inc.
    Inventors: Sunay Tripathi, Robert James Drost, Chih-Kong Ken Yang
  • Patent number: 9678889
    Abstract: Address translation circuitry and a method of operating such a translation circuitry are provided. The address translation circuitry is configured to receive a first address used in a first addressing system and to translate it into a second address used in a second addressing system. Translation pipeline circuitry has plural pipeline stages configured to translate the first address into the second address over the course of the plural pipeline stages. Address comparison circuitry is configured to identify an address match condition when a received first address at least partially matches a previously received first address. Insertion circuitry is configured to determine a stage of progress of the previously received first address in the plural pipeline stages and to cause content of the stage of progress of the previously received first address to be unchanged at a next pipeline cycle when the address comparison circuitry identifies the address match condition.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: June 13, 2017
    Assignee: ARM Limited
    Inventors: Roko Grubisic, Andrew Burdass, Daren Croxford, Isidoros Sideris
  • Patent number: 9626286
    Abstract: A storage module may include a controller that has hardware path that includes a plurality of hardware modules configured to perform a plurality of processes associated with execution of a host request. The storage module may also include a firmware module having a processor that executes firmware to perform at least some of the plurality of processes performed by the hardware modules. The firmware module performs the processes when the hardware modules are not able to successfully perform them.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: April 18, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Sergey Anatolievich Gorobets, Matthew Davidson, Gary J. Lin, Daniel Tuers, Robert Jackson
  • Patent number: 9621482
    Abstract: One networking device includes a switch module, a server, and a switch controller. The switch module has ports with a communications interface of a first type (CI1) and ports with a communications interface of a second type (CI2). The server, coupled to the switch module via a first CI2 coupling, includes a virtual CI1 driver, which provides a CI1 interface in the server, defined to exchange CI1 packets with the switch module via the first CI2 coupling. The virtual CI1 driver includes a first network device operating system (ndOS) program. The switch controller, in communication with the switch module via a second CI2 coupling, includes a second ndOS program controlling, in the switch module, a packet switching policy defining the switching of packets through the switch module or switch controller. The first and second ndOS programs exchange control messages to maintain a network policy for the switch fabric.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 11, 2017
    Assignee: Pluribus Networks Inc.
    Inventors: Sunay Tripathi, Robert James Drost, Chih-Kong Ken Yang
  • Patent number: 9542193
    Abstract: A semiconductor chip is described having a load collision detection circuit comprising a first bloom filter circuit. The semiconductor chip has a store collision detection circuit comprising a second bloom filter circuit. The semiconductor chip has one or more processing units capable of executing ordered parallel threads coupled to the load collision detection circuit and the store collision detection circuit. The load collision detection circuit and the store collision detection circuit is to detect younger stores for load operations of said threads and younger loads for store operations of said threads.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventors: Enrique De Lucas, Pedro Marcuello, Oren Ben-Kiki, Ilan Pardo, Yuval Yosef
  • Patent number: 9507656
    Abstract: A mechanism for handling unfused multiply-add accrued exception bits includes a processor including a floating point unit, a storage, and exception logic. The floating-point unit may be configured to execute an unfused multiply-accumulate instruction defined with the instruction set architecture (ISA). The unfused multiply-accumulate instruction may include a multiply sub-operation and an accumulate sub-operation. The storage may be configured to maintain floating-point exception state information. The exception logic may be configured to capture the floating-point exception state after completion of the multiply sub-operation and prior to completion of the accumulate sub-operation, for example, and to update the storage to reflect the floating-point exception state.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: November 29, 2016
    Assignee: Oracle America, Inc.
    Inventors: Jeffrey S. Brooks, Paul J. Jordan, Christopher H. Olson
  • Patent number: 9507725
    Abstract: A bit or other vector may be used to identify whether an address range entered into an intermediate buffer corresponds to most recently updated data associated with the address range. A bit or other vector may also be used to identify whether an address range entered into an intermediate buffer overlaps with an address range of data that is to be loaded. A processing device may then determine whether to obtain data that is to be loaded entirely from a cache, entirely from an intermediate buffer which temporarily buffers data destined for a cache until the cache is ready to accept the data, or from both the cache and the intermediate buffer depending on the particular vector settings. Systems, devices, methods, and computer readable media are provided.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: November 29, 2016
    Assignee: Intel Corporation
    Inventors: Steffen Kosinski, Fernando Latorre, Niranjan Cooray, Stanislav Shwartsman, Ethan Kalifon, Varun Mohandru, Pedro Lopez, Tom Aviram-Rosenfeld, Jaroslav Topp, Li-Gao Zei
  • Patent number: 9477619
    Abstract: Disclosed herein are system, method and/or computer program product embodiments for increasing memory bandwidth when accessing a plurality of memory devices. An embodiment operates by executing, by at least one processor, a first read operation to read data from a first memory device following an access time for the first memory device. The embodiment further includes executing, by the at least one processor, a second read operation to read data from a second memory device following an access time for the second memory device. The access time for the second memory device is substantially the same or longer than the access time for the first memory device plus a time it takes to read data from the first memory device.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: October 25, 2016
    Inventors: Qamrul Hasan, Dawn M. Hopper, Clifford Alan Zitlaw
  • Patent number: 9454387
    Abstract: According to the invention, a first executable environment is provided. The first executable environment is for execution within an operating system environment of a host computer system. The first executable environment is not an emulator for emulating any of another processor and another operating system. A software application is provided for installation and execution within the operating system environment. The software application is for fixed installation and not for installation in a portable fashion for being ported from one host computer system to another. The software application is then installed within the first executable environment, the installed software application installed within a removable peripheral memory storage device for execution within the first executable environment.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: September 27, 2016
    Assignee: Kingston Digital, Inc.
    Inventors: Laurence Hamid, Marc Charbonneau
  • Patent number: 9348681
    Abstract: An apparatus and method for detecting the fault of a processor are disclosed. The apparatus includes a fetch fault control unit, a decoding fault control unit, and an execution fault control unit. The fetch fault control unit detects the fault of each of fetch units of a plurality of processor cores connected to memory. The decoding fault control unit detects the fault of each of decoding units of the plurality of processor cores connected to the memory. The execution fault control unit detects the fault of each of execution units of the plurality of processor cores connected to the memory, executes the same instruction in the plurality of processor cores, determines a processor core where a fault has occurred, and provides notification of the determined processor to the fetch fault control unit and the decoding fault control unit.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: May 24, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Jin-Ho Han
  • Patent number: 9317434
    Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: April 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert M. Dinkjian, Robert S. Horton, Michael Y. Lee, Bill N. On
  • Patent number: 9311508
    Abstract: A processor of an aspect includes a decode unit to decode a user-level instruction. The user-level instruction is to indicate a page of a secure enclave and is to indicate a linear address. An execution logic is coupled with the decode unit. The execution logic is operable, in response to the user-level instruction, to change an initial linear address of the page of the secure enclave. The initial linear address is to be stored in an enclave page storage metadata unit. The initial linear address is to be changed by the execution logic to the linear address that is to be indicated by the user-level instruction. The change to the linear address is performed without contents of the page of the secure enclave being lost.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: April 12, 2016
    Assignee: Intel Corporation
    Inventors: Rebekah M. Leslie-Hurd, Carlos V. Rozas
  • Patent number: 9262098
    Abstract: A controller controls data input/output for a semiconductor memory device. The controller includes a first buffer configured to perform data transmission between an interface and the semiconductor memory device, a first control unit configured to control the semiconductor memory device according to an external request, and a second control unit configured to control the first buffer and the first control unit to simultaneously process a plurality of external requests according to a pipeline scheme.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: February 16, 2016
    Assignees: SK HYNIX INC., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Eui-Young Chung, Sang-Hoon Park
  • Patent number: 9230654
    Abstract: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: January 5, 2016
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Jin-Ki Kim, Hong Beom Pyeon
  • Patent number: 9208836
    Abstract: Integrated circuit devices transmit data via a shared signaling link in back to back burst intervals without contention and without insertion of performance-degrading bubbles by disabling output drivers during an interval that occurs at an edge or “margin” of a given burst interval and thus at a timing boundary between the back to back burst intervals. In “bit-level margining” embodiments, the driver-disabling operation or “margining” is performed during a portion of each bit interval (i.e., a unit of time allocated to transmission of a bit or other symbol. In “burst-level margining” embodiments, output drivers are disabled over an entire bit interval that occurs at the margin of a given burst interval.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: December 8, 2015
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Patent number: 9201652
    Abstract: A system for translating compressed instructions to instructions in an executable format is described. A translation unit is configured to decompress compressed instructions into a native instruction format using X and Y indices accessed from a memory, a translation memory, and a program specified mix mask. A level 1 cache is configured to store the native instruction format for each compressed instruction. The memory may be configured as a paged instruction cache to store pages of compressed instructions intermixed with pages of uncompressed instructions. Methods of determining a mix mask for efficiently translating compressed instructions is also described. A genetic method uses pairs of mix masks as genes from a seed population of mix masks that are bred and may be mutated to produce pairs of offspring mix masks to update the seed population. A mix mask for efficiently translating compressed instructions is determined from the updated seed population.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: December 1, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Sergei Larin, Lucian Codrescu, Anshuman Das Gupta
  • Patent number: 9195622
    Abstract: It is determined whether more than one half of a plurality of data blocks are addressed to a same primary memory bank in a plurality of memory banks. If not more than one half of the data blocks in the plurality of data blocks are addressed to the same primary memory bank, the plurality of data blocks are written to appropriate ones of the primary memory banks in a single clock cycle. If more than one half of the data blocks are addressed to the same primary memory bank, (i) a subset of the data blocks addressed to the same primary memory bank are written to the same primary memory bank, and (ii) one or more remaining data blocks of the data blocks addressed to the same primary memory bank are written to an additional memory bank.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: November 24, 2015
    Assignee: MARVELL WORLD TRADE LTD.
    Inventor: Amir Roitshtein
  • Patent number: 9170954
    Abstract: Translation management instructions are used in a multi-node data processing system to facilitate remote management of address translation data structures distributed throughout such a system. Thus, in multi-node data processing systems where multiple processing nodes collectively handle a workload, the address translation data structures for such nodes may be collectively managed to minimize translation misses and the performance penalties typically associated therewith.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: October 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • Patent number: 9164908
    Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: October 20, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert M. Dinkjian, Robert S. Horton, Michael Y. Lee, Bill N. On
  • Patent number: 9158677
    Abstract: A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: October 13, 2015
    Assignee: SANDISK ENTERPRISE IP LLC
    Inventors: Aaron K. Olbrich, Douglas A. Prins
  • Patent number: 9152480
    Abstract: Embodiments of the present disclosure provide a method for storing application data and a terminal device, and relate to the field of communications, so that installation of an application having a default specified path and storage of data that is generated after the application is run are enabled to be located in the same storage space. The method includes: receiving an instruction for running a local application, wherein the instruction is triggered by a user; determining an actual path of a storage space in which the application is installed; running the application, and acquiring data that is generated after the application is run; and storing the data that is generated after the application is run in the actual path of the storage space in which the application is installed. The embodiments of the present disclosure are applied to use of a mobile phone.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: October 6, 2015
    Assignee: Huawei Device Co., Ltd.
    Inventor: Lei Chen
  • Patent number: 9135008
    Abstract: A device and a method for performing bitwise manipulation is provided. Multiple bitwise logic circuits are coupled to an instruction decoder, a register array and a rotator. Each bitwise logic circuit includes input multiplexers connected to an output multiplexer. The instruction decoder receives a bit manipulation instruction and sends to each corresponding input multiplexer a control signal based on a type of the instruction. Each input multiplexer of each bitwise logic circuit receives a control signal, a constant signal that has a value that is indifferent to the value of the mask, and a mask affected signal that has a value that is responsive to a value of an associated mask bit. Each input multiplexer selects between the constant signal and the mask affected signal based on the control signal, and outputs a selected signal.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: September 15, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Evgeni Ginzburg, Keren Guy, Adi Katz
  • Patent number: 9092340
    Abstract: A method and system for achieving die parallelism through block interleaving includes non-volatile memory having a multiple non-volatile memory dies, where each die has a cache storage area and a main storage area. A controller is configured to receive data and write sequentially addressed data to the cache storage area of a first die. The controller, after writing sequentially addressed data to the cache storage area of the first die equal to a block of the main storage area of the first die, writes additional data to a cache storage area of a next die until sequentially addressed data is written into the cache area of the next die equal to a block of the main storage area. The cache storage area may be copied to the main storage area on the first die while the cache storage area is written to on the next die.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: July 28, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Steven Sprouse, Chris Avila, Jianmin Huang
  • Patent number: 9092346
    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a speculative cache modification design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a cache communicably interfaced with the data bus; a pipeline communicably interfaced with the data bus, in which the pipeline is to receive a store instruction corresponding to a cache line to be written to cache; caching logic to perform a speculative cache write of the cache line into the cache before the store instruction retires from the pipeline; and cache line validation logic to determine if the cache line written into the cache is valid or invalid, in which the cache line validation logic is to invalidate the cache line speculatively written into the cache when determined invalid and further in which the store instruction is allowed to retire from the pipeline when the cache line is determined to be valid.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: July 28, 2015
    Assignee: Intel Corporation
    Inventor: James E. McCormick, Jr.
  • Patent number: 9047092
    Abstract: A load store pipeline 18 includes an issue queue 20 and load store circuitry 24. The load store circuitry 24 includes the plurality of access slot circuits 26 to 40. Dependency tracking circuitry 42, 44, 46, 48 serves to track a freeable number of access slot circuits 26 to 42 corresponding to the sum of access slot circuits that are empty and those processing data access instructions which have not bypassed any preceding data access instructions within the program execution order.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 2, 2015
    Assignee: ARM Limited
    Inventors: Mélanie Emanuelle Lucie Teyssier, Philippe Pierre Maurice Luc, Albin Pierick Tonnerre
  • Patent number: 9043518
    Abstract: Apparatuses and methods of calibrating a memory interface are described. Calibrating a memory interface can include loading and outputting units of a first data pattern into and from at least a portion of a register to generate a first read capture window. Units of a second data pattern can be loaded into and output from at least the portion of the register to generate a second read capture window. One of the first read capture window and the second read capture window can be selected and a data capture point for the memory interface can be calibrated according to the selected read capture window.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: May 26, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Terry M. Grunzke
  • Patent number: 9036718
    Abstract: Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: May 19, 2015
    Assignee: Intel Corporation
    Inventors: David J. Zimmerman, Michael W. Williams
  • Patent number: 9037827
    Abstract: A system and method for scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: May 19, 2015
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, John Hayes, Bo Hong, Feng Wang, Ethan Miller, Craig Harmer