Abstract: Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.

Abstract: Methods, memories and systems to access a memory may include generating an address during a first time period, decoding the address during the first time period, and selecting one or more cells of a buffer coupled to a memory array based, at least in part, on the decoded address, during a second time period.

Abstract: A tier identification (TID) is to indicate a characteristic of a memory region associated with a virtual address in a tiered memory system. A thread may be serviced according to a first path based on the TID indicating a first characteristic. The thread may be serviced according to a second path based on the TID indicating a second characteristic.

Abstract: A communication apparatus has plural processors to perform pipeline processing on communication data. A first processor among the plural processors transfers information, used by a second processor to perform post-stage processing of the first processor, from a first memory to a second memory.

Abstract: A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

Abstract: A method includes, in at least one aspect, asserting a control signal to one or more devices, determining an initial wait time after asserting the control signal, issuing a first command based on the initial wait time, determining a first interval time associated with the first command and a second command, and issuing the second command based on the first interval time.

Abstract: A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Abstract: A memory device and method of programming the same comprising partitioning memory into two or more chunks of information. At least a first portion of a first of the information chunks can be programmed while concurrently determining whether a first portion of a second of the information chunks should be set or reset. Further, the first portion of the second information chunk can be sequential programmed following the programming of the first portion of the first information chunk. The memory device can include different types of memory, such as PCM memory.

Abstract: Apparatuses and methods of calibrating a memory interface are described. Calibrating a memory interface can include loading and outputting units of a first data pattern into and from at least a portion of a register to generate a first read capture window. Units of a second data pattern can be loaded into and output from at least the portion of the register to generate a second read capture window. One of the first read capture window and the second read capture window can be selected and a data capture point for the memory interface can be calibrated according to the selected read capture window.

Abstract: Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detected, and the received order of the memory access requests is rearranged to avoid or minimize the conflicts or delays and to optimize the flow of data to and from the memory data bus. The memory access requests are executed in the reordered sequence, while the originally received order of the requests is tracked. After execution, data read from the memory device by the execution of the read-type memory access requests are transferred to the respective requestors in the order in which the read requests were originally received.

Abstract: Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the write latency and/or the latency window of a memory device such that a data signal and a data strobe signal are received by the memory device within the latency window of the memory device.

Abstract: System and method for allocating memory resources are disclosed. The system utilizes a bus system coupled to a plurality of requestors and a plurality of memory systems coupled to the bus system. Each memory system includes a memory component and a memory management module including a value that represents access rights to the memory component. The memory management module is configured to receive an access request from a first requestor of the plurality of requestors and to grant access to the memory component only if the value indicates that the first requestor has access rights to the memory component. The memory management module is configurable to change the value to give the access rights to the memory component to a second requestor of the plurality of requestors.

Abstract: A method of providing requests to a cache pipeline includes receiving a plurality of requests from one or more state machines at an arbiter; selecting one of the plurality of requests as a selected request the selected request having been provided by a first state machine; determining that the selected request includes a mode that requires a first step and a second step, the first step including an access to a location in a cache; determining that the location in the cache is unavailable; and replacing the mode with a modified mode that only includes the second step.

Abstract: Embodiments of the invention relate to data replication and block allocation in a file system to support write transactions. Regions in a cluster file system are defined to support a block allocation. Blocks in the defined regions are allocated to support the data replication. A pipeline manager is provided to schedule population of the blocks in the allocated region(s) based upon network characteristics.

Abstract: A data read/write system includes a system clock, a single port memory, a cache memory that is separate from the single port memory, and a controller coupled to an instruction pipeline. The controller receives, via the instruction pipeline, first data to write to an address of the single port memory, and further receives, via the instruction pipeline, a request to read second data from the single port memory. The controller stores the first data in the cache memory, and retrieves the second data from either the cache memory or the single port memory during one or more first clock cycles of the system clock. The controller copies the first data from the cache memory and stores the first data at the address in the single port memory during a second clock cycle of the system clock that is different than the one or more first clock cycles.

Abstract: According to one embodiment, a semiconductor memory device includes a command processing module, a plurality of storage units, a plurality of control modules, an adjustment circuit, and a setting register. The adjustment circuit is configured to exclude the control module connected to the storage unit of a second group from a write operation in accordance with identification data, and to cause the control module connected to the storage unit of the second group to perform a read operation in a period overlapping the write operation performed by the control module connected to the storage unit of a first group.

Abstract: A storage control device obtains an access request having a random characteristic or an access request having a sequential characteristic, compares a threshold with a ratio of the number of commands corresponding to the access request having the random characteristic to the number of commands corresponding to the access request having the sequential characteristic, generates and issues a command to which first identification information for instructing a storage to determine an execution order of commands issued to the storage has been assigned or a command to which second identification information for instructing the storage to execute commands in an order in which the storage received the commands has been assigned, in accordance with a result of the comparison, measures a time from issuance of the command to a response from the storage when the obtained access request has a random characteristic, and adjusts the threshold.

Abstract: A method of rebuilding metadata in a flash memory controller following a loss of power. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area is valid.

Abstract: Embodiments of the systems and methods disclosed provide a distributed RAID system comprising a set of data banks. More particularly, in certain embodiments of a distributed RAID system each data bank has a set of associated storage media and executes a similar distributed RAID application. The distributed RAID applications on each of the data banks coordinate among themselves to distribute and control data flow associated with implementing a level of RAID in conjunction with data stored on the associated storage media of the data banks.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: Queuing of received transactions that have a resource conflict is disclosed. A first node receives a first transaction from a second node, where the first transaction relates to a resource of the first node. The transaction may be a request relating to a memory line of the first node, for instance. It is determined that a second transaction that relates to this resource of the first node is already being processed by the first node. Therefore, the first transaction is enqueued in a conflict queue within the first node. The queuing may be a linked list, a priority queue, or another type of queue. Once the second transaction has been processed, the first transaction is restarted for processing by the first node. The first transaction is then processed by the first node.

Abstract: A network device includes memory having memory banks, and a packet processor module configured to receive bursts of packets and segment a received packet into a plurality of sections corresponding to the memory banks. The memory is configured to store a first section of a first received packet at a first one of the memory banks, continue storing remaining sections of the first received packet in remaining ones of the memory banks, and begin storing sections of a second received packet at a second one of the memory banks. The second one of the memory banks is offset from the first one of the memory banks by at least one of a number of memory banks that is less than a total number of memory banks required to store the first received packet, and a number of banks that is randomly selected for each of the packets.

Abstract: Write-through-read (WTR) comparator circuits and related WTR processes and memory systems are disclosed. The WTR comparator circuits can be configured to perform WTR functions for a multiple port file having one or more read and write ports. One or more WTR comparators in the WTR comparator circuit are configured to compare a read index into a file with a write index corresponding to a write-back stage selected write port among a plurality of write ports that can write data to the entry in the file. The WTR comparators then generate a WTR comparator output indicating whether the write index matches the read index to control a WTR function. In this manner, the WTR comparator circuit can employ less WTR comparators than the number of read and write port combinations. Providing less WTR comparators can reduce power consumption, cost, and area required on a semiconductor die for the WTR comparator circuit.

Abstract: In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency.

Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

Abstract: Systems and methods are disclosed for limiting power consumption of a non-volatile memory (NVM) using a power limiting scheme that distributes a number of concurrent NVM operations over time. This provides a “current consumption cap” that fixes an upper limit of current consumption for the NVM, thereby eliminating peak power events. In one embodiment, power consumption of a NVM can be limited by receiving data suitable for use as a factor in adjusting a current threshold from at least one of a plurality of system sources. The current threshold can be less than a peak current capable of being consumed by the NVM and can be adjusted based on the received data. A power limiting scheme can be used that limits the number of concurrent NVM operations performed so that a cumulative current consumption of the NVM does not exceed the adjusted current threshold.

Abstract: Embodiments of the systems and methods disclosed provide a distributed RAID system comprising a set of data banks. More particularly, in certain embodiments of a distributed RAID system each data bank has a set of associated storage media and executes a similar distributed RAID application. Each data bank may have a high speed memory where a write cache is stored. In certain embodiments, a virtualization layer may be executed on a data bank and the distributed RAID application may execute on the virtualization layer. The distributed RAID application may control access to the high speed memory on which the write cache is stored.

Abstract: A multi-port memory, comprising: a plurality of ports, each port including port input logic that generates a write enable value from received control signals, and a delay stage coupled to store the write enable value from the input stage, and configured to force the write enable value to a disable state in response to an asserted busy signal of the port; and an arbitration circuit coupled to the ports that arbitrates contending accesses to the ports by de-asserting a busy signal to one port, and asserting a busy signal for all other ports.

Abstract: A system and method for tracking core load requests and providing arbitration and ordering of requests. When a core interface unit (CIU) receives a load operation from the processor core, a new entry in allocated in a queue of the CIU. In response to allocating the new entry in the queue, the CIU detects contention between the load request and another memory access request. In response to detecting contention, the load request may be suspended until the contention is resolved. Received load requests may be stored in the queue and tracked using a least recently used (LRU) mechanism. The load request may then be processed when the load request resides in a least recently used entry in the load request queue. CIU may also suspend issuing an instruction unless a read claim (RC) machine is available. In another embodiment, CIU may issue stored load requests in a specific priority order.

Abstract: A method, information processing device, and computer program product mitigate busy time in a hierarchical store-through memory cache structure. In one embodiment, a cache directory associated with a memory cache is divided into a plurality of portions each associated with a portion memory cache. Simultaneous cache lookup operations and cache write operations between the plurality of portions of the cache directory are supported. Two or more store commands are simultaneously processed in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory.

Abstract: A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data in a memory and at least one egress module for transmitting the incoming data to at least one egress port. The memory management unit is configured to receive data at a clock speed for the network device and write the data to the memory using a multiplied clock speed that is a multiple of the clock speed for the network device, read out the data from the memory at the multiplied clock speed and provide the data to the at least one egress module at the clock speed for the network device, where the multiplied clock speed is used to sample the clock speed for the network device to place domains of the multiplied clock speed and the clock speed for the network device in phase.

Abstract: Method and apparatus for scheduling access requests for a multi-bank low-latency random read memory (LLRRM) device within a storage system. The LLRRM device comprising a plurality of memory banks, each bank being simultaneously and independently accessible. A queuing layer residing in storage system may allocate a plurality of request-queuing data structures (“queues”), each queue being assigned to a memory bank. The queuing layer may receive access requests for memory banks in the LLRRM device and store each received access request in the queue assigned to the requested memory bank. The queuing layer may then send, to the LLRRM device for processing, an access request from each request-queuing data structure in successive order. As such, requests sent to the LLRRM device will comprise requests that will be applied to each memory bank in successive order as well, thereby reducing access latencies of the LLRRM device.

Abstract: The architecture and techniques described herein can improve system performance with respect to the following. Communication between two interdependent hardware engines, that are part of pipeline, such that the engines are synchronized to consume resources when the engines are done with the work. Reduction of the role of software/firmware from feeding each stage of the hardware pipeline when the previous stage of the pipeline has completed. Reduction in the memory allocation for software-initialized hardware descriptors to improve performance by reducing pipeline stalls due to software interaction.

Abstract: In general, methods and apparatus for implementing a Quality of Service (QoS) model are disclosed. A Quality of Service (QoS) contract with an initiating network device may be satisfied. A request may be received from the initiating network device in a first time less than or equal to an ordinal number times an arrival interval. The ordinal number signifies a position of the request among a group of requests. The request that has been serviced may be returned to the initiator in a second time less than or equal to a constant term plus the ordinal number times a service interval.

Abstract: Disclosed is a method and apparatus for reading mirrored data. In one embodiment, a node receives a read request for data, identical copies of which are maintained on a primary storage device and any number of corresponding minors. A read generator coupled to the node generates a number of read operations for smaller portions of the data. Preferably, the read generator then transmits the read operations in parallel to at least two storage devices on which identical copies of the data are maintained (e.g., a primary storage device and a corresponding mirror, two mirrors of a primary storage device, etc.). The read operations may then be processed in parallel by the storage devices to which the read operations were transmitted.

Abstract: A list structure control circuit includes memories each individually stores data, selection circuits arranged for each of the memories and series-connect the memories so that data stored in each memory has an order relation, and an update control circuit that adds a position selection signal which specifies a position for data insertion or data removal to a fixed value, or subtracts the position selection signal from the fixed value, generates an enable signal based on the calculation result, and controls data retention performed in the memories or data update performed in the memories using data of a memory in precedent stages based on the generated enable signal, wherein the selection circuits are controlled based on the position selection signal at the time of the data insertion, and data stored in a memory located at the position specified by the position specification signal is updated with data to be inserted.

Abstract: Some embodiments provide a system that facilitates concurrency control in a computer system. During operation, the system generates a set of signatures associated with memory accesses in the computer system. To generate the signatures, the system creates a set of hierarchical Bloom filters (HBFs) corresponding to the signatures, and populates the HBFs using addresses associated with the memory accesses. Next, the system compares the HBFs to detect a potential conflict associated with the memory accesses. Finally, the system manages concurrent execution in the computer system based on the detected potential conflict.

Abstract: A schedule control program that is capable of allocating threads to CPUs so as to effectively use caches. When a thread is executed, the execution start time and the CPU number of a CPU that executes the thread are stored. When an interrupted thread is re-allocated to a CPU to execute it next, an elapsed time t counted from the execution start time is calculated. Time parameters are set to caches that are used by the CPUs in such a way that the higher the level of a cache, the larger time parameter is set. If the elapsed time t is smaller than a time parameter set to an n-level (where n is a natural number of 2 or greater) cache and is equal to or larger than a time parameter set to an (n-1)-level cache, the thread is allocated to a CPU with the lowest load among the CPUs sharing the n-level cache with the last execution CPU.

Abstract: Some embodiments of the present invention provide methods, computer media encoding instructions, and systems for receiving write requests directed to non-sequential logical block addresses and writing the write requests to sequential disk block addresses in a storage system. Some embodiments further include overprovisioning a storage system to include an increment of additional storage space such that it is more likely a large enough sequential block of storage will be available to accommodate incoming write requests.

Abstract: A system and method for scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency.

Abstract: Techniques are provided for dynamically re-ordering operation requests that have previously been submitted to a queue management unit. After the queue management unit has placed multiple requests in a queue to be executed in an order that is based on priorities that were assigned to the operations, the entity that requested the operations (the “requester”) sends one or more priority-change messages. The one or more priority-change messages include requests to perform operations that have already been queued. For at least one of the operations, the priority assigned to the operation in the subsequent request is different from the priority that was assigned to the same operation when that operation was initially queued for execution. Based on the change in priority, the operation whose priority has change is placed at a different location in the queue, relative to the other operations in the queue that were requested by the same requester.

Abstract: A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one block of data; merging store data from the store request with the block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated block of data into a store data queue; for each additional store request, where the additional store request requires at least one updated block of data: determining if store forwarding is appropriate for the additional store request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the additional store request.

Abstract: Some of the embodiments of the present disclosure provide an apparatus comprising a command cancellation channel (CCC) including a plurality of stages, the CCC configured to receive a first memory address of a sequence of memory addresses and a corresponding first modification command, determine that at least a first stage of the plurality of stages includes the first memory address and a corresponding second modification command, and erase the first memory address or cancel the second modification command while shifting the first memory address and the second modification command from the first stage to a second stage. Other embodiments are also described and claimed.

Abstract: A system, and computer program product for increasing a capacity of a memory are provided in the illustrative embodiments. Using an application executing using a processor wherein the memory includes a set of ranks, the memory is configured to form a cold tier and a hot tier, the cold tier including a first subset of ranks from the set of ranks in the memory, and the hot tier including a second subset of ranks from the set of ranks in the memory. A determination is made whether a page to which a memory access request is directed is located in the cold tier in the memory. In response to the page being located in the cold tier of the memory, the processing of the memory access request is throttled by processing the memory access request with a delay.

Abstract: Methods, systems and computer program products for implementing a polling process among one or more flash memory devices are described. In some implementations, the polling process may include sending a read status command to a flash memory device to detect the ready or busy state of the flash memory device. A status register may be included in the flash memory device for storing a status signal indicating an execution state of a write (or erase) operation. A solid state drive system may perform the polling process by reading the status register of the flash memory device.

Abstract: The object of the invention is to provide the user with improved operatability of an information-processing apparatus and usability of application programs as well as to implement rendering of services to download the application programs from a server to the information-processing apparatus. If storage means employed in the information-processing apparatus does not contain a free area with a storage size large enough for accommodating a desired application program and a data file relevant thereto to be downloaded from the server, an information communication system comprising the information-processing apparatus and the server automatically transfers application programs and data files from the storage means to an external recording medium such as the server itself to be saved therein in order to secure a free storage area in the storage means. The free storage area is used for storing a desired application program and a relevant data file which are to be downloaded from the server.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed.

Abstract: Disclosed herein are systems, methods, and non-transitory computer-readable storage media for managing free chains of compute resources. A system configured to practice the method divides a free chain of compute resources into a usable part (UP) which contains resources available for immediate allocation and an unusable part (UUP) which contains resources not available for immediate allocation but which become available after a certain minimum number of allocations. The system sorts resources in the UP by block number, and maintains a last used object (LUO) vector, indexed by block number, which records a last object in the UP for each block. Each time the system frees a resource, the system adds the freed resource to a tail of the UUP and promotes an oldest resource in the UUP to the UP. This approach can manage free chains in a manner that is both flaw tolerant and has relatively high performance.

Abstract: A method, system, and apparatus are directed towards selectively compressing data for transmission over a network. In one embodiment, a sending network device and receiving network device negotiates different compression modes to communicate data between them. An initial compression mode may be selected based on a network bandwidth. The sending network device then reads data, and compresses using the selected compression mode. The compressed data may then be written out. Ratios of compression and the write times are then employed to selectively adjust the compression mode for subsequent data compressions. In one embodiment, a compression ratio is also employed to determine whether to employ the selected compression mode, or to reduce the level of compression by using a different compression mode. The receiving network device having received information about the selected compression mode, then employs that compression mode to decompress the received data.

Abstract: To provide a job scheduler, a job scheduling method, and a job control program that are capable of, even with an incapable CPU not equipped with a real-time OS, meeting basic real-time property that is required in a system. The job scheduler is a job scheduler 5 for calling each of a plurality of jobs for controlling an appliance to a main loop and causing each job to be executed. The job scheduler 5 carries out calling control including: dividing the jobs into a plurality of groups according to a degree of need for real-time processing of each jobs; setting a priority on a group basis; and restricting a calling frequency, per cycle, of a job belonging to a group of low priority to a minimum tolerated frequency.