Abstract: A multithreaded rendering software pipeline architecture utilizes a rolling texture context data structure to store multiple texture contexts that are associated with different textures that are being processed in the software pipeline. Each texture context stores state data for a particular texture, and facilitates the access to texture data by multiple, parallel stages in a software pipeline. In addition, texture contexts are capable of being “rolled”, or copied to enable different stages of a rendering pipeline that require different state data for a particular texture to separately access the texture data independently from one another, and without the necessity for stalling the pipeline to ensure synchronization of shared texture data among the stages of the pipeline.

Abstract: A memory system, apparatus and method for performing operations in a shared cache coupled to a first requester and a second requester. The method includes receiving at the shared cache a first request from the second requester; assigning the request to a state machine; transmitting a first pipe pass request from the state machine to an arbiter; providing a first instruction from the first pipe pass request to a cache pipeline, the first instruction causing a first pipe pass; and providing a second pipe pass request to the arbiter before the first pipe pass is completed. The first requester may be a lower level cache such as an L2 cache, or an I/O device and the second requester may be an upper level cache such as an L4 cache, and the first request may be a coherency request.

Abstract: A Trusted Service Manager (TSM) receives via a first communication channel from a Service Provider (SP) a request (REQ(MIA)) that contains an application (MIA) together with a unique identifier of a mobile phone (MOB), particularly its telephone number. The mobile phone (MOB) is equipped with a memory device (MIF) that comprises multiple memory sectors being protected by sector keys. Preferably the memory device (MIF) is a MIFARE device. The TSM extracts the application (MIA) and the unique identifier from the received request, assigns destination sector(s) and associated sector key(s) of the memory device (MIF), compiles the application (MIA), the sector key(s) and the sector number(s) of the destination sector(s) into a setup-message (SU(MIA)), encrypts the setup-message and transmits it to either the mobile phone via a second communication channel or the Service Provider via the first communication channel (CN).

Abstract: The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several components may request access to the memory banks. A controller can receive the requests and open or close the pages in the memory bank in response to the requests. In some embodiments, the controller assigns priority to some components requesting access, and assigns a specific page in a memory bank to the priority component. Further, additional available pages in the same memory bank may also be opened by other priority components, or by components with lower priorities. The controller may conserve power, or may increase the efficiency of processing transactions between components and the memory bank by closing pages after time outs, after transactions are complete, or in response to a number of requests received by masters.

Abstract: Dynamically managing a thread pool associated with a plurality of sub-applications. A request for at least one of the sub-applications is received. A quantity of threads currently assigned to the at least one of the sub-applications is determined. The determined quantity of threads is compared to a predefined maximum thread threshold. A thread in the thread pool is assigned to handle the received request if the determined quantity of threads is not greater than the predefined maximum thread threshold. Embodiments enable control of the quantity of threads within the thread pool assigned to each of the sub-applications. Further embodiments manage the threads for the sub-applications based on latency of the sub-applications.

Abstract: Techniques for epoch pipelining are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for epoch pipelining comprising the steps of beginning a first epoch, determining for one or more pages of memory if the pages of memory are likely to be modified in a subsequent epoch, performing a first operation on the pages of memory that are likely to be modified in a subsequent epoch, beginning a second epoch, subsequent to the first epoch, performing a second operation on the pages of memory that are not likely to be modified in a subsequent epoch, and ending the first epoch, wherein the first operation and the second operation are dissimilar.

Abstract: A communication interface (e.g., a memory interface) includes a data processing channel adapted to be coupled to a data source and having multiple data processing stages. A bypass network or pipeline is coupled to the data processing channel and configurable to bypass at least one stage in the data processing channel. A controller is coupled to the bypass network for configuring the bypass network to bypass at least one stage of the data processing channel based on performance criteria. In some embodiments or modes of operation, the bypass network is configured to bypass at least one stage of the data processing channel to reduce idle latency after an idle period. In an alternative embodiment or mode of operation, the bypass channel is configured to include at least one stage of the data processing channel to increase data throughput.

Abstract: A Method to redirect SRB routines from otherwise non-zIIP eligible processes on an IBM z/OS series mainframe to a zIIP eligible enclave is disclosed. This redirection is achieved by intercepting otherwise blocked operations and allowing them to complete processing without errors imposed by the zIIP processor configuration. After appropriately intercepting and redirecting these blocked operations more processing may be performed on the more financially cost effective zIIP processor by users of mainframe computing environments.

Abstract: A Method to redirect SRB routines from otherwise non-zIIP eligible processes on an IBM z/OS series mainframe to a zIIP eligible enclave is disclosed. This redirection is achieved by intercepting otherwise blocked operations and allowing them to complete processing without errors imposed by the zIIP processor configuration. After appropriately intercepting and redirecting these blocked operations more processing may be performed on the more financially cost effective zIIP processor by users of mainframe computing environments.

Abstract: A command processing pipeline is coupled to a shared cache. The command processing pipeline comprises (i) a first command processing stage configured to sequentially receive and process first and second cache commands, and (ii) a second command processing stage coupled to the first command processing stage. The first and the second command processing stages are two consecutive command processing stages of the command processing pipeline. The first and second command processing stages may access different groups of cache resources, and the first and second cache commands may be processed during consecutive clock cycles of a clock signal. Processing of the second cache command may be performed independently of an outcome of processing the first cache command by the first command processing stage. A third command processing stage may write data associated with the first cache command to one of a valid memory and a data memory included in the cache.

Abstract: For decreasing seeks generated when switching an execution flow between commands to enhance read and write performances of a disc drive, a command is implemented with a specifically-designed data structure, and commands having neighboring physical addresses and the same type of read or write operations are grouped and linked together. With the aid of command groups, seeks between commands are significantly decreased, though starvation may arise. A few techniques are further provided for preventing starvation of command groups and for preserving the benefits of decreasing seeks.

Abstract: A method of storing data onto a non-volatile memory includes receiving, from a host, first data that is originally assigned to a first storage area, programming the first data to a second storage area, receiving second data from the host, and while receiving the second data from the host, programming, to the first storage area, the first data that has been programmed to the second storage area, wherein the second data is received from the host simultaneously with the first data being programmed to the first storage area. The second storage area is capable of having data stored thereon faster than the first storage area.

Abstract: The disclosed embodiments relate to a system for processing memory references received from multiple processor cores. During operation, the system monitors the memory references to determine whether memory references from different processor cores are interfering with each other as the memory references are processed by a memory system. If memory references from different processor cores are interfering with each other, the system time-multiplexes the processing of memory references between processor cores, so that a block of consecutive memory references from a given processor core is processed by the memory system before memory references from other processor cores are processed.

Abstract: A data storage method includes, in a memory controller that accepts memory access commands from a host for execution in one or more memory units, holding a definition of a policy to be applied by the memory controller in the execution of the memory access commands in the memory units. The policy is reported from the memory controller to the host so as to cause the host to format memory access commands based on the reported policy.

Abstract: Embodiments of systems and methods for routing commands to a distributed RAID system are disclosed. Specifically, embodiments may route a command to an appropriate data bank in a distributed RAID system, where each data bank has a set of associated storage media and executes a similar distributed RAID application. The distributed RAID applications on each of the data banks coordinate among themselves to distribute and control data flow associated with implementing a level of RAID in conjunction with data stored on the associated storage media of the data banks.

Abstract: A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Abstract: Embodiments of the systems and methods disclosed provide a distributed RAID system comprising a set of data banks. More particularly, in certain embodiments of a distributed RAID system each data bank has a set of associated storage media and executes a similar distributed RAID application. The distributed RAID applications on each of the data banks coordinate among themselves to distribute and control data flow associated with implementing a level of RAID in conjunction with data stored on the associated storage media of the data banks.

Abstract: A method includes operating an arbitration logic of a memory controller at a core clock frequency lower than that of a memory clock frequency. The memory controller is configured to generate a command sequence including a number of commands in accordance with a number of external requests to access the memory. The method also includes parallelizing the number of commands in the command sequence based on a timing requirement for a non-first command in the command sequence defined by a memory-access protocol being satisfied at a rising edge or a falling edge of the core clock relative to a previous command in the command sequence. Further, the method includes ensuring, through the parallelizing, availability of the number of commands in the command sequence to a memory interface operating at the memory clock frequency at a command rate equal to the memory clock frequency.

Abstract: Some of the embodiments of the present disclosure provide an apparatus comprising a command cancellation channel (CCC) including a plurality of stages, the CCC configured to receive a first memory address of a sequence of memory addresses and a corresponding first modification command, determine that at least a first stage of the plurality of stages includes the first memory address and a corresponding second modification command, and erase the first memory address or cancel the second modification command while shifting the first memory address and the second modification command from the first stage to a second stage. Other embodiments are also described and claimed.

Abstract: Systems and/or methods that facilitate transferring data between a processor component and memory components are presented. A transfer controller component facilitates controlling data transfers in part by receiving respective subsets of data from respective memory components and arranging the respective subsets of data based in part on a desired predefined data order. The processor component generates a transfer map that includes information to facilitate arranging data in a predefined order. The processor component generates respective subsets of commands that are provided to queue components in respective memory components to retrieve desired data from the respective memory components. Each memory component services the commands in its queue component in an independent and parallel manner, and transfers the data retrieved from memory to the transfer controller component, which can arrange the received data in a predefined order for transfer to the processor component.

Abstract: A mechanism for retrieving data over a network using an asynchronous buffer is described herein. According to one embodiment, an exemplary process includes, in response to a request for first data from a client via a first thread, determining whether a local circular buffer contains the requested first data, the local circular buffer having a head region and a tail region for identifying a head and a tail of the local circular buffer respectively, and the local circular buffer containing a portion of a data file maintained by a server over a network, generating a second thread to the server over the network to request the first data, if the local circular buffer does not contain the requested first data, and returning the first thread to the client while waiting for a result of the second thread from the server. Other methods and apparatuses are also described.

Abstract: In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load.

Abstract: A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.

Abstract: A system controller communicates with devices in a serial interconnection. The system controller sends a read command, a device address identifying a target device in the serial interconnection and a memory location. The target device responds to the read command to read data in the location identified by the memory location. Read data is provided as an output signal that is transmitted from a last device in the serial interconnection to a data receiver of the controller. The data receiver establishes acquisition instants relating to clocks in consideration of a total flow-through latency in the serial interconnection. Where each device has a clock synchronizer, a propagated clock signal through the serial interconnection is used for establishing the acquisition instants. The read data is latched in response to the established acquisition instants in consideration of the flow-through latency, valid data is latched in the data receiver.

Abstract: A network storage system includes an address adjusting module that includes a segmented packet receiver module that receives M sections of a segmented packet, where M is an integer greater than one. A bank identification (ID) overwriter module overwrites a bank ID of at least one of the M sections of the packet with a control bank ID that is different than the bank ID.

Abstract: In a system and method for write hazard handling a memory management unit policy is pre-computed for a write request using an address that is at least one clock cycle before data. The pre-computed memory management unit policy is registered and used for controlling a pipeline stall to ensure that a non-bufferable write is pipeline-protected, so that no non-bufferable location is bypassed from within the pipeline, and so that a subsequent non-bufferable read will get data from a final destination. A read request is bypassed only after a corresponding write request is updated in a write pending buffer. The write request is decoded with the write request aligned to data. The write request is registered in the write pending buffer. Arbitration logic is allowed to force the pipeline stall for a region that will have a write conflict. Read requests are stalled to protect against write hazards.

Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.

Abstract: A memory system includes logical banks divided into sub-banks or collections of sub-banks. The memory system responds to memory-access requests (e.g., read and write) directed to a given logical bank by sequentially accessing sub-banks or collections of sub-banks. Sequential access reduces the impact of power-supply spikes induced by memory operations, and thus facilitates improved system performance. Some embodiments of the memory system combine sequential sub-bank access with other performance-enhancing features, such as wider power buses or increased bypass capacitance, to further enhance performance.

Abstract: An integrated circuit to serialize local data and selectively merge it with serialized feed-through data into a serial data stream output that includes a parallel-in-serial-out (PISO) shift register, a multiplexer, and a transmitter. The PISO shift register serializes parallel data on a local data bus into serialized local data. The multiplexer selectively merges serialized local data and feed-through data into a serial data stream. The transmitter drives the serial data stream onto a serial data link. In another embodiment of the invention, a method for a memory module includes receiving an input serial data stream; merging local frames of data and feed-through frames of data together into an output serial data stream in response to a merge enable signal; and transmitting the output serial data stream on a northbound data output to a next memory module or a memory controller. Other embodiments of the invention are disclosed and claimed.

Abstract: A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.

Abstract: Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.

Abstract: Multiple pipelined Translation Look-aside Buffer (TLB) units are configured to compare a translation address with associated TLB entries. The TLB units operated in serial order comparing the translation address with associated TLB entries until an identified one of the TLB units produces a hit. The TLB units following the TLB unit producing the hit might be disabled.

Abstract: A method for accessing a memory includes receiving a first address wherein the first address corresponds to a demand fetch, receiving a second address wherein the second address corresponds to a speculative prefetch, providing first data from the memory in response to the demand fetch in which the first data is accessed asynchronous to a system clock, and providing second data from the memory in response to the speculative prefetch in which the second data is accessed synchronous to the system clock. The memory may include a plurality of pipeline stages in which providing the first data in response to the demand fetch is performed such that each pipeline stage is self-timed independent of the system clock and providing the second data in response to the speculative prefetch is performed such that each pipeline stage is timed based on the system clock to be synchronous with the system clock.

Abstract: A non-volatile memory device is operated by outputting data in response to an alternating sequence of first and second edges of a read control signal, respectively. A determination is made whether the read control signal and a write control signal are in synchronization at one of the first edges. Output of the data is stopped at the second edge that follows the one of the first edges of the read control signal if the read control signal and the write control signal are in synchronization at the one of the first edges.

Abstract: In an embodiment, a method is disclosed that includes, comparing, during a write back stage at an execution unit, a write identifier associated with a result to be written to a register file from execution of a first instruction to a read identifier associated with a second instruction at an execution pipeline within an interleaved multi-threaded (IMT) processor having multiple execution units. When the write identifier matches the read identifier, the method further includes storing the result at a local memory of the execution unit for use by the execution unit in the subsequent read stage.

Abstract: A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a processor, a call for a semi-synchronous memory copy operation. The semi-synchronous memory copy operation preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit. The call includes at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied. The memory copy operation is placed in a queue for execution by a memory controller. The queue is coupled to the memory controller. At least one subsequent instruction is continued to be executed as the subsequent instruction becomes available from an instruction pipeline.

Abstract: A memory access control apparatus includes a plurality of memory access request generating modules and an arbitrator. When one of the memory access request generating modules receives a second memory access event while a memory device is performing a first memory access operation according to a first memory access request in response to a first memory access event, the memory access request generating module outputs a second memory access request corresponding to the second memory access event to the memory device after a delay time. The arbitrator is implemented for arbitrating memory access requests respectively outputted from the memory accessing request generating modules.

Abstract: A method and apparatus for allowing multiple devices access to an address translation cache while cache maintenance operations are occurring at the same time. By interleaving the commands requiring address translation with maintenance operations that may normally take many cycles, address translation requests may have faster access to the address translation cache than if maintenance operations were allowed to stall commands requiring address translations until the maintenance operation was completed.

Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface are some operations performed by the controller. The controller determines a width for a Data bus while assigning a target device address to each of the memory devices.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: A concurrent and asynchronous system may be managed by monitoring the performance of a plurality of operations that access a designated region of memory. In that region of memory, an occurrence of a potentially non-deterministic event can be detected when at least one of the operations is a write operation. The occurrence of the potentially non-deterministic event may then be recorded.

Abstract: A method and system for processing data. In one embodiment, the method includes receiving a plurality of stores into a store queue, where each store is a result from a processor, and where the plurality of stores are destined for at least one memory address. The method also includes marking a most recent store of the plurality of stores for each unique memory address, comparing a load request against the store queue, and identifying only the most recent store for each unique memory address for the purpose of handling load-hit-store ordering hazards.

Abstract: Some of the embodiments of the present disclosure provide an apparatus comprising a command cancellation channel (CCC) including a plurality of stages, the CCC configured to receive a first memory address of a sequence of memory addresses and a corresponding first modification command, determine that at least a first stage of the plurality of stages includes the first memory address and a corresponding second modification command, and erase the first memory address or cancel the second modification command while shifting the first memory address and the second modification command from the first stage to a second stage. Other embodiments are also described and claimed.

Abstract: Included are embodiments for facilitating operation of an input/output (I/O) link. At least one embodiment of a method includes receiving a first cache line from a memory controller and determining whether the first cache line corresponds to a first portion of data. Some embodiments include, when the first cache line corresponds to the first portion of data, determining whether a second cache line is received and when the second cache line is not received, processing the first cache line. Similarly, some embodiments include when the first cache line does not correspond to the first portion of data, waiting for a cache line that does correspond to the first portion of data.

Abstract: Embodiments of the systems and methods disclosed provide a distributed RAID system comprising a set of data banks. More particularly, in certain embodiments of a distributed RAID system each data bank has a set of associated storage media and executes a similar distributed RAID application. The distributed RAID applications on each of the data banks coordinate among themselves to distribute and control data flow associated with implementing a level of RAID in conjunction with data stored on the associated storage media of the data banks.

Abstract: A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.

Abstract: Embodiments of systems and methods for routing commands to a distributed RAID system are disclosed. Specifically, embodiments may route a command to an appropriate data bank in a distributed RAID system, where each data bank has a set of associated storage media and executes a similar distributed RAID application. The distributed RAID applications on each of the data banks coordinate among themselves to distribute and control data flow associated with implementing a level of RAID in conjunction with data stored on the associated storage media of the data banks.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: A method of and apparatus for arbitrating a memory access conflict to a memory array. The apparatus may include selection logic coupled with a plurality of ports and a memory array to arbitrate among a plurality of contending memory access requests and to conditionally block write data from accessing the memory array when write data arrives late in time.

Abstract: A data processing system in the form of an integrated circuit includes a general purpose programmable processor and a hardware accelerator. A shared memory management unit provides memory management operations on behalf of both of the processor core and the hardware accelerator. The processor and the hardware accelerator share a memory system. A first communication channel between the processor and the hardware accelerator communicates at least control signals therebetween. A second communication channel coupling the hardware accelerator and the memory system allows the hardware accelerator to perform its own data access operations upon the memory system.