Abstract: A system and method for a processor to determine a memory page management implementation used by a memory controller without necessarily having direct access to the circuits or registers of the memory controller is disclosed. In one embodiment, a matrix of counters correspond to potential page management implementations and numbers of pages per block. The counters may be incremented or decremented depending upon whether the corresponding page management implementations and numbers of pages predict a page boundary whenever a long access latency is observed. The counter with the largest value after a period of time may correspond to the actual page management implementation and number of pages per block.

Abstract: Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an indication that address translation is prohibited, in response to a buffer miss. When a processing unit of the computing environment is met with this restriction, it performs a comparison of page indices, which indicates whether the address translation can continue. If address translation can continue, the restriction is ignored. The processing unit includes a processor or a pageable entity, as examples.

Abstract: A method, apparatus and computer program product are provided for dynamically minimizing translation lookaside buffer (TLB) entries across contiguous memory. A page table with page table entries (PTEs) is provided for mapping multiple sized pages from a virtual address space to a physical address space. Each of the multiple sized pages is a multiple of a base page size. A region of memory having a starting address and a length is divided into a minimum number of natural blocks for the memory region. Once the region of memory is divided into the natural blocks, page table entries (PTEs) are assigned to map each natural block. Multiple identical PTEs are required to map each natural block greater than a base page size. Only one TLB entry is used to map each natural block.

Abstract: A system including a data requester and a storage system. The storage system determines which prefetch data to include with demand data, without the data requester specifying the prefetch data, and provides information enabling the data requestor to discern the demand data from the prefetch data. The data requestor can be a disk drive driver which copies the demand data in fulfilling an operating system request, and then caches the prefetch data. The storage system can be a disk drive.

Abstract: A cache data control system and method for a computer system in which in a memory read processing, a coherent controller issues an advanced speculative read request for (speculatively) reading data from a cache data section in advance to a cache data controller, before reading a cache tag from a cache tag section and conducting cache hit check. If a cache hit has occurred, the cache data controller returns the data subjected to speculative reading as response data, at the time when the cache data controller has received a read request issued by the coherent controller.

Abstract: If a base register value, an index register value and a displacement value are given in the case of operand access, these values are inputted to an arithmetic unit to generate a correctly calculated logical address. Simultaneously, a logical address predicting unit predicts a logical address. An absolute address is predicted based on the predicted logical address by using an absolute address history table. Access to a cache memory (LBS) based on an absolute address is made using the predicted absolute address to obtain cache data. Then, the arithmetic unit calculates a correct absolute address using the correctly calculated address using a TLB and checks if the correct absolute address coincides with the predicted absolute address so as to perform result confirmation of the cache data read from the LBS. In the case of instruction fetch, similar processing is carried out except that the calculation of a logical address is not performed.

Abstract: A method of prefetching from a memory device includes determining a prefetch buffer hit rate (PBHR) and a memory bandwidth utilization (MBU) rate. Prefetches are inserted aggressively if the memory bandwidth utilization (MBU) rate is above a MBU threshold level and the prefetch buffer hit rate (PBHR) is above a PBHR threshold level. Prefetches are inserted conservatively if the memory bandwidth utilization (MBU) rate is above the MBU threshold level and the prefetch buffer hit rate (PBHR) is below the PBHR threshold level.

Abstract: An end of a queue or a page-crossing within a queue is detected. A virtual memory address for the head of the queue or for the next queue page is pre-translated into a physical memory address while the last entry in the queue or in the current queue page is being serviced.

Abstract: A data transfer apparatus for simplifying a module structure for controlling a connected data recording apparatus and improving the processing efficiency. A control code issued by a common application module having a main purpose of check-out/check-in is made a control code corresponding to a device connected by a conversion module and transmitted via a device driver. Moreover, for example, a control code issued by a local application module having a main purpose of controlling processing depending on a device connected shares the aforementioned device driver. For example, the local application module issues a control code in a state matched with a control code format converted by the conversion module. Alternatively, the local application module issues a local control code by indicating issuance of a local control code of a format different from the control code format converted by the conversion module.

Abstract: This invention provides a dual usage cache reload buffer (CRB) to hold both demand loads as well as prefetch loads. A new form of a data cache block touch (DCBT) instruction specifies which level of the cache hierarchy to prefetch data into. A first asynchronous form of a DCBT instruction is issued to prefetch a stream of data into a L2 cache. A second synchronous form of a DCBT instruction is used to prefetch data from the L2 cache to the CRB in the main CPU, which will bypass the L1 data cache and forward data directly to the register file. This CRB has a dual usage and is used to hold both normal cache reloads as well as the aforementioned prefetched cache lines.

Abstract: A method and apparatus are described for protecting cache lines allocated to a cache by a run-ahead prefetcher from premature eviction, preventing thrashing. The invention also prevents premature eviction of cache lines still in use, such as lines allocated by the run-ahead prefetcher but not yet referenced by normal execution. A protection bit indicates whether its associated cache line has protected status in the cache or whether it may be evicted.

Abstract: A method, apparatus, and system that compares a current fetch request having a first start address and length associated with the current fetch request to a second start address of the next fetch request, determines whether the content already loaded in a buffer will be used to at least partially fulfill the next fetch request based upon the comparison, and inhibits access to an instruction cache based upon the comparison.

Abstract: A technique is described to reduce the complexity of floating point linear address (FLA) maintenance in a superscalar processor by coupling FLA updates when floating point data is stored instead of when floating point addresses are stored.

Abstract: A computational circuit for generating a predicted address value includes an instruction field that contains an instruction value. A value immediate field is associated with the instruction field and includes a offset value and a first subset of lower-order bits. An effective address cache stores a plurality of higher-order bits of a plurality of recently-accessed memory addresses and reads out a value corresponding to a second subset of higher-order bits of a memory address that corresponds to the first subset of lower-order bits. A circuit concatenates the second subset, the first subset and the offset value, thereby generating the predicted address value.

Abstract: A system, method, and computer program product are disclosed for invalidating specified pretranslations maintained in a data processing system which maintains decentralized copies of pretranslations. A centralized mapping of virtual addresses to their associated physical addresses is established. The centralized mapping includes a listing of pretranslations of the virtual addresses to their associated physical addresses. Multiple lists of pretranslations are generated. Control of the lists may be passed from one entity to another, such that the lists are not owned by any particular entity. Each one of the lists includes a copy of pretranslations for virtual addresses. A particular one of the physical addresses is specified. Each list that includes a pretranslation of a virtual address to the specified physical addresses is located. The pretranslation of the virtual address to the specified physical address is then invalidated within each one of the lists.

Abstract: A computer system includes a read ahead engine that receives a sequence of read requests and performs read ahead operations in accordance with various patterns detected within the sequence of read requests. The prefetch engine may implement the method of storing a first run value indicative of the run size of a first plurality of sequential read requests, and storing a first skip value indicative of a non-sequential skip associated with a subsequent read request. The method may further include determining whether a second run value indicative of the sequential run size of a second plurality of read requests equals the first run value, and whether a second skip value indicative of another non-sequential skip associated with an additional read request equals the first skip value. If the first run value equals the second run value, and the first skip value equals the second skip value, a stride pattern is indicated, and one or more read ahead operations according to the detected stride pattern may be initiated.

Abstract: An instruction-set-aware method for reducing transitions on an irredundant address bus comprises receiving a first address for communication to a memory on an irredundant address bus. The method retrieves an instruction from a memory location indicated by the first address, transmits the instruction on a data bus, and determines a category of the instruction. The method predicts a second address based, at least in part, on the first address, the instruction, and the category of the instruction.

Abstract: Disclosed is a method of access control for a disk drive whereby an access operation for, particularly, sequentially and alternately executing accesses is supported. A CPU of the present disk drive sequentially and alternately executes accesses to a plurality of data tracks on a disk in response to an access request generated from a host system. During the access operation, the CPU secures time for a look-ahead operation, the time corresponding to the difference between transfer rates. Thus, sequential and alternate access operation in which the number of seek operations can be reduced can be realized.

Abstract: An apparatus and method in a pipelined microprocessor for replacing one of two target addresses in a branch target address cache (BTAC) line. If only one of the two entries is invalid, the invalid entry is replaced. If both entries are valid, the least recently used entry is replaced. If both entries are invalid, the entry is replaced corresponding to the side of the BTAC, indicated by a global status register, not last written to with an invalid entry. In one embodiment, the global status is updated only if a side is written when both entries are invalid. In another embodiment, the BTAC stores N entries per line, where N is greater than 1. The status register maintains information for determining which of the N sides is least recently written. The least recently written side is chosen for replacement.

Abstract: A system and method for analyzing the effectiveness of a computer cache memory. A bus with memory transactions is monitored. A subset of addresses, along with associated transaction data, on the bus is captured and stored in a memory. The captured addresses are applied to a software model of a computer cache. The capture process is repeated multiple times, each time with a different subset of the address space. Statistical estimates of hit rate and other parameters of interest are computed based on the software model. Multiple cache configurations may be modeled for comparison of performance. Alternatively, a subset of addresses along with associated transaction data is sent to a hardware model of a cache. The contents of the hardware model are periodically dumped to memory or statistical data may be computed and placed in the memory. Statistical estimates of hit rate and other parameters of interest are computed based on the contents of the memory.

Abstract: In an information processsing unit with key controlled protection, since it takes a long time to fetch a storage key from key storage, an instruction and computation unit of a CPU receives data from a memory control unit of the CPU before a key is received, and then the transferred storage key is checked.

Abstract: A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.

Abstract: A behavioral memory mechanism for performing address mappings within a data processing system is disclosed. The data processing system includes a processor, a real memory, a address converter, and an address translator. The real memory has multiple real address locations, and each of the real address locations is associated with a corresponding one of many virtual address locations. The virtual address locations are divided into two non-overlapping regions, namely, an architecturally visible virtual memory region and a behavioral virtual memory region. The address converter converts an effective address to an architecturally visible virtual address and a behavioral virtual address. The architecturally visible virtual address is utilized to access the architecturally visible virtual memory region of the virtual memory and the behavioral virtual address is utilized to access the behavioral virtual memory region of the virtual memory.

Abstract: A system, method, and computer program product are disclosed for migrating real pages. A real page of data is established. Virtual addresses that are associated with the real addresses that are included within the real page are generated. A mapping table is established that includes mappings of the virtual addresses to these real addresses. A routine is executed that accesses the mapping table to obtain the mappings of virtual addresses to real addresses. The routine utilizes the virtual addresses to access the data that is stored in the real page. While the routine is executing, the data is migrated from the real page to a new real page. The mapping table is then updated while the routine is executing so that the routine utilizes the same virtual addresses to access the data that is now stored in the new real page. Execution of the routine continues while the mapping table is being updated.

Abstract: Computer systems are typically designed with multiple levels of memory hierarchy. Prefetching has been employed to overcome the latency of fetching data or instructions from or to memory. Prefetching works well for data structures with regular memory access patterns, but less so for data structures such as trees, hash tables, and other structures in which the datum that will be used is not known a priori. The present invention significantly increases the cache hit rates of many important data structure traversals, and thereby the potential throughput of the computer system and application in which it is employed. The invention is applicable to those data structure accesses in which the traversal path is dynamically determined. The invention does this by aggregating traversal requests and then pipelining the traversal of aggregated requests on the data structure.

Abstract: A microprocessor includes a first memory to store microcode and a second memory to store predicted micro-operation addresses. Micro-operation addresses are predicted, stored in memory, and retrieved to get the next micro-operations from the microcode memory. Misprediction recovery logic is used to determine if the next predicted address is correct and to determine a recovery address to correct the predicted address if the predicted address is incorrect.

Abstract: A pointer structure on the storage unit of a non-volatile memory maintains a correspondence between the physical and logical address. The controller and storage unit transfer data on the basis of logical sector addresses with the conversion between the physical and logical addresses being performed on the storage unit. The pointer contains a correspondence between a logical sector address and the physical address of current data as well as maintaining one or more previous correspondences between the logical address and the physical addresses at which old data is stored. New and old data can be kept in parallel up to a certain point. When combined with background erase, performance is improved. In an exemplary embodiment, the pointer structure is one or more independent non-volatile sub-arrays, each with its own row decoder.

Abstract: A computer object access control graphical user interface allows a user to set computer locations where a computer object may be accessed and other users who may access the computer object. The computer object may be a computer file, a computer message, person contact information, etc. The access control user interface may operate, for example, to save a computer object to one or more computer locations, and also to specify sharing of the computer object with one or more other users so that they can access the object. Saving a computer object and setting the sharing of it are together referred to as controlling access to the object, the former referring to where the object may be accessed from and the latter referring to who may access the object. This provides, therefore, a unified interface for selecting and displaying destinations that can be either a file store or a person, thereby unifying the control of access to a computer object.

Abstract: The present invention relates to a technique for accessing memory units in a data processing apparatus. The data processing apparatus comprises of plurality of memory units for storing data values, a processor core for issuing an access request specifying an access to be made to the memory units in relation to a data value, and a memory controller for performing the access specified by the access request. Attribute generation logic is provided for determining from the access request one or more predetermined attributes verifying which of the memory units should be used when performing the access. However, the memory controller does not wait until such determination has been performed by the attribute generation logic before beginning the access.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

Abstract: In some embodiments, the invention includes a system having a memory controller, a bus, and first and second memory devices. The memory controller requests read and write operations and operates with a burst length. The first and second memory devices are coupled to the memory controller through the bus, the first and second memory devices each having a prefetch length that is greater than the burst length, but performing the requested read and write operations with the burst length. Other embodiments are described and claimed.

Abstract: A method and system are employed within a processor for performing page table walks on speculative software prefetch operations. The system includes a first fault register to store information associated with a faulting micro-op relating to a non-prefetch memory access operation and a second fault register to store information associated with a faulting micro-op relating to a prefetch memory access operation. Also included in the system is a first unit to determine whether a currently pending micro-op relates to a non-prefetch operation or a prefetch operation. The first unit is configured to drop the currently pending micro-op from a pipeline if (1) the currently pending micro-op relates to a prefetch memory access and (2) the currently pending micro-op has previously faulted.

Abstract: A computer system may include several caches that are each coupled to receive data from a shared memory. A cache coherency mechanism may be configured to receive a cache fill request, and in response, to send a probe to determine whether any of the other caches contain a copy of the requested data. Some time after sending the probe, the cache controller may provide a speculative response to the cache fill request to the requesting device. By delaying providing the speculative response until some time after the probes are sent, it may become more likely that the responses to the probes will be received in time to validate the speculative response.

Abstract: A processor includes a translation look-aside buffer (TLB) that relates virtual page addresses to both physical page addresses and main-memory addresses. If the processor references a virtual page address in the TLB for which there is no corresponding information in cache, the processor passes the main-memory address directly to main memory, avoiding the latency normally associated with systems that translate a physical page address to a main-memory address before accessing information from main memory.

Abstract: A system and method for a processor to determine a memory page management implementation used by a memory controller without necessarily having direct access to the circuits or registers of the memory controller is disclosed. In one embodiment, a matrix of counters correspond to potential page management implementations and numbers of pages per block. The counters may be incremented or decremented depending upon whether the corresponding page management implementations and numbers of pages predict a page boundary whenever a long access latency is observed. The counter with the largest value after a period of time may correspond to the actual page management implementation and number of pages per block.

Abstract: The present invention describes a method for configuring a station connected to a field bus, wherein a logical address is allocated to said station. The method comprises the steps of: transmitting said logical address from an address-allocation unit to said station; transmitting a physical address from said address-allocation unit to said station, said physical address corresponding to an assumed physical position of said station relative to said field bus; verifying said physical address being transmitted to said station based on an actual physical position of said station relative to said field bus; and storing said transmitted logical address in a memory of said station depending on the verification of said physical address.

Abstract: A cache controller (210) includes a streaming memory attribute. The cache controller (210) is coupled to provide data from a cache line within a cache (228) to a memory (124) when both (a) the cache line is full and (b) the streaming memory attribute is set.

Abstract: A microprocessor capable of suppressing reduction in performance caused due to a cache miss when a specific command is issued. The processor according to the present invention comprises a command buffer/queue; an execution unit; a subroutine call decoder; a data cache control unit; an Addiu decoder for detecting an addiu command; a pre-fetch control section; an adder; a PAdr register; a selector; and an adder circuit. When a subroutine call occurs, a stack pointer is moved by an amount used in a subroutine, and data used in the subroutine is pre-fetched to be stored in an area used by the subroutine in a data cache. Therefore, it is possible to reduce cache miss penalties due to stack access which is apt to be generated at the time of a subroutine call.

Abstract: A next address computing section contains a selector and is connected to an instruction cache. The instruction cache maintains a predecode result of a branch instruction or predefined settings for a field in this branch instruction. Based on this information maintained in the instruction cache, the selector determines whether the compiler performed a branch prediction about the branch instruction or could not perform that branch prediction. When the compiler could not perform the branch prediction, the selector selects an output from a conditional branch prediction device (saturation counter section). When the compiler performed the branch prediction, the selector selects a prediction result by the compiler for a prediction in Agree mode. These selection results are used for setting a value of a register holding the next address. Based on this next-address register value, an instruction is fetched from the cache then inserted into a pipeline.

Abstract: A processor or processor core has register file circuitry having a plurality of physical registers and a plurality of tag storing portions corresponding respectively to the physical registers. Each tag storing portion stores a tag representing a logical register ID allocated to the corresponding physical register. A register selection unit receives a logical register ID and selects one of the logical registers whose tag matches the received logical register ID. A tag changing unit changes the stored tags so as to change a mapping between at least one logical register ID and one of the physical registers. Such register circuitry permits a mapping between logical register IDs and physical registers to be changed quickly efficiently and can permit a desired physical register to be selected quickly.

Abstract: A computer system cache monitors the effectiveness of data inserted into a cache by one or more sources to determine which source should receive preferential treatment when updating the cache. The cache may be part of a computer system that includes a plurality of host systems, each host system includes a host cache, connected to a storage system having a storage system cache. Ghost caches are used to record hits from the plurality of host systems performing operations for storing and retrieving data from the storage system cache. The storage system cache includes a cache controller that is operable to calculate a merit figure and determine an insertion point in a queue associated with the storage system cache based on the merit figure. The merit figure is calculated using a weighting algorithm for weighting hits from the plurality of sources recorded in the ghost caches.

Abstract: A prefetch process that generates prefetch tasks for short sequences that are no longer than n tracks in length. The value of n is selected as 8. The prefetch process maintains a history of short sequences, uses that history to predict an expected length of a current sequence and generates a short prefetch task based on that prediction. The historical short sequence data is stored in histograms, each histogram being associated with a different logical volume. The histograms store a cumulative count of sequence occurrences of a given sequence length for each sequence length in a range of 1 track to n tracks. The process applies a probability-based threshold to its prediction to control the aggressiveness of the prefetch task to be generated. The threshold is adjusted based on system activity level metrics, such as processor utilization and average memory access time.

Abstract: A system for moving physically stored data in a distributed, virtualized storage network is disclosed. A group of data sets is written to a first storage device as part of a write operation such as migration. A plurality of storage devices partially filled with data are designated as substitutes. The write operation to the first storage device is suspended upon receiving a request to read a data set stored in the first storage device, such as occurs in a recall operation. A second storage device is then selected from the plurality of substitute storage devices. The write operation is continued by writing data sets from the group of data sets included in the write operation that were not written to the first storage device to the selected second storage device. The requested data is then read from the first storage device.

Abstract: A data processing system includes a memory storing data to be retrieved and an I/O controller configured to request data stored in the memory at a plurality of addresses. The I/O may be responsive to an internal or external device requesting such data. A fetch machine provides or initiates retrieval of data stored at the requested address, while a prefetch machine predicts future requests and keeps track of memory requests already initiated and queued. Thus, the prefetch machine is responsive to the plurality addresses to predict others of the addresses and provide or initiate retrieval of data stored thereat. To avoid prefetching information already requested and in a fetch queue, the prefetch machine includes a memory storing a last one of the addresses subject to prefetching. Finally, to avoid conflicts between currently requested data and prefetch operation, an arbiter resolves memory accesses or data requests initiated by the fetch and prefetch machines.

Abstract: A shared-memory system includes processing modules communicating with each other through a network. Each of the processing modules includes a processor, a cache, and a memory unit that is locally accessible by the processor and remotely accessible via the network by all other processors. A home directory records states and locations of data blocks in the memory unit. A prediction facility that contains reference history information of the data blocks predicts a next requester of a number of the data blocks that have been referenced recently. The next requester is informed by the prediction facility of the current owner of the data block. As a result, the next requester can issue a request to the current owner directly without an additional hop through the home directory.

Abstract: A network of memory and coherence controllers is provided which interconnected nodes in a cache-coherent multi-processor system. The nodes contain multiple processors operatively connected via respective caches to associated memory and coherence controllers. The system supports better processor utilization and better application performance by reducing the latency in accessing data by performing proactive speculative data transfers. In being proactive, the system speculates, without specific requests from the processors, as to what data transfers will reduce the latency and will make data transfers according to information derived from the system at any time that data transfers could be made.

Abstract: A memory controller includes an incrementer for predicting a next address to be asserted by a processor. The incrementer, structurally a counter, is configurable to wrap at a wrap boundary and to indicate when a predicted address crosses a page boundary if the memory is in page mode. This incrementer provides accurate predictions even where successor addresses are on different pages or, in the case of address loops, even in some cases in which the successor address is not consecutive. Thus, the number of accurate address predictions is increased, enhancing overall performance. The invention has particular applicability to signal processing applications with instructions loops that cross one or more page boundaries.

Abstract: A cache bank prediction unit is provided for use in a processor having a plurality of cache memory banks. The cache bank prediction unit has an input port that receives an instruction. The cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of cache banks is associated with the instruction.

Abstract: A data structure to aid in and a method, system, and computer program product for prefetching data from a data cache are provided. In one embodiment, the data structure includes a prediction history field, a next line address field, and a data field. The prediction history field provides information about the success of past data cache address predictions. The next line address field provides information about the predicted next data cache lines to be accessed. The data field provides data to be used by the processor. When a data line in the data cache is accessed by the processor, determines the value of a prediction history field and the value of a next line address field. If the prediction history field is true, then the next line address in the next line address field is prefetched. Based on whether the next line actually utilized by the processor matches the next line address in the next line address field, the contents of the prediction history field and the next line address filed are modified.

Abstract: A disk driver includes an access log for recording recent transactions with the hard disk drive. The access log may be consulted during write operations to buffer writes to memory before accessing the hard disk drive. The access log may also be consulted during read operations to prefetch additional data during access of the hard disk drive.