Abstract: Methods and apparatus for storing data in a multi-level memory hierarchy having at least a lower level cache and a higher level cache. Relevancy information is maintained for various data values stored in the lower level cache, the relevancy information indicating whether the various data values stored in the lower level cache, if lost, could only be generated from corresponding data stored in the higher level cache. If one of the various data values stored in the lower level cache is to be updated, a determination as to whether corresponding data should be stored in the higher level cache is based at least in part on 1) the status of the relevancy information corresponding to the one of the various data values stored in the lower level cache which is to be updated, and 2) whether the updated value which is to be written into the lower level cache matches one or more select data value patterns.

Abstract: A magnetic disc control apparatus detects a near sequential I/O and pre-reads data from a magnetic disc drive into a cache memory. The control apparatus includes a near sequential I/O processor, which has an I/O history storage table for storing a transfer end address of I/O requested by a host computer, a near sequential I/O identifier for calculating an address difference between the transfer end address read out from this I/O history storage table and the current I/O transfer start address and identifying the I/O as a near sequential I/O if the address difference is within a predetermined value, and a pre-read executor for pre-reading data from the magnetic disc drive to the cache memory when a near sequential I/O is detected.

Abstract: A processor is configured to generate lookahead values using a cumulative constant. The processor classifies operations to a particular register (e.g. the stack pointer register, or ESP in an embodiment employing the x86 instruction set architecture) as either accelerated or non-accelerated. For example, instructions which are defined to increment/decrement the particular register by an explicit or implicit constant value may be accelerated operations. Upon the occurrence of a non-accelerated operation, the processor may begin accumulating the cumulative effect of accelerated operations to the result of the non-accelerated operation as a cumulative offset. The result of the non-accelerated operation (upon execution thereof) may then be added to the cumulative offset values corresponding to each accelerated operation to generate the particular register value corresponding to that accelerated operation. Accordingly, dependencies upon the register due to the accelerated operations may be alleviated.

Abstract: A method and system for mirroring and archiving mass storage. A primary mass storage and a secondary mass storage are synchronized to contain the same data. Thereafter, a primary system tracks changes made to the primary mass storage. These changes are consolidated periodically into update files, the consolidations representing changes made to the primary mass storage during a time interval that ends when the primary mass storage is in a logically consistent state. These update files contain only those changes necessary to represent the modified state of the primary mass storage at the time of the update. The primary system then transfers the update files to a secondary system to bring the secondary mass storage current with the primary mass storage. The consolidation minimizes the amount of information that must be transferred and therefore allows for a relatively low band width communication channel.

Abstract: An arrangement and a method provide instruction processing. Instructions are delivered to a multi-stage pipeline arrangement from at least one instruction source. A storing arrangement stores jump address information for jump instructions. The storing arrangement includes at least one FIFO-register. The conditional jump target address information is stored in the FIFO-register while at least the jump instructions are stored in the pipeline arrangement. The jump target address information is delivered from the FIFO-register in such a way that substantially sequential and continuous prefetching of the instructions is enabled irrespective of the number of conditional jumps and irrespective of whether the jumps are taken or not.

Abstract: A method and apparatus for manipulating data in a storage device that is coupled to a host computer. Manipulations that can be performed by the storage device include moving non-contiguous blocks of data between the host computer and the storage device in a single operation. Other manipulations can be performed directly by the storage device without passing data to or from the host computer and include copying data from one logical object that is defined on the host computer to another, initializing, backing-up, transforming, or securely deleting a logical object that is defined by the host computer with a single command. In one embodiment, an application programming interface is provided that allows a relationship between logical objects on a host computer and storage locations on a storage device to be communicated between the host computer and the storage device.

Abstract: A cache memory control device enables an external instruction ROM to be co-owned by plural processors while minimizing the lowering of the processing performance of the processor and curtailing the number of external terminals of the LSIs. In a multi-processor system having a processor, an instruction RAM bank and an instruction RAM controller for each physical layer PHY, there is provided one instruction ROM for storing instruction data. The RAM controller of each PHY outputs time allowance information to a pre-fetch request of the instruction data. If there are simultaneously output pre-fetch requests from plural PHYs, the pre-fetch controller selects a pre-fetch request having the smallest time allowance.

Abstract: A storage unit comprises a plurality of storage modules, each of which is dynamically assigned to and used as each area in a main storage (MS) or an extended storage (ES). The storage unit or a system controller has address arrays for MS and for ES which store information indicating which of the storage modules comprised in the storage unit each area in the MS and the ES corresponds to. When the contents of the MS/ES address arrays are rewritten to change a storage module belonging to the ES to a storage module belonging to the MS, a page-in operation is realized without executing an actual data move operation. Similarly, a page-out operation is realized without executing an actual data move operation by changing a storage module belonging to the MS to a storage module belonging to the ES.

Abstract: Disclosed is a predictive instruction cache system, and the method it embodies, for a VLIW processor. The system comprises: a first cache; a real or virtual second cache for storing a subset of the instructions in the second cache; and a real or virtual history look-up table for storing relations between first instructions and second instructions in the second cache. If a first instruction is located in a stage of the pipeline, then one of the relations will predict that a second instruction will be needed in the same stage a predetermined time later. The first cache can be physically distinct from the second cache, but preferably is not, i.e., the second cache is a virtual array. The history look-up table can also be physically distinct from the first cache, but preferably is not, i.e., the history look-up table is a virtual look-up table. The first cache is organized as entries.

Abstract: A method for prefetching structured data, and more particularly a mechanism for observing address references made by a processor, and learning from those references the patterns of accesses made to structured data. Structured data means aggregates of related data such as arrays, records, and data containing links and pointers. When subsequent accesses are made to data structured in the same way, the mechanism generates in advance the sequence of addresses that will be needed for the new accesses. This sequence is utilized by the memory to obtain the data somewhat earlier than the instructions would normally request it, and thereby eliminate idle time due to memory latency while awaiting the arrival of the data.

Abstract: A method and apparatus for prefetching superblocks in a computer processing system having a fetch mechanism for fetching instructions for execution includes the step of controlling the fetch mechanism to begin fetching at a starting address of a current superblock. A superblock includes a set of instructions in consecutive address locations terminated by a branch instruction known to have been taken. A Superblock Target Buffer (STB) is supplied with the starting address of the current superblock. The STB has a plurality of entries each indexed by a starting address of a superblock and including a run length of the superblock and a target address of the terminating branch of the superblock. The run length corresponds to the sum of a length of the terminating branch and the difference between a starting address of the terminating branch of the superblock and the starting address of the superblock.

Abstract: The memory space accessible by a processor is partitioned such that multiple memory regions map to the same physical memory. Processor accesses in one of the regions are regarded as normal accesses, and are satisfied from the memory or a read buffer. If memory access is required, the processor is stalled until the desired data is returned from the memory. Processor accesses to the other region are regarded as requests to prefetch the data from the memory and place it into a read buffer without stalling the processor. The processor continues program execution while the data is being prefetched. At a later point in program execution, the processor requests the data via the first region. The data likely resides in the read buffer, and can therefore be provided to the processor quickly, resulting in improved performance.

Abstract: The invention relates to a process for accessing a storage area of a digital data processing machine (19) in a physical addressing mode the storage arena also being accessible in a virtual addressing mode by means of virtual addresses, each constituted by a logical page number (LPN) and a relative address (SPRA). A first logical page number (i) in question corresponds to a first given physical page number (q), and a second logical page number (i+1) contiguous to the first logical page number (i) in question corresponds to a second physical page number (s), not necessarily contiguous to the first given physical page number (q). The process is comprised of writing, at the address constituted by the first logical page number (i) in question and by a relative address having a first predetermined value, the second physical page number (s).

Abstract: A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is detected where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

Abstract: A method and system in a data storage system for reading stored data from the data storage system, where the data storage system comprises N data storage drives and an associated cache, where data and calculated parity are striped across the N data storage drives, where a stripe comprises multiple sectors on each of the N data storage drives. Data is requested from the data storage system. A determination is made of whether or not the requested data currently resides in a cache associated with the data storage system. In addition, a determination is made of whether or not the requested data sequentially follows other sectors also residing in the cache. Only the requested data is fetched into the cache if it is determined that the requested data does not reside in the cache and the requested data does not sequentially follow sectors in the cache.

Abstract: A microprocessor employs a branch prediction unit including a branch prediction storage which stores the index portion of branch target addresses and an instruction cache which is virtually indexed and physically tagged. The branch target index (if predicted-taken, or the sequential index if predicted not-taken) is provided as the index to the instruction cache. The selected physical tag is provided to a reverse translation lookaside buffer (TLB) which translates the physical tag to a virtual page number. Concatenating the virtual page number to the virtual index from the instruction cache (and the offset portion, generated from the branch prediction) results in the branch target address being generated. In one embodiment, the process of reading an index from the branch prediction storage, accessing the instruction cache, selecting the physical tag, and reverse translating the physical tag to achieve a virtual page number may require more than a clock cycle to complete.

Abstract: A processor is configured to generate lookahead values using a cumulative constant. The processor classifies operations to a particular register (e.g. the stack pointer register, or ESP in an embodiment employing the x86 instruction set architecture) as either accelerated or non-accelerated. For example, instructions which are defined to increment/decrement the particular register by an explicit or implicit constant value may be accelerated operations. Upon the occurrence of a non-accelerated operation, the processor may begin accumulating the cumulative effect of accelerated operations to the result of the non-accelerated operation as a cumulative offset. The result of the non-accelerated operation (upon execution thereof) may then be added to the cumulative offset values corresponding to each accelerated operation to generate the particular register value corresponding to that accelerated operation. Accordingly, dependencies upon the register due to the accelerated operations may be alleviated.

Abstract: A stacked map storage system has a base mapping of logical data to physical locations in the storage system. Level maps are created either as positive or negative maps of a lower level map. A positive map enables an alternate view while keeping the next lowest level map the same. A negative map allows changes to a lower level map but stores references to the data in itself so the negative map becomes a backup. Negative maps freeze storage in themselves and are read-only. A positive map allows changes to itself and can be used by applications under test to make changes, while not allowing changes to the next lower level map to be made through the positive map. In a preferred embodiment, maps can be stacked to any number of levels, can be shared by applications and hosts, and can either be deleted or merged. Deletion removes the map as though it never existed. A merge overlays an upper view onto a lower view and thus changes the lower view to match the other's state.

Abstract: A central processor uses virtual addresses to access data via cache logic including a DAT and ART, and the cache logic accesses data in the hierarchical storage subsystem using absolute addresses to access data, a part of the first level of the cache memory includes a translator for virtual or real addresses to absolute addresses. When requests are sent for a data fetch and the requested data are not resident in the first level of cache the request for data is delayed and may be forwarded to a lower level of said hierarchical memory, and a delayed request may result in cancellation of any process during a delayed request that has the ability to send back an exception. A delayed request may be rescinded if the central processor has reached an interruptible stage in its pipeline logic at which point, a false exception is forced clearing all I the wait states while the central processor ignores the false exception.

Abstract: A microprocessor (12) comprising a cache circuit (20) and circuitry (46, 48, 41, 56) for issuing a prefetch request. The prefetch request (82) comprises an address (82a) and requests information of a first size (82b) from the cache circuit. The microprocessor also includes prefetch control circuitry (22), which comprises circuitry for receiving the prefetch request and evaluation circuitry for evaluating system parameters corresponding to the prefetch request. Additionally, the prefetch control circuitry comprises circuitry, responsive to the evaluation circuitry, for determining a size of information for a prefetch operation starting at the address from the cache circuit, where the prefetch operation corresponds to the prefetch request.

Abstract: A superscalar microprocessor employing a data cache configured to perform store accesses in a single clock cycle is provided. The superscalar microprocessor speculatively stores data within a predicted way of the data cache after capturing the data currently being stored in that predicted way. During a subsequent clock cycle, the cache hit information for the store access validates the way prediction. If the way prediction is correct, then the store is complete, utilizing a single clock cycle of data cache bandwidth. Additionally, the way prediction structure implemented within the data cache bypasses the tag comparisons of the data cache to select data bytes for the output. Therefore, the access time of the associative data cache may be substantially similar to a direct-mapped cache access time. The superscalar microprocessor may therefore be capable of high frequency operation.

Abstract: A memory cache method and apparatus with two memory execution pipelines, each having a translation lookaside buffer (TLB). Memory instructions are executed in the first pipeline (324) by searching a data cache (310) and a prefetch cache (320). A large data TLB (330) provides memory for storing address translations for the first pipeline (324) A second pipeline (328) executes memory instructions by accessing the prefetch cache (320). A second micro-TLB (340) is associated with the second pipeline (328). It is loaded in anticipation of data that will be referenced by the second pipeline (328). A history file (360) is also provided to retain information on previous instructions to aid in deciding when to prefetch data. Prefetch logic (370) determines when to prefetch data, and steering logic (380) routes certain instructions to the second pipeline (328) to increase system performance.

Abstract: Apparatus, methods, and computer program products are disclosed that improve the operation of a computer that uses a top-of-stack cache by reducing the number of overflow and underflow traps generated during the execution of a program. The invention maintains a predictor value that controls the number of stack elements that are spilled from, or filled to, the top-of-stack cache in response to an overflow trap or an underflow trap (respectively). The predictor reflects the history of overflow traps and underflow traps.

Abstract: A data processing system is disclosed which comprises a data processor and memory control device for controlling the access of information from the memory. The memory control device includes temporary storage and decision ability for determining what order to execute the memory accesses. The compiler detects the requirements of the data processor and selects the data to stream to the memory control device which determines a memory access order. The order in which to access said information is selected based on the location of information stored in the memory. The information is repeatedly accessed from memory and stored in the temporary storage until all streamed information is accessed. The information is stored until required by the data processor. The selection of the order in which to access information maximizes bandwidth and decreases the retrieval time.

Abstract: In accordance with one aspect of the current invention, the system comprises a memory for storing instruction sequences by which the processor-based system is processed, where the memory includes a physical memory and a virtual memory. The system also comprises a processor for executing the stored instruction sequences. The stored instruction sequences include process acts to cause the processor to: map a plurality of predetermined instruction sequences from the physical memory to the virtual memory, determine an offset to one of the plurality of predetermined instruction sequences in the virtual memory, receive an instruction to execute the one of the plurality of predetermined instruction sequences, transfer control to the one of the plurality of predetermined instruction sequences, and process the one of the plurality of predetermined instruction sequences from the virtual memory.

Abstract: A computer processor that uses an AAHT to provide a guess at the real (absolute) address bits used to access the cache and directories that is more accurate in a high-frequency design which prevents any sort of full or large partial adds of ranges of base, index, or displacement has two index values generated and two AAHT arrays, one each for instruction and operand logical requests. It handles cases in which the data is not directly from the GPR array. For designs that aim at improving performance data for some operations that update GPR's may be used for address generation prior to the execution and write to the GPR array, these include data bypass for Load Address (LA) and Load (L). The system handles instruction fetches, relative branches, other special instruction address instruction fetch requests, and those started as a result of a branch history table (BHT) predicted instruction fetch.

Abstract: A data processing system and method thereof utilize a unique cache architecture that performs class prediction in a multi-way set associative cache during either or both of handling a memory access request by an anterior cache and translating a memory access request to an addressing format compatible with the multi-way set associative cache. Class prediction may be performed using a class predict data structure with a plurality of predict array elements partitioned into sub-arrays that is accessed using a hashing algorithm to retrieve selected sub-arrays. In addition, a master/slave class predict architecture may be utilized to permit concurrent access to class predict information by multiple memory access request sources. Moreover, a cache may be configured to operate in multiple associativity modes by selectively utilizing either class predict information or address information related to a memory access request in the generation of an index into the cache data array.

Abstract: A microprocessor includes an execution engine, a prediction table cache, and a prefetch controller. The execution engine is adapted to issue a memory request. The memory request includes an identifier corresponding to a row location in an external main memory. The prediction table cache is adapted to store a plurality of entries defining an access history of previously encountered memory requests. The prediction table cache is indexed by the identifier. The prefetch controller is adapted to receive the memory request and generate at least one prefetch candidate based on the memory request and the access history. A method for prefetching data in a microprocessor includes receiving a memory request. The memory request includes an identifier corresponding to a row location in an external main memory. The memory request is compared to an access history of previously encountered memory requests. The access history is indexed by the identifier.

Abstract: A digital system has a main memory 10 with a main memory access (DMA) unit 11 through which data channels 12, 13 are coupled to the memory. A processor system (processor 14, RAM data memory 15, instruction memory 16) is also coupled to the memory through a read/write buffer 20, each read stalling the processor for typically 5 cycles. For block reads, a block memory read unit 25 is connected in parallel with the path between the read/write buffer 20 and the DMA unit 11. This block read unit can be set from the processor 14 with a block start address and a block length passed as writes through the read/write buffer 20. The block is read (first phase) word by word from the main memory via the DMA unit into a memory 28 in the block read unit.

Abstract: A computer system, a cache memory and a process, supporting prefetch operations and cache access operations so as to store information duplicated from a high level memory for use by a processing device, the processing device issuing addresses, including prefetch addresses and cache access addresses. The cache memory comprises memory resources, and prefetch resources are coupled to the memory resources and to the processing device both for receipt and storage of prefetch addresses from the processing device and for injection management of the received prefetch addresses so as to coordinate prefetch operations with cache access operations. As for the process, the invention comprises the steps of receiving prefetch addresses issued by a processing device; providing for storing, in a prefetch memory, prefetch addresses; and providing for injecting prefetch addresses in a selected order from the prefetch memory for use in fetching, into the cache memory, information associated with the prefetch addresses.

Abstract: An information processing unit and method for controlling a cache according to a software prefetch instruction, are disclosed. Indicator or indication bits are provided for indicating a hierarchical level of a cache to which an operand data is to be transferred or a quantity of an operand data to be transferred, or both. The indication bits are provided in a software prefetch instruction such that at the time of a transfer of block data or line data, a required data is transferred to a cache based on the indication bits in the prefetch instruction. Thus, it is not necessary to change the timing for executing a software prefetch instruction depending on which one of the caches of the hierarchical levels is hit, and a compiler can generate an instruction sequence more easily.

Abstract: The present invention comprises a system for delivering an interactive multimedia work from a storage device, for example a hard disk drive, a CD-ROM drive, a network server, etc. to a playback device, for example a personal computer, in a manner that provides improved performance regardless of the playback sequence selected by a user. In one embodiment of the present invention, for each segment of an interactive multimedia work, a probability factor is assigned to each possible alternative succeeding segment. In addition a retrieval and delivery time cost factor is also assigned to each possible succeeding segment. In one embodiment of the invention, the time cost factor for each resource is assigned a fixed value. In another embodiment, the time cost factor is recalculated periodically to reflect changes in location and status of resources. The probability and time cost factor for each possible succeeding segment are combined to produce a relative priority ranking.

Abstract: Apparatus, methods, and computer program products are disclosed that improve the operation of a computer that uses a top-of-stack cache by reducing the number of overflow and underflow traps generated during the execution of a program. An exception history is maintained that tracks recent occurrences of overflow and underflow exception traps. This exception history is hashed with the address of the computer instruction that caused the exception to generate an index into a set of predictors. Thus, a predictor is used that is responsive to the current exception history of the top-of-stack cache.

Abstract: A method and an apparatus for position independent reconfiguration in a network of multiple context processing elements are provided. Wach multiple context processing element in a networked array of multiple context processing elements has an assigned physical identification. Virtual identifications may also be assigned to a number of the multiple context processing elements. Data is transmitted to at least one of the multiple context processing elements of the array, the data comprising control data, configuration data, an address mask, and a destination identification. The transmitted address mask is applied to either the physical or virtual identification and to a destination identification. The masked physical or virtual identification is compared to the masked destination identification.

Abstract: A microprocessor includes an instruction cache having a cache access time greater than the clock cycle time employed by the microprocessor. The instruction cache is banked, and access to alternate banks is pipelined. The microprocessor also includes a branch prediction unit. The branch prediction unit provides a branch prediction in response to each fetch address. The branch prediction predicts a non-consecutive instruction block within the instruction stream being executed by the microprocessor. Access to the consecutive instruction block is initiated prior to completing access to a current instruction block. Therefore, a branch prediction for the consecutive instruction block is produced as a result of fetching a prior instruction block. A branch prediction produced as a result of fetching the current instruction block predicts the non-consecutive instruction block, and the fetch address of the non-consecutive instruction block is provided to the instruction cache access pipeline.

Abstract: A cache memory control system includes a cache memory to store a copy of a subset of data which is stored in the main memory and a cache controller to control data caching and data replacement for the cache memory. Upon a cache miss, the cache controller replaces data in the cache memory with the read requested data and a plurality of data which are adjacent to that read requested data on a display screen.

Abstract: A method and apparatus for implementing a page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area and a page table walker. The page size storage area is used to store a number of page sizes each selected for translating a different set of virtual addresses. The page table walker includes a selection unit coupled to the page size storage area, as well as a page entry address generator coupled to the selection unit. For each of the virtual address received, the selection unit positions a field in that virtual address based on the page size selected for translating the set of virtual addresses to which that virtual address belongs.

Abstract: A microprocessor employs a branch prediction unit including a branch prediction storage which stores the index portion of branch target addresses and an instruction cache which is virtually indexed and physically tagged. The branch target index (if predicted-taken), or the sequential index (if predicted not-taken) is provided as the index to the instruction cache. The selected physical tag is provided to a reverse translation lookaside buffer (TLB) which translates the physical tag to a virtual page number. Concatenating the virtual page number to the virtual index from the instruction cache (and the offset portion, generated from the branch prediction) results in the branch target address being generated. In one embodiment, a current page register stores the most recently translated virtual page number and the corresponding real page number.

Abstract: A microprocessor employs a branch prediction unit including a branch prediction storage which stores the index portion of branch target addresses and an instruction cache which is virtually indexed and physically tagged. The branch target index (if predicted-taken, or the sequential index if predicted not-taken) is provided as the index to the instruction cache. The selected physical tag is provided to a reverse translation lookaside buffer (TLB) which translates the physical tag to a virtual page number. Concatenating the virtual page number to the virtual index from the instruction cache (and the offset portion, generated from the branch prediction) results in the branch target address being generated. In one embodiment, the process of reading an index from the branch prediction storage, accessing the instruction cache, selecting the physical tag, and reverse translating the physical tag to achieve a virtual page number may require more than a clock cycle to complete.

Abstract: Method for increasing data-processing speed in computer systems containing at least one microprocessor, a memory device, and a so-called cache connected to the processor, in which the cache is arranged to fetch data from the addresses in the memory device requested by the processor and then also fetches data from one or several addresses in the memory device not requested by the processor. The computer system includes a circuit called the stream-detection circuit, connected to interact with a cache such that the stream-detection circuit detects the addresses which the processor requests in the cache and registers whether the addresses requested already existed in cache. The stream-detection circuit is arranged such that it is made to detect one or several sequential series of addresses requested by the processor in the cache.

Abstract: A caching apparatus and method for enhancing retrieval of data from an optical storage device are provided. The apparatus preferably includes a first memory device for storing data therein. The first memory device preferably includes a predetermined application. An optical storage device is positioned in communication with the first memory device for optically storing data therein. The optical storage device includes a plurality of data storage sectors. A second memory device is positioned in communication with the first memory device for storing data. The second memory device preferably has a predetermined amount of data storage space. The predetermined amount of data storage space includes a caching space defined by only a portion of the predetermined amount of data storage space of the second memory device.

Abstract: A data processing system having a processor core 4, a memory management unit 6 and a cache memory 8 uses the memory management unit 6 to produce a confirm signal C that indicates that a memory access request will be processed no further, i.e. the outcome is fully determined. The next memory access request is initiated prior to this confirm signal C being available and accordingly if the confirm signal C indicates a result different to that predicted, then a stall of the system is required until the non-confirmed memory access request can be dealt with.

Abstract: An apparatus for performing speculative stores is provided. The apparatus reads the original data from a cache line being updated by a speculative store, storing the original data in a restore buffer. The speculative store data is then stored into the affected cache line. Should the speculative store later be canceled, the original data may be read from the restore buffer and stored into the affected cache line. The cache line is thereby returned to a pre-store state. In one embodiment, the cache is configured into banks. The data read and restored comprises the data from one of the banks which comprise the affected cache line. Instead of forwarding store data to subsequent load memory accesses, the store is speculatively performed to the data cache and the loads may subsequently access the data cache. Dependency checking between loads and stores prior to the speculative performance of the store may stall the load memory access until the corresponding store memory access has been performed.

Abstract: An improved method for loading a cache is described. The present invention monitors memory access to identify specific types of memory access, for example, requests to launch executable program code stored in a hard disk drive. The method maps the stored program code into a plurality of memory blocks. The memory block access during the launching of the executable program code is then profiled. When the computer remains idle for a predetermined time the profiling process is stopped. Alternatively, if the computer does not remain idle, for the predetermined time, the profiling process is stopped after a timeout period. The profile is then evaluated to identify the most frequently accessed memory blocks. A list of the most frequently accessed memory blocks is stored. The number of memory blocks stored in the list depends upon the size of the cache. The file access system is monitored to identify the next time that a profiled memory access process is initiated.

Abstract: A superscalar microprocessor employing a data cache configured to perform store accesses in a single clock cycle is provided. The superscalar microprocessor speculatively stores data within a predicted way of the data cache after capturing the data currently being stored in that predicted way. During a subsequent clock cycle, the cache hit information for the store access validates the way prediction. If the way prediction is correct, then the store is complete, utilizing a single clock cycle of data cache bandwidth. Additionally, the way prediction structure implemented within the data cache bypasses the tag comparisons of the data cache to select data bytes for the output. Therefore, the access time of the associative data cache may be substantially similar to a direct-mapped cache access time. The superscalar microprocessor may therefore be capable of high frequency operation.

Abstract: A method of providing programmable associativity in a cache used by a processor of a computer system is disclosed. A congruence class of a memory block is defined using a first mapping function, providing a first associativity level of the cache. A logic unit connected to the cache monitors cache misses as the cache uses the first associativity level, and selects other associativity levels based on the cache misses, using other mapping functions. The logic unit has incorporated therein means for selecting the other associativity levels based on a rate of the cache misses in a particular congruence class. The congruence class may be defined by associating the memory block with a particular set of cache blocks in the cache, based on a first portion of an address of the memory block, and the other mapping functions may be implemented by dividing the particular set into subsets and selecting a subset for the memory block based on a second portion of the address.

Abstract: An address limit violation detection circuit in a microprocessor-based computer system for eliminating delay between the generation of a definite limit violation (DLV) signal and the generation of a potential limit violation signal. The detection circuit includes a full adder circuit which is adapted to receive a linear address, a base address, and a limit value and further adapted to produce a plurality of sum bits and a plurality of carry bits in response thereto. The circuit further includes a DLV detection circuit adapted to receive the plurality of sum bits and carry bits from the full adder circuit and further adapted to produce a DLV signal in response thereto. The DLV signal is indicative of whether the linear address is greater than the sum of the base address and the limit value.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

Abstract: The present invention includes a computer system having an on-processor predictor tag array, an off-processor cache memory, and comparison circuitry. The on-processor predictor tag array contains first portions of tag information for multiple ways and multiple sets. The off-processor cache memory includes memory locations to store data and second portions of tag information. The comparison circuitry makes a first comparison of a first portion of an address with the first portions of tag information for the ways of one of the sets and uses results of the first comparison in predicting which of the ways, if any, correspond to the address. The comparison circuitry also makes a second comparison of the second portion of the address with sections of the second portions of tag information identified by the predicted way and the address.

Abstract: Index prediction is used to access data in a memory array. A virtual address is received at an input. The virtual address is translated to a physical address. The memory array is accessed at a predicted address. A portion of the predicted address is compared to a portion of the physical address. If the portion of the predicted address is different from the portion of the physical address, then the predicted address was an incorrect prediction. The memory array is accessed at the physical address.