Virtual Addressing Patents (Class 711/203)
  • Patent number: 10691600
    Abstract: Table of contents (TOC) pointer cache entry having a pointer for a range of addresses. An address of a called routine and a pointer value of a pointer to a reference data structure to be entered into a reference data structure pointer cache are obtained. The reference data structure pointer cache includes a plurality of entries, and an entry of the plurality of entries includes a stored pointer value for an address range. A determination is made, based on the pointer value, whether an existing entry exists in the reference data structure pointer cache for the pointer value. Based on determining the existing entry exists, one of an address_from field of the existing entry or an address_to field of the existing entry is updated using the address of the called routine. The stored pointer value of the existing entry is usable to access the reference data structure for the address range defined by the address_from field and the address_to field.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10678701
    Abstract: The presently disclosed subject matter includes various inventive aspects, which are directed to direct read access of a host computer device to a share storage space in a data storage system, as well as control of the direct read of the host computer device by a control computer device in the data storage system.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: June 9, 2020
    Assignee: Kaminario Technologies Ltd.
    Inventors: Eyal Gordon, Ilan Steinberg, Eli Malul, Shahar Salzman, Gilad Hitron, Eran Mann
  • Patent number: 10678702
    Abstract: The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the IOMMU. The controller then performs the virtual address to physical address translations using the one or more selected memory elements.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: June 9, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Sergey Blagodurov, Andrew G. Kegel
  • Patent number: 10678452
    Abstract: A method of distributed file deletion, performed by a storage system, is provided. The method includes receiving, at the storage system, a request to delete a directory and contents of the directory and adding the directory to a first set, listed in a memory in the storage system. The method includes operating on the first set, by examining each directory in the first set to identify subdirectories, adding each identified subdirectory to the first set as a directory, and adding each examined directory to a second set listed in the memory. The method includes deleting in a distributed manner across the storage system without concern for order, contents of directories, and the directories, listed in the second set.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: June 9, 2020
    Assignee: Pure Storage, Inc.
    Inventors: Ronald Karr, Robert Lee, Igor Ostrovsky
  • Patent number: 10673947
    Abstract: A computerized method for enabling a client device seamless access to a plurality of remote storage devices connected to the client device via a communication network. The method comprises receiving a plurality of physical addresses by a controller communicatively coupled to the client device and to a plurality of storage servers, each of the plurality of storage servers communicatively coupled to at least one storage device, the plurality of physical addresses enabling access by the controller to the remote storage devices. A single virtual storage device having a logical address space is generated on the device, wherein each of the plurality of physical addresses is mapped by the controller to a unique logical address of the virtual storage device.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: June 2, 2020
    Assignee: Excelero Storage Ltd.
    Inventors: Yaniv Romem, Omri Mann, Ofer Oshri
  • Patent number: 10664367
    Abstract: A computer-implemented method, according to one embodiment, includes: determining that a data storage drive in a first array has failed, determining a location to rebuild the failed data storage drive, instructing performance of a rebuild operation at the determined location, determining one or more data storage drives in one or more arrays having a combined amount of available space that is sufficient to mirror data and/or parity information of the first array, instructing mirroring of the data and/or parity information of the first array in parallel with performing the rebuild operation, instructing deletion of the mirrored data and/or parity information of the first array from the one or more data storage drives in response to the rebuild operation being completed, and instructing reallocation of the space in the one or more data storage drives used to mirror the data and/or parity information of the first array as available space.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Gary Anna, Emmanuel Barajas Gonzalez, Shaun E. Harrington, Harry R. McGregor, Christopher B. Moore
  • Patent number: 10664410
    Abstract: In example implementations, mapping fields and respective operation fields may be stored in a translation lookaside buffer (TLB) of a central processing unit (CPU) that is communicatively coupled to a storage volume. The operation fields may be populated based on processes, running on the CPU, corresponding to the respective mapping fields. In response to a storage volume access request generated by one of the processes, and based on contents of one of the mapping fields that matches the storage volume access request, a memory address corresponding to a memory location in the storage volume may be identified. A translated address based on the identified memory address, and contents of the respective operation field, may be transmitted to a media controller communicatively coupled to the CPU and the storage volume.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: May 26, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B Lesartre, Derek Alan Sherlock, Russ W Herrell
  • Patent number: 10652327
    Abstract: The present subject matter relates to migrating a virtual machine (VM) from a source server to a destination server. The migration involves computation of a suitability score for each particular server in the plurality of candidate servers. The suitability score for a server indicates the suitability of the server to host the VM. In an example implementation, the suitability score for a server is computed based on satisfaction of at least one criterion for operation of the VM by the server.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: May 12, 2020
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Murali Nidugala, Kalapriya Kannan, Hariharan Krishna
  • Patent number: 10642539
    Abstract: The present disclosure discloses a read/write path determining method and apparatus. The method is used by a physical host. The method includes: obtaining, by the host, a first read/write request of the virtual machine, where the first read/write request includes a first virtual address, searching for the first virtual address in an address translation information set, and determining to process the first read/write request by using the block device or the virtual block device according to the address translation information set and the first virtual address. According to the method and apparatus, an appropriate read/write path is determined according to a read/write request and an address translation information set, so that both storage performance and a storage function can be considered.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 5, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Canquan Shen
  • Patent number: 10635417
    Abstract: Various embodiments are generally directed to techniques for compiler sheltered nonvolatile memory (NVM) stores, such as based on demarcated atomic persistence regions in source code, for instance. Some embodiments are particularly related to a compiler that effectively shelters updates to NVM-based variables in a compiler implemented register, or register file, until the compiler has recorded undo values into a temporary but nonvolatile log range.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: April 28, 2020
    Assignee: INTEL CORPORATION
    Inventors: Bhanu Shankar, Kshitij Doshi
  • Patent number: 10635823
    Abstract: Technologies are provided in embodiments for using compiling techniques to harden software programs from branching exploits. One example includes program instructions for execution to obtain a first encoded instruction of a software program, the first encoded instruction including a first opcode in a first field to be performed when the first encoded instruction is executed, identify a vulnerable value in a second field within the first encoded instruction, where the vulnerable value includes a second opcode, determine that the first encoded instruction can be replaced with one or more alternative encoded instructions that do not contain the vulnerable value, and replace the first encoded instruction with the one or more alternative encoded instructions.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Daniel Fernando Gutson, Vadim Sukhomlinov, Dmitry Yurievich Babokin, Alex Nayshtut
  • Patent number: 10628349
    Abstract: An I/O control method and system for respectively achieving both acceleration of I/O processing and redundantization of data. The present invention is based upon an I/O control method of performing control related to an I/O request from a virtual machine operated in a computer provided with an I/O device that executes I/O processing, and the I/O control method includes a first step in which an I/O analysis unit determines whether or not data redundantization processing related to the I/O request is executed on the basis of the I/O request from the virtual machine and setting information for enabling identifying whether or not the data redundantization processing is executed and a second step in which a control unit transmits an I/O command related to the I/O request to a data redundantization mechanism that executes the data redundantization processing on the basis of a determination result in the first step.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: April 21, 2020
    Assignee: HITACHI, LTD.
    Inventors: Kazuhiko Mizuno, Ken Sugimoto, Hiroaki Akutsu, Naoya Okada, Keitaro Uehara
  • Patent number: 10599580
    Abstract: A computer-implemented method according to one embodiment includes identifying a data write to a specific position within a virtual address space, determining an entry within a metadata structure that corresponds to the specific position within the virtual address space, and adding state information associated with the data write to the entry within the metadata structure, the state information including a size of the data write within the virtual address space and an alignment of the data write within the virtual address space.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yosef Shatsky, Asaf Porat-Stoler
  • Patent number: 10599582
    Abstract: A virtual-to-virtual page table maps a main surface containing the actual data and a metadata or auxiliary surface that gives information about compression of the main surface. In order to access the metadata that corresponds to main surface, an additional virtual-to-virtual table may be used ahead of the regular page table mapping to avoid the need to pass the metadata base address and x, y coordinates across a pipeline which may result in multiple memory writes.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Vidhya Krishnan, Niranjan L. Cooray, Murali Ramadoss
  • Patent number: 10593305
    Abstract: A display controller for a data processing system includes a memory read sub-system operable to read data of input surfaces to be used as input layers to be processed by the display controller. The memory read sub-system is operable to request in advance the loading of memory address translation data into a memory address translation data cache for memory pages storing data relating to an input surface. The memory read sub-system selects the memory pages that it requests the advance loading of address translation data for based on information relating to the data for the input surface that will be required by the display controller to generate the output surface, such as the vertical and horizontal size of the input layer that the input surface will be used for, an indication of any flipping or rotation of the input surface, etc.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: March 17, 2020
    Assignee: Arm Limited
    Inventors: Michal Karol Bogusz, Damian Piotr Modrzyk, Quinn Carter, Thomas James Cooksey
  • Patent number: 10585805
    Abstract: A computing device that handles address translations is described. The computing device includes a hardware table walker and a memory that stores a reverse map table and a plurality of pages of memory. The table walker is configured to use validated indicators in entries in the reverse map table to determine if page accesses are made to pages for which entries are validated. The table walker is further configured to use virtual machine permissions levels information in entries in the reverse map table determine if page accesses for specified operation types are permitted.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: March 10, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: David A. Kaplan, Jeremy W. Powell, Thomas R. Woller
  • Patent number: 10572152
    Abstract: Disclosed herein are a memory device and a method of operating the memory device. The memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell may a plurality of main memory blocks and a plurality of sub-memory blocks included in each of the main memory blocks. The peripheral circuit may perform a program operation on the main memory blocks or the sub-memory blocks, detect an amount of data loaded for the program operation, and output data amount information. The control logic may control the peripheral circuits so that, during the program operation, at least one memory block is selected from the main memory blocks or from the sub-memory blocks according to the data amount information and the program operation is performed on the selected memory block.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: February 25, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10558395
    Abstract: A memory system having multiple memory layers includes a first memory layer comprising a volatile memory, a second memory layer comprising a first sub-memory and a second sub-memory. In response to a reference failure that occurred in the first memory layer, to which a read reference failed data and a write reference failed data are respectively loaded from a lower level memory layer.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: February 11, 2020
    Assignee: SEJONG UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATION
    Inventor: Gi Ho Park
  • Patent number: 10552172
    Abstract: An example method of provisioning a virtual appliance to a virtualized computing system, comprising: deploying the virtual appliance to the virtualized computing system, the virtual appliance including a system partition, one or more disk images, and configuration data, the configuration data defining a virtual machine executable on each of a plurality of processor architectures, the system partition configured to boot on any one of the plurality of processor architectures; and booting the virtual appliance from the system partition.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: February 4, 2020
    Assignee: VMware, Inc.
    Inventors: Ye Li, Cyprien Laplace, Andrei Warkentin, Alexander Fainkichen, Regis Duchesne
  • Patent number: 10547737
    Abstract: Agencies issue recording devices to personnel for administrating and monitoring controlled calls during the course of their duties. To provide flexible capabilities to agencies, a virtual number is provisioned and configured to enable an operator to administrate controlled calls without dedicated recording devices. Using the virtual number, the operator may setup a controlled call between a victim and a baddie. The victim is contacted via the virtual number by the operator and optionally informed about the controlled call process. In turn, the baddie is contacted using number information of the victim's phone and connected with the victim. Call audio between the victim and baddie is transmitted to the operator. When necessary, the operator may terminate the call remotely from the telephonic device the operator used to setup the call.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: January 28, 2020
    Assignee: World Emergency Network—Nevada, Ltd.
    Inventor: Christopher Ryan Bennett
  • Patent number: 10528735
    Abstract: Various approaches are described herein for, among other things, detecting and/or neutralizing attacks by malicious code. For example, instance(s) of a protected process are modified upon loading by injecting a runtime protector that creates a copy of each of the process' imported libraries and maps the copy into a random address inside the process' address space to form a “randomized” shadow library. The libraries loaded at the original address are modified into a stub library. Shadow and stub libraries are also created for libraries that are loaded after the process creation is finalized. Consequently, when malicious code attempts to retrieve the address of a given procedure, it receives the address of the stub procedure, thereby neutralizing the malicious code. When the original program's code (e.g., the non-malicious code) attempts to retrieve the address of a procedure, it receives the correct address of the requested procedure (located in the shadow library).
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: January 7, 2020
    Assignee: Morphisec Information Security 2014 Ltd.
    Inventors: Michael Gorelik, Mordechai Guri, David Mimran, Gabriel Kedma, Ronen Yehoshua
  • Patent number: 10509728
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receive a request from a core, the request associated with a memory operation to read or write data, and the request comprising a first address and an offset, the first address to identify a memory location of a memory. Embodiments include performing a first iteration of a memory indirection operation comprising reading the memory at the memory location to determine a second address based on the first address, and determining a memory resource based on the second address and the offset, the memory resource to perform the memory operation for the computing resource or perform a second iteration of the memory indirection operation.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 17, 2019
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Mark Schmisseur, Thomas Willhalm
  • Patent number: 10474580
    Abstract: Methods, systems, and apparatus for receiving a request to access, from a main memory, data contained in a first portion of a first page of data, the first page of data having a first page size; initiating a page fault based on determining that the first page of data is not stored in the main memory; allocating a portion of the main memory equivalent to the first page size; transferring the first portion of the first page of data from the secondary memory to the allocated portion of the main memory without transferring the entire first page of data; and updating a first page table entry associated with the first portion of the first page of data to point to a location of the allocated portion of the main memory to which the first portion of the first page of data is transferred.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: November 12, 2019
    Assignee: Google LLC
    Inventors: Joel Dylan Coburn, Albert Borchers, Christopher Lyle Johnson, Robert S. Sprinkle
  • Patent number: 10423478
    Abstract: Systems and methods that enable user space processing threads to handle hardware events (e.g., page faults) for another processing thread in a security-enhanced manner. An example method may comprise: associating, by a processing device executing a kernel, a first processing thread with a storage unit of a second processing thread; detecting, by a processing device, a hardware event corresponding to an address of the storage unit; determining a storage object comprising data of the storage unit; translating the address of the storage unit to an offset of the storage object; and transmitting, by the kernel, a notification of the hardware event to the first processing thread, wherein the notification comprises the offset.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: September 24, 2019
    Assignee: Red Hat, Inc.
    Inventors: Michael Tsirkin, Andrea Arcangeli, David Alan Gilbert
  • Patent number: 10416890
    Abstract: Apparatuses, methods and storage medium associated with application execution enclave cache management, are disclosed herein. In embodiments, an apparatus may include one or more processors with supports for application execution enclaves; cache memory coupled with the one or more processors to be organized into a plurality of cache pages; and an exception handler to be operated by the one or more processors to handle cache page fault exceptions, wherein to handle cache page fault exceptions includes to handle a cache page fault triggered to request additional allocation of one or more cache pages to an execution enclave of an application. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Bin Xing, Mark W. Shanahan, Bo Zhang
  • Patent number: 10409736
    Abstract: A first data storage device may be connected to first and second entities as part of a distributed network with each entity having direct block level access to logical block addresses of the first data storage device. The first data storage device can consist of a provisioning module and a staging buffer with the provisioning module configured to store and acknowledge non-volatile write data in the staging buffer in response to a write request to any logical block address of a range of logical block addresses in the first data storage device. The provisioning module may return previously committed data resident in the range of logical block addresses instead of the write data resident in the staging buffer until a commit signal is received from at least one entity for the write data.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: September 10, 2019
    Assignee: Seagate Technology LLC
    Inventor: Thomas Roy Prohofsky
  • Patent number: 10402355
    Abstract: An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: September 3, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Brian Karguth, Chuck Fuoco, Chunhua Hu, Todd Christopher Hiers
  • Patent number: 10394596
    Abstract: An identification of one or more memory pages that are associated with the guest operating system may be received by a hypervisor and from a guest operating system. The hypervisor may receive a request from the guest operating system to initiate a tracking operation for the one or more memory pages. The tracking operation may be initiated for the one or more memory pages in response to receiving the request from the guest operating system. Furthermore, the one or more memory pages may be freed in view of the tracking operation that has been initiated by the hypervisor.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: August 27, 2019
    Assignee: Red Hat, Inc.
    Inventors: Michael Tsirkin, Henri Han van Riel
  • Patent number: 10380012
    Abstract: The inventive concept pertains to a computer-implemented method by which an application, an operating system, and hardware communicate with one another. The method entails the application converting an application-level virtual address to a physical address and communicating the physical address to the operating system. The operating system then uses the physical address to determine OS-level virtual address and complete the data transfer.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: August 13, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Manoj K Guthula, Venkata Bhanu Prakash Gollapudi
  • Patent number: 10372563
    Abstract: Disclosed are an analyzing system for managing an information storage table and a control method thereof. That is, each of the physical basic regions, which are units of hashing an information storage position, is divided into a plurality of physical sub regions having same size. Then, a combination of virtual basic regions which satisfy a predetermined target value is checked from all configurable combinations and a hash value related with the combination of the virtual basic regions which satisfies the checked target value is stored in a predetermined region of a memory. Therefore, even though an information storage space required for every unit region is overloaded, when there is an extra information storage space in another region, the information storage space having an extra space is used to maximize efficiency of the information storage space.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: August 6, 2019
    Assignee: Korea University Research and Business Foundation
    Inventors: Seon Wook Kim, Ho Kwon Kim, Jae Yung Jun, Young Sun Han
  • Patent number: 10359965
    Abstract: An apparatus in one embodiment comprises a storage system having a plurality of storage devices configured to store at least a first set of data. The storage system is configured to generate a first signature for the first set of data and to verify equivalence between the first set of data and a second set of data by comparing the first signature to a second signature generated for the second set of data. The first and second sets of data comprise respective first and second sets of pages with each page having a content-based page identifier and a page address, and the first and second signatures are generated as respective functions of the page identifiers and page addresses of the respective first and second sets of pages. The first and second sets of data may comprise respective first and second storage volumes, respective first and second sets of multiple storage volumes, or other sets of data.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: July 23, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: William Stronge, David Meiri
  • Patent number: 10348822
    Abstract: In accordance with an embodiment, described herein is a system and method for supporting clustering in a multitenant application server environment. The system includes a domain with a plurality of server clusters, and a plurality of partitions, wherein each cluster is homogenously configured and targeted by one or more partitions. An application programming interface (API) can be used to initiate a resource group across-cluster migration within a partition. The API can invoke a replication manager, which queries a target cluster for a runtime topology for use in determining where to store primary session; migrates the primary session to a determined server instance in the target cluster. Additional clustering features, such as cluster messaging service, leasing service, singleton service management, session replication, clustered JNDI, and use of domain front-end load balancing, can be supported.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 9, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Lenny Phan, Mohamed Abdelaziz, Rajiv Mordani, Nazrul Islam
  • Patent number: 10346330
    Abstract: Systems and methods for directly updating the virtual machine memory by interrupt handlers. An example method may comprise: receiving, by a computer system, an interrupt triggered by a physical device; receiving, by an interrupt handling routine, a data frame from the physical device; identifying a virtual machine to receive the interrupt; and responsive to determining that an active memory context on the computer system matches a memory context of the virtual machine, writing, by the interrupt handling routine, the data frame into a memory of the virtual machine.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: July 9, 2019
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Henri Han van Riel
  • Patent number: 10324774
    Abstract: Provided is a kernel program and so on capable of enhancing the confidentiality of data memorized in a storage device without using a file system on an OS kernel level. The kernel program is mounted on a computer operable to input and output data between an application program and a storage device, and causes the computer to function as: a socket establisher establishing a socket for connecting with the application program; a relational database operable to input and output data from/to the storage device through a device driver; and an access controller inputting a command from the application program through a message structure of the socket then to output the command to the relational database and inputting an execution result from the relational database then to output the execution result through a message structure of the socket to the application program.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: June 18, 2019
    Assignees: NEXTY ELECTRONICS CORPORATION, TAKEOKA LAB CORP.
    Inventors: Kiyokazu Ikeda, Shozo Takeoka, Takamichi Kono
  • Patent number: 10310990
    Abstract: In one example in accordance with the present disclosure, a method may include retrieving, at a memory management unit (MMU), encrypted data from a memory via direct memory access and determining, at the MMU, a peripheral that is the intended recipient of the encrypted data. The method may also include accessing an application key used for transmission between an application and the peripheral, wherein the application key originates from the application and decrypting, at the MMU, the encrypted data using the application key and transmitting the decrypted data to the peripheral.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: June 4, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Adrian Shaw, Geoffrey Ndu, Fraser John Dickin
  • Patent number: 10303543
    Abstract: A system and method are provided to control error-protected access to a memory device having address integrity protection for data words of memory transactions. A communication port receives a command having a port address, which is adaptively converted to a memory address by an interface portion. The interface portion includes an adaptation stage carrying out a predefined adaptation response on an address propagated therethrough during a clock cycle of operation. An address protection portion configures the adaptation stage to maintain the predefined adaptation response over at least two clock cycles. Address error is detected based on comparison of output addresses respectively generated upon iterative propagation of the same input address through the adaptation stage over the clock cycles. A command control portion executes to adaptively split each command received from the interface portion, as well as the corresponding memory address according to an inline storage configuration of the memory device.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: May 28, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: John M. MacLaren
  • Patent number: 10303595
    Abstract: The present invention relates to a dynamic memory management method which includes generating an N-dimensional memory address space in which coordinates are in a range of N natural numbers, the sum of which is the number of bits; and mapping a predetermined linear memory address region to an address region in the N-dimensional memory address space.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: May 28, 2019
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Ik Soon Kim
  • Patent number: 10303380
    Abstract: In one embodiment, a computer program product for managing a reserve command includes a computer readable storage medium having program code embodied therewith, the program code readable and/or executable by a processor to receive, by the processor, a request to access a data set on one or more volumes of at least one direct access storage device (DASD), the request including a reserve command, and each of the one or more volumes including a consecutive set of one or more tracks of the at least one DASD, and reserve one or more extents of the at least one DASD while reserving less than a volume of the at least one DASD and not allowing any other entity than an entity which requested the reserve to access the one or more extents of the at least one DASD that have been reserved.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Susan K. Candelaria, Clint A. Hardy, Gavin S. Johnson, Matthew J. Kalos, Michael J. Koester, John R. Paveza, Carrie J. Van Noorden
  • Patent number: 10289561
    Abstract: A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 14, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Elona Erez, Avner Dor, Jun-Jin Kong
  • Patent number: 10289435
    Abstract: The described implementations relate to virtual computing techniques. One implementation provides a technique that can include receiving a request to execute an application. The application can include first application instructions from a guest instruction set architecture. The technique can also include loading an emulator and a guest operating system into an execution context with the application. The emulator can translate the first application instructions into second application instructions from a host instruction set architecture. The technique can also include running the application by executing the second application instructions.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: May 14, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Barry C. Bond, Reuben R. Olinsky, Galen C. Hunt
  • Patent number: 10289418
    Abstract: Techniques are provided for handling a trap encountered in a thread that is part of a thread array that is being executed in a plurality of execution units. In these techniques, a data structure with an identifier associated with the thread is updated to indicate that the trap occurred during the execution of the thread array. Also in these techniques, the execution units execute a trap handling routine that includes a context switch. The execution units perform this context switch for at least one of the execution units as part of the trap handling routine while allowing the remaining execution units to exit the trap handling routine before the context switch. One advantage of the disclosed techniques is that the trap handling routine operates efficiently in parallel processors.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: May 14, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Gerald F. Luiz, Philip Alexander Cuadra, Luke Durant, Shirish Gadre, Robert Ohannessian, Lacky V. Shah, Nicholas Wang, Arthur Danskin
  • Patent number: 10284519
    Abstract: When requesting network services, clients often supply authentication information such as digital signatures. A network provider may from time to time change its authentication scheme. Clients are notified of the change and are provided with an updated authentication specification. Upon receiving the updated authentication specification, a client updates its authentication logic accordingly, and subsequently prepares and provides authentication information in accordance with the new authentication scheme.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: May 7, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Eric J. Brandwine, Peter N. DeSantis
  • Patent number: 10282373
    Abstract: Embodiments are directed towards managing pushed vitality updates of recent user-generated content (UGC). A vitality service is arranged to receive pushed vitality updates that each include a resource identifier and at least one other type of vitality information referring to recent UGC on a network device. The vitality service is configured to manage the pushed vitality updates according to recency and to receive query requests for vitality information. In response to a query request, the vitality service searches for vitality updates and provides to another network device recent vitality information based on the query request. The recent vitality information includes at least one or more resource identifiers and one or more other types of vitality information so that the other network device can access the full UGC for display.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: May 7, 2019
    Assignee: EXCALIBUR IP, LLC
    Inventors: Michael Tadlock, Tom Quiggle
  • Patent number: 10275187
    Abstract: A memory device is provided. A processor accesses non-volatile memories via channels and generates a status table according to at least one command of a command queue. The status table records a plurality of tasks. Each task corresponds to one read status and one channel number. The processor selects a plurality of specific tasks from the tasks to serve as a first task set and simultaneously performs all the selected specific tasks with different channel numbers. When the read status of a first specific task matches a first predetermined status, the processor retrieves a logical-to-physical address mapping table relating to the logical address of the first specific task. When the read status of the first specific task matches a second predetermined status, the processor retrieves data relating to the logical address of the first specific task.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: April 30, 2019
    Assignee: Silicon Motion, Inc.
    Inventor: Yu-Chih Lin
  • Patent number: 10275306
    Abstract: A system and method are provided for controlling access to a memory device having adaptively split addressing of error-protected data words according to an inline memory storage configuration. An address translation section executes to convert a data address associated with a received command to inline data and inline error checking addresses corresponding thereto. Each data word's data and error checking bits are stored according to respective inline data inline error checking addresses. A segment of error checking bits is thereby offset in address from at least one segment of the same data word's data bits in a common chip of the memory device. A command translation section executes to convert between a received command to data access and error checking access commands for actuating respective access operations on the memory device. An error checking storage section intermediately stores error checking bits responsive to execution of the error checking access command.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: April 30, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: John MacLaren, Carl Olson, Jerome J. Johnson, Thomas J. Shepherd
  • Patent number: 10261840
    Abstract: Aspects include allocating virtual resources to physical resources in a computer environment and aggregating the virtual resources, as a virtual resource pool, at a per virtual machine level in the computer environment. Other aspects include evaluating the virtual resources in the virtual resource pool against resource pool domain constraints. Other aspects include determining a resource allocation adjustment as a function of the evaluating. The resource allocation adjustment is configured to achieve a maximum specified virtual machine density. Other aspects include adjusting the virtual resources based on the resource allocation adjustment.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Simon J. Kofkin-Hansen, Richard T. Lemelin, Setareh Mehrabanzad, Shawn P. Raess
  • Patent number: 10254963
    Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a data stream including one or more data blocks; determine a size of the one or more data blocks; determine a number of mappings needed for a physical block based on the size of a data block and a size of the physical block, the number of mappings being variable for different physical blocks depending on the size of the one or more data blocks storing in the physical block; retrieve a dynamically sized reverse map, the dynamically sized reverse map being a dynamic tree structure; determine a starting location in the dynamically sized reverse map for mappings of the one or more data blocks; and create an entry for the physical block in the dynamically sized reverse map.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: April 9, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sandeep Sharma, Saurabh Manchanda
  • Patent number: 10248448
    Abstract: Methods, computer-readable storage medium, and systems described herein facilitate provisioning a virtual desktop infrastructure having virtual shared storage. A provisioning manager receives a desktop pool type and provisions virtual shared storage among a cluster of hosts. The provisioning manager configures the virtual shared storage based on the desktop pool type and provisions at least one virtual machine to each host in the cluster of hosts. The provisioning manager optimizes the virtual shared storage by receiving a storage performance benchmark from each host and performing an optimization on the cluster of hosts if the storage performance benchmark results do not meet a threshold within a pre-defined tolerance.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: April 2, 2019
    Assignee: VMware, Inc.
    Inventor: Daniel James Beveridge
  • Patent number: 10242124
    Abstract: In a memory, multiple pieces of entry data sorted in ascending or descending order are stored associated with addresses. With whole addresses for storing the multiple pieces of entry data as an initial search area, the search circuit repeatedly performs a search operation for comparing entry data stored in a central address of the search area with the search data, outputting the address as a search result in the case of a match, and narrowing the search area for the next search based on a magnitude comparison result in the case of a mismatch.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: March 26, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tsutomu Makino
  • Patent number: 10241841
    Abstract: Aspects include allocating virtual resources to physical resources in a computer environment and aggregating the virtual resources, as a virtual resource pool, at a per virtual machine level in the computer environment. Other aspects include evaluating the virtual resources in the virtual resource pool against resource pool domain constraints. Other aspects include determining a resource allocation adjustment as a function of the evaluating. The resource allocation adjustment is configured to achieve a maximum specified virtual machine density. Other aspects include adjusting the virtual resources based on the resource allocation adjustment.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Simon J. Kofkin-Hansen, Richard T. Lemelin, Setareh Mehrabanzad, Shawn P. Raess