Abstract: In accordance with described techniques for processing-in-memory (PIM) search stop control, a computing system or computing device includes a memory system that includes a stop condition check component, which receives an instruction that includes a programmed check value. The stop condition check component compares the programmed check value to outputs of a PIM component, and the stop condition check component initiates a stop instruction to stop the PIM component from processing subsequent computations based on an output of the PIM component matching the programmed check value.

Abstract: An embodiment may involve receiving, at a web server application, a query specifying a file, a block number of a block of data within the file, and a block size, wherein the file includes entries representing differences between snapshots of configuration data; identifying, based on the block size, the block of data within the file; storing the block in a non-transitory memory that is accessible to the web server application; and in response to the query, transmitting, by the web server application, a set of the entries within the block formatted for display in a list component of a graphical user interface.

Abstract: Adaptive scheduling of memory requests and processing-in-memory requests is described. In accordance with the described techniques, a memory controller receives a plurality of processing-in-memory requests and a plurality of non-processing-in-memory requests from a host. The memory controller schedules an order of execution for the plurality of processing-in-memory requests and the plurality of non-processing-in-memory requests based at least in part on a processing-in-memory request stall threshold and a non-processing-in-memory request stall threshold. In response to a system switching (e.g., from executing processing-in-memory requests to executing non-processing-in-memory requests or from executing non-processing-in-memory requests to executing processing-in-memory requests), the memory controller modifies the processing-in-memory request stall threshold and the non-processing-in-memory request stall threshold.

Abstract: A memory system comprising: a memory device having a nonvolatile specific storage space configured to store workload information including groups of parameter values, grouped respectively corresponding to a plurality of workload classes in a table form, and a controller configured to detect a ratio of a set command inputted from an outside in a set operation mode, select one of the workload classes as a detected class, load, from the specific storage space, one of the groups corresponding to the detected class, process the set command under an execution condition determined by applying the loaded group, and update the group corresponding to the detected class with parameter values inputted from the outside.

Abstract: A hardware-based processing node of an object memory fabric can comprise a memory module storing and managing one or more memory objects within an object-based memory space. Each memory object can be created natively within the memory module, accessed using a single memory reference instruction without Input/Output (I/O) instructions, and managed by the memory module at a single memory layer. The memory module can provide an interface layer below an application layer of a software stack. The interface layer can comprise one or more storage managers managing hardware of a processor and controlling portions of the object-based memory space visible to a virtual address space and physical address space of the processor. The storage managers can further provide an interface between the object-based memory space and an operating system executed by the processor and an alternate object memory based storage transparent to software using the interface layer.

Abstract: In some aspects, a non-transitory computer readable storage medium includes instructions stored thereon that, when executed by a processor, cause the processor to create a virtual swap space that is exposed to a core system software, intercept a first page selected by the core system software to be swapped out to the virtual swap space, map the virtual swap space to a physical swap space that is allocated to a type of page associated with first swap metadata, and write the first page to the physical swap space based on the first page having the first swap metadata. In some embodiments, the first page is associated with the first swap metadata.

Abstract: A method of memory allocation in a host computer includes: allocating one or more regions of physical working memory for use by an application, the regions individually including contiguous physical memory segments, but the regions not necessarily being contiguous between themselves; generating a segment address table having at least as many entries as the total number of physical memory segments allocated to the application; populating entries of the segment address table sequentially and contiguously with the physical addresses of the physical memory segments across the or each region in order; presenting to the application a contiguous virtual addressable space having at least as many virtual memory segments as the total number of physical memory segments allocated to the application; and mapping from virtual memory addresses to physical memory addresses by reference to the segment address table.

Abstract: Synchronizing metadata among storage systems synchronously replicating a dataset, where synchronizing the metadata includes: receiving, at a first storage system of the storage systems, an I/O operation directed to the dataset; determining, in dependence upon the I/O operation, a metadata update describing a mapping of segments of content to a virtual address within a storage object, wherein the storage object includes the dataset; and synchronizing metadata on a second storage system of the storage systems by sending the metadata update to the second storage system to update a metadata representation on the second storage system in accordance with the metadata update.

Abstract: Provided are a method for operating a storage driver in a container environment and a storage driver apparatus and a method for operating a storage driver according to an exemplary embodiment of the present disclosure includes: requesting downloading of an image for running a container; downloading a plurality of sub images associated with the requested image; allocating each of the plurality of downloaded sub images to an independent logical volume in a multi-layer based file system; and running a container using each of the plurality of allocated sub images.

Abstract: This document describes techniques for storing virtual disk payload data. In an exemplary configuration, each virtual disk extent can be associated with state information that indicates whether the virtual disk extent is described by a virtual disk file. Under certain conditions the space used to describe a virtual disk extent can be reclaimed and state information can be used to determine how read and/or write operations directed to the virtual disk extent are handled. In addition to the foregoing, other techniques are described in the claims, figures, and detailed description of this document.

Abstract: A storage system having high performance and high reliability includes a non-volatile storage device, a storage controller configured to control data to be read and written from and to the storage device using a storage function; and a volatile memory. In the reading and writing, the storage controller generates a log and stores the log in a log memory, writes the log stored in the memory to the storage device, and collects a capacity of the storage area of the memory storing the log written to the storage device. In collecting a free area of the memory, the storage controller executes a base image saving method of writing in the storage device in units of storage areas having a plurality of logs and collecting a free area, and a garbage collection method of writing in the storage device in units of logs and collecting a free area.

Abstract: A method, apparatus, and system for performing a Location SLO check based on a location scatter table is disclosed. A location scatter table is maintained, the location scatter table indicative of updated geographical location distribution of all backups of all assets. A Location Service Level Objective (SLO) associated with a first asset is determined, the Location SLO associated with the first asset specifying one or more allowed locations where backups of the first asset are permitted to be located. All locations where at least one backup of the first asset is located are determined. A Location SLO check for the first asset is performed, wherein the Location SLO check passes when all the locations where at least one backup of the first asset is located fall within the allowed locations specified by the Location SLO.

Abstract: Apparatus for data processing and a method of data processing are provided. Address translation storage stores address translations between first set addresses and second set addresses, and responds to a request comprising a first set address to return a response comprising a second set address if the required address translation is currently stored therein. If it is not the request is forwarded towards memory in a memory hierarchy. A pending request storage stores entries for received requests and in response to reception of the request, if a stored entry for a previous request indicates that the previous request has been forwarded towards the memory and an expected response to the previous request will provide the address translation, intercepts the request to delay its reception by the address translation storage. Bandwidth pressure on the address translation storage is thus relieved.

Abstract: Disclosed is a method for processing a page fault. The method includes performing demand paging depending on an application operation in a system including a processor and an operating system, and loading, at the processor, data on a memory in response to the demand paging.

Abstract: An address search circuit of a semiconductor memory apparatus may include a first search interface configured to receive a search command, generate a first signal when a reference count of the target logical address is less than a threshold value, and generate a second signal when the reference count of the target logical address is equal to or more than the threshold value, a second search interface configured to receive map data whose respective reference counts are less than the threshold value in response to the first signal, a search memory configured to store map data whose respective reference counts are equal to or more than the threshold value, a first search buffer configured to store the map data received through the second search interface, and receive map data in response to the second signal; and a search engine configured to select map data by searching the map data.

Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.

Abstract: A logic circuitry package for a replaceable print apparatus component includes an interface to communicate with a print apparatus logic circuit, and a logic circuit having a communication address to communicate with the print apparatus logic circuit. The logic circuit is configured to detect, via the interface, communications that include an other communication address. The logic circuit is configured to respond, via the interface, to a command series directed to the logic circuit that include the communication address of the logic circuit, based on the detected communications.

Abstract: A computer-implemented method according to one embodiment includes initializing a new gateway node at a first site in response to a failure of an old gateway node at the first site; creating, at the new gateway node, a list of dirty directories at the first site; synchronizing, with a second site by a background thread at the first site, all directories within the list of dirty directories; and synchronizing, with the second site by a foreground thread at the first site, new operations performed within the first site after the initialization of the new gateway node.

Abstract: A method for detecting a Direct Memory Access (DMA) address capability at high address values when testing PCIe devices is disclosed. The method includes enabling an input/output (I/O) memory management unit (IOMMU); remapping physical addresses to virtual addresses at a high end of an address range; adding a peripheral component interconnect express (PCIe) device; and mapping physical memory addresses to high value memory addresses.

Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a first temperature level of a first block family associated with a memory device; identify a second temperature level of a second block family associated with the memory device; determine if a condition is satisfied based on the first temperature level and the second temperature level; and in response to the condition being satisfied, combine the first block family and the second block family to generate a combined block family.

Abstract: The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the IOMMU. The controller then performs the virtual address to physical address translations using the one or more selected memory elements.

Abstract: Systems, methods and apparatuses to throttle network communications for memory as a service are described. For example, a computing device can borrow an amount of random access memory of the lender device over a communication connection between the lender device and the computing device. The computing device can allocate virtual memory to applications running in the computing device, and configure at least a portion of the virtual memory to be hosted on the amount of memory loaned by the lender device to the computing device. The computing device can throttle data communications used by memory regions in accessing the amount of memory over the communication connection according to the criticality levels of the contents stored in the memory regions.

Abstract: A processing device in a memory sub-system maintains a mapping data structure to track data movements from a plurality of data management units associated with a media management operation on a memory device. The processing device further uses a first indicator and a second indicator of a plurality of indicators to indicate which data of data management units of a source group of data management units have been copied to a destination group of data management units during the media management operation. Data located in data management units preceding the first indicator have been copied to data management units of the destination group of data management units. Data located in data management units associated with the first indicator and the second indicator or between the first indicator and the second indicator are either copied to data management units of the destination group of data management units or remain located in data management units of the source group of data management units.

Abstract: Systems and methods are disclosed for employing a media read cache in a storage device. In certain embodiments, an, an apparatus may comprise a data storage drive including a volatile read cache, and a disc memory including a primary data storage region of the storage device configured for long-term storage of data via persistent logical block address to physical block address mapping, and a media read cache region configured to store a copy of data from the volatile read cache. The data storage drive may be configured to perform a read operation including: retrieve read data from the volatile read cache based on determining that the read data is available in the volatile read cache, and retrieve the read data from the media read cache based on determining that the read data is not available in the volatile read cache and is available in the media read cache.

Abstract: A method, computer program product, and computer system for identifying, by a computing device, information associated with a relationship between a physical layer block and a virtual logic block for RAID storage. The information associated with the relationship between the physical layer block and the virtual logic block may be written within the RAID storage.

Abstract: An apparatus is provided, where the apparatus includes a plurality of processing cores to execute a plurality of processes, a register to store an indicator that is to indicate a preference for either performance or energy efficiency, a first circuitry to determine an effective utilization of a first processing core, based on the indicator, and a second circuitry to select at least one of an operating voltage or an operating frequency of the first processing core, based at least in part on the effective utilization of the first processing core.

Abstract: A distributed storage system comprises a first module and a second module. The first module processes read requests for an address range, to send to the second module. The first module receives an address associated with a read request for a data page stored on the second module. A method searches a table on the first module for a content-based signature of the data page based on the address and provides the data page from a first module read cache if the content-based signature is in the read cache, where content-based signatures in the table are associated with the address range.

Abstract: A controller and a memory system including the same are disclosed. The controller receives a write command for storing write data, which is stored in at least one among a plurality of memory regions included in a host memory, in a nonvolatile memory device, generates a host memory map table by mapping virtual addresses to host memory physical addresses corresponding to the at least one memory region, and transmits the write data stored in the at least one memory region to the nonvolatile memory device by converting the virtual addresses into the host memory physical addresses based on the host memory map table.

Abstract: A method and apparatus for performing mapping information management regarding a RAID are provided. The method includes: writing data into a data region of the RAID in a redirect-on-write (ROW) manner, and recording mapping information between logical addresses of the data and protected-access-unit addresses (p-addresses) of protected access units in the data region into a logical-address-to-p-address (L2p) table within a table region of the RAID; when partial data of the data is updated, maintaining an updating list including a set of L2p table entries for the partial data in a RAM, and maintaining a recovery log corresponding to the updating list in a log region of the RAID, for power failure recovery; and according to the updating list, detecting whether a number of same-location L2p table entries in the set of L2p table entries reaches a predetermined threshold, to selectively update the L2p table with the same-location L2p table entries.

Abstract: A non-transitory computer-readable storage medium, a method, and an apparatus for reading partial data of a page on multiple data planes are provided. A processor core when loading and executing program code is arranged operably to: select at least two flash-memory access commands, which individually reads data whose length (e.g., 4KB or 8KB) is shorter than a length (e.g., 16KB) of one page across data planes for a logical unit number (LUN) according to the content of scheduling table; integrate the selected flash-memory access commands into one MPR-Lite command; drive a flash interface to perform a multi-page read lite (MPR-Lite) operation by executing the MPR-Lite command rather than the flash-memory access commands to read data from the LUN; and reply with read data to a host. Therefore, the time delay between the execution of selected flash-memory access commands would be reduced.

Abstract: A system includes a memory and at least one processor to monitor for a condition associated with a first cloud computing resource performing a cloud computing operation, determine that the condition associated with the first cloud computing resource has occurred, analyze the condition associated with the first cloud computing resource and compare the first cloud computing resource with a second cloud computing resource that is capable of performing at least a subset of the cloud computing operation, automatically modify the cloud computing operation that uses the first cloud computing resource to use the second cloud computing resource, and send at least one notification to a computing device about the condition associated with the first cloud computing resource and information associated with a modification of the cloud computing operation from the first cloud computing resource to the second cloud computing resource.

Abstract: Embodiments are configured to receive metadata of a process intercepted on an end host when attempting to access a network. The metadata includes a hash of an application associated with the process and an endpoint reputation score of the application. Embodiments are configured to request a threat intelligence reputation score based on the hash of the application, to determine an action to be taken by the end host based, at least in part, on one or more policies and at least one of the threat intelligence reputation score and the endpoint reputation score, and to send a response indicating the action to be taken by the end host. Further embodiments request another threat intelligence reputation score based on another hash of a dynamic link library module loaded by the process on the end host, and the action is determined based, at least in part, on the other threat intelligence score.

Abstract: A method for processing requests includes receiving a request comprising a virtual address, wherein the request is associated with an application executing on an operating system, identifying, based on data specified in the request, a logical volume associated with the data, making a first determination, based on the logical volume, that the logical volume is managed by a remote node, generating a data layout request to receive a data layout of the data from the remote node, receiving the data layout, wherein the data layout specifies a first physical address on the remote node that stores the data, initiating a copy request to copy the data from the first physical address to a second physical address on a local node, generating, based on the copy request, a virtual-to-physical address mapping between the virtual address and the second physical address; and initiating processing the request using the virtual-to-physical address mapping.

Abstract: A method, computer program product, and computer system for receiving, by a master controller, a request to create a read-only snapshot for an asynchronous source volume, wherein the master controller may be assigned ownership of the read-only snapshot. A peer controller may be assigned as a secondary owner of the read-only snapshot. Ownership of the peer controller as the secondary owner of the read-only snapshot may be revoked based upon a change in metadata of the read-only snapshot. The read-only snapshot may be replicated, asynchronously, from a replication source to a replication destination.

Abstract: An application running in a container is able to access files stored on disk via normal file system calls, but in a manner that remains isolated from applications and processes in other containers. In one aspect, a namespace virtualization component is coupled with a copy-on-write component. When an isolated application is accessing a file stored on disk in a read-only manner, the namespace virtualization component and copy-on-write component grant access to the file. But, if the application requests to modify the file, the copy-on-write component intercepts the I/O and effectively creates a copy of the file in a different storage location on disk. The namespace virtualization component is then responsible for hiding the true location of the copy of the file, via namespace mapping.

Abstract: Disclosed is a method for performing write-back operations to maintain coherence of remote memories in a memory pool. When a local application makes a request for a page of memory that is in the memory pool but not local, a device obtains the page through its RDMA facility and thereafter keeps track of the page for any changes made by the application to the page by storing the page locally and monitoring cache coherency events of cache lines that make up the page. If a requested page become dirty, then periodically the dirty cache lines of the dirty page are written back to the remote memory from which the pages were obtained. In addition, all dirty cache lines are written back when the local memory storing the page becomes full or the application closes a region containing the page.

Abstract: Techniques involve: in response to receiving an access request for a logical address, determining a first virtual storage unit and a first offset within the first virtual storage unit corresponding to the logical address; determining a first set of virtual storage units to which the first virtual storage unit belongs and a position of the first virtual storage unit, determining, from the plurality of physical storage units corresponding to the first set of virtual storage units and based on the position and the first offset, a physical storage unit and a second offset within the physical storage unit corresponding to the logical address; and performing, based on an identifier of the physical storage unit and the second offset, a data access operation requested by the access request. Accordingly, I/O loads on a plurality of disks can be balanced, thereby improving overall performance of a storage system.

Abstract: A technique for performing store-to-load forwarding is provided. The technique includes determining a virtual address for data to be loaded for the load instruction, identifying a matching store instruction from one or more store instruction memories by comparing a virtual-address-based comparison value for the load instruction to one or more virtual-address-based comparison values of one or more store instructions, determining a physical address for the load instruction, and validating the load instruction based on a comparison between the physical address of the load instruction and a physical address of the matching store instruction.

Abstract: A data index sequence indexing a dataset is received. A location of a data sample identified by a data index in the data index sequence is determined. A scheme is generated for specifying a data movement based on the location. Responsive to determining that the location is a cache of a process, the data sample in the cache can be reused without having to load the data sample from a storage device.

Abstract: According to one embodiment, an information processing device includes a nonvolatile memory, assignment unit, and transmission unit. The assignment unit assigns logical address spaces to spaces. Each of the spaces is assigned to at least one write management area included in a nonvolatile memory. The write management area is a unit of an area which manages the number of write. The transmission unit transmits a command for the nonvolatile memory and identification data of a space assigned to a logical address space corresponding to the command.

Abstract: Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.

Abstract: Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can be used to provide a unique instruction model based on triggers defined in metadata of the memory objects. This model represents a dynamic dataflow method of execution in which processes are performed based on actual dependencies of the memory objects. This provides a high degree of memory and execution parallelism which in turn provides tolerance of variations in access delays between memory objects. In this model, sequences of instructions are executed and managed based on data access. These sequences can be of arbitrary length but short sequences are more efficient and provide greater parallelism.

Abstract: An adaptive memory expansion scheme is proposed, where one or more memory expansion capable Hosts or Accelerators can have their memory mapped to one or more memory expansion devices. The embodiments below describe discovery, configuration, and mapping schemes that allow independent SCM implementations and CPU-Host implementations to match their memory expansion capabilities. As a result, a memory expansion host (e.g., a memory controller in a CPU or an Accelerator) can declare multiple logical memory expansion pools, each with a unique capacity. These logical memory pools can be matched to physical memory in the SCM cards using windows in a global address map. These windows represent shared memory for the Home Agents (HAs) (e.g., the Host) and the Slave Agent (SAs) (e.g., the memory expansion device).

Abstract: A first processor core with an operating system installed and a second processor core controlled by the first processor core and capable of executing parallel operation processing are included. The second processor core, when detecting a page fault, stops new instruction issue and stops as an issued and uncompleted instruction can be restarted, and also sends notification of page fault detection to the first processor core. The first processor core includes a permissibility judgment part that judges whether or not the page fault is permissible in response to reception of the notification, a page table updating part that updates a page table included by the second processor core in accordance with a result of the judgment by the permissibility judgment part, and a directing part that sends a direction corresponding to a result of the judgment by the permissibility judgment part to the second processor core.

Abstract: Implementations disclosed describe a system and a method to execute a virtual machine on a processing device, receive a request to access a memory page identified by a guest virtual memory address (GVA) in an address space of the virtual machine, translate the GVA to a guest physical memory address (GPA) using a guest page table (GPT) comprising a GPT entry mapping the GVA to the GPA, translate the GPA to a host physical address (HPA) of the memory page, store, in a translation lookaside buffer (TLB), a TLB entry mapping the GVA to the HPA, modify the GPT entry to designate the memory page as accessed, detect an attempt by an application to modify the GPT entry; generate, in response to the attempt to modify the GPT entry, a page fault; and flush, in response to the page fault, the TLB entry.

Abstract: A computer-implemented method according to one embodiment includes identifying a data write to a specific position within a virtual address space, determining an entry within a metadata structure that corresponds to the specific position within the virtual address space, and adding state information associated with the data write to the entry within the metadata structure, the state information including a size of the data write within the virtual address space and an alignment of the data write within the virtual address space.

Abstract: A high efficiency garbage collection method, an associated data storage device and a controller thereof are provided. The high efficiency garbage collection method includes: starting and executing a garbage collection procedure; determining whether a Trim command from a host device is received; in response to the Trim command being received, determining whether target data of the Trim command is stored in a source block of the garbage collection procedure; in response to the target data being stored in the source block, determining whether the target data stored in the source block has been copied to a destination block of the garbage collection procedure; and in response to the target data stored in the source block having been copied to the destination block, changing at least one physical address of the target data of the Trim command to a Trim tag in a logical-to-physical address mapping table.

Abstract: Virtual block redirection clean-up is accomplished for a virtual block in a mapper tree for a logical volume that is redirected to a destination virtual block in the mapper tree. In response to redirection of the virtual block, a redirection notification is sent to each component in a set of dependent components. Each dependent component may store one or more pointers to pointers located within virtual blocks of the mapper tree. The redirected virtual block is cleaned up in response to determining that each dependent component has expressly indicated, in response to the redirection notification, that it does not store any pointer to any pointer that is located within the redirected virtual block.

Abstract: A processing device includes a processor configured to output a memory access instruction issued by a process executed on a virtual machine and a virtual address targeted by the memory access instruction. The processor is configured to perform first translation of translating the virtual address into a real address of a virtual memory. The processor is configured to perform second translation of translating the real address into a physical address of a physical memory. The processor is configured to determine, based on the memory access instruction and an access permission attribute of the real address, whether an access permission violation occurs. The processor is configured to perform, upon determining that an access permission violation occurs, retranslation of translating the virtual address into the real address. The processor is configured to record the virtual address and the real address obtained by the retranslation in a log area of a memory.