Virtual Addressing Patents (Class 711/203)
  • Patent number: 10310990
    Abstract: In one example in accordance with the present disclosure, a method may include retrieving, at a memory management unit (MMU), encrypted data from a memory via direct memory access and determining, at the MMU, a peripheral that is the intended recipient of the encrypted data. The method may also include accessing an application key used for transmission between an application and the peripheral, wherein the application key originates from the application and decrypting, at the MMU, the encrypted data using the application key and transmitting the decrypted data to the peripheral.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: June 4, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Adrian Shaw, Geoffrey Ndu, Fraser John Dickin
  • Patent number: 10303543
    Abstract: A system and method are provided to control error-protected access to a memory device having address integrity protection for data words of memory transactions. A communication port receives a command having a port address, which is adaptively converted to a memory address by an interface portion. The interface portion includes an adaptation stage carrying out a predefined adaptation response on an address propagated therethrough during a clock cycle of operation. An address protection portion configures the adaptation stage to maintain the predefined adaptation response over at least two clock cycles. Address error is detected based on comparison of output addresses respectively generated upon iterative propagation of the same input address through the adaptation stage over the clock cycles. A command control portion executes to adaptively split each command received from the interface portion, as well as the corresponding memory address according to an inline storage configuration of the memory device.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: May 28, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: John M. MacLaren
  • Patent number: 10303380
    Abstract: In one embodiment, a computer program product for managing a reserve command includes a computer readable storage medium having program code embodied therewith, the program code readable and/or executable by a processor to receive, by the processor, a request to access a data set on one or more volumes of at least one direct access storage device (DASD), the request including a reserve command, and each of the one or more volumes including a consecutive set of one or more tracks of the at least one DASD, and reserve one or more extents of the at least one DASD while reserving less than a volume of the at least one DASD and not allowing any other entity than an entity which requested the reserve to access the one or more extents of the at least one DASD that have been reserved.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Susan K. Candelaria, Clint A. Hardy, Gavin S. Johnson, Matthew J. Kalos, Michael J. Koester, John R. Paveza, Carrie J. Van Noorden
  • Patent number: 10303595
    Abstract: The present invention relates to a dynamic memory management method which includes generating an N-dimensional memory address space in which coordinates are in a range of N natural numbers, the sum of which is the number of bits; and mapping a predetermined linear memory address region to an address region in the N-dimensional memory address space.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: May 28, 2019
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Ik Soon Kim
  • Patent number: 10289435
    Abstract: The described implementations relate to virtual computing techniques. One implementation provides a technique that can include receiving a request to execute an application. The application can include first application instructions from a guest instruction set architecture. The technique can also include loading an emulator and a guest operating system into an execution context with the application. The emulator can translate the first application instructions into second application instructions from a host instruction set architecture. The technique can also include running the application by executing the second application instructions.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: May 14, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Barry C. Bond, Reuben R. Olinsky, Galen C. Hunt
  • Patent number: 10289561
    Abstract: A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 14, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Elona Erez, Avner Dor, Jun-Jin Kong
  • Patent number: 10289418
    Abstract: Techniques are provided for handling a trap encountered in a thread that is part of a thread array that is being executed in a plurality of execution units. In these techniques, a data structure with an identifier associated with the thread is updated to indicate that the trap occurred during the execution of the thread array. Also in these techniques, the execution units execute a trap handling routine that includes a context switch. The execution units perform this context switch for at least one of the execution units as part of the trap handling routine while allowing the remaining execution units to exit the trap handling routine before the context switch. One advantage of the disclosed techniques is that the trap handling routine operates efficiently in parallel processors.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: May 14, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Gerald F. Luiz, Philip Alexander Cuadra, Luke Durant, Shirish Gadre, Robert Ohannessian, Lacky V. Shah, Nicholas Wang, Arthur Danskin
  • Patent number: 10284519
    Abstract: When requesting network services, clients often supply authentication information such as digital signatures. A network provider may from time to time change its authentication scheme. Clients are notified of the change and are provided with an updated authentication specification. Upon receiving the updated authentication specification, a client updates its authentication logic accordingly, and subsequently prepares and provides authentication information in accordance with the new authentication scheme.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: May 7, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Eric J. Brandwine, Peter N. DeSantis
  • Patent number: 10282373
    Abstract: Embodiments are directed towards managing pushed vitality updates of recent user-generated content (UGC). A vitality service is arranged to receive pushed vitality updates that each include a resource identifier and at least one other type of vitality information referring to recent UGC on a network device. The vitality service is configured to manage the pushed vitality updates according to recency and to receive query requests for vitality information. In response to a query request, the vitality service searches for vitality updates and provides to another network device recent vitality information based on the query request. The recent vitality information includes at least one or more resource identifiers and one or more other types of vitality information so that the other network device can access the full UGC for display.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: May 7, 2019
    Assignee: EXCALIBUR IP, LLC
    Inventors: Michael Tadlock, Tom Quiggle
  • Patent number: 10275187
    Abstract: A memory device is provided. A processor accesses non-volatile memories via channels and generates a status table according to at least one command of a command queue. The status table records a plurality of tasks. Each task corresponds to one read status and one channel number. The processor selects a plurality of specific tasks from the tasks to serve as a first task set and simultaneously performs all the selected specific tasks with different channel numbers. When the read status of a first specific task matches a first predetermined status, the processor retrieves a logical-to-physical address mapping table relating to the logical address of the first specific task. When the read status of the first specific task matches a second predetermined status, the processor retrieves data relating to the logical address of the first specific task.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: April 30, 2019
    Assignee: Silicon Motion, Inc.
    Inventor: Yu-Chih Lin
  • Patent number: 10275306
    Abstract: A system and method are provided for controlling access to a memory device having adaptively split addressing of error-protected data words according to an inline memory storage configuration. An address translation section executes to convert a data address associated with a received command to inline data and inline error checking addresses corresponding thereto. Each data word's data and error checking bits are stored according to respective inline data inline error checking addresses. A segment of error checking bits is thereby offset in address from at least one segment of the same data word's data bits in a common chip of the memory device. A command translation section executes to convert between a received command to data access and error checking access commands for actuating respective access operations on the memory device. An error checking storage section intermediately stores error checking bits responsive to execution of the error checking access command.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: April 30, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: John MacLaren, Carl Olson, Jerome J. Johnson, Thomas J. Shepherd
  • Patent number: 10261840
    Abstract: Aspects include allocating virtual resources to physical resources in a computer environment and aggregating the virtual resources, as a virtual resource pool, at a per virtual machine level in the computer environment. Other aspects include evaluating the virtual resources in the virtual resource pool against resource pool domain constraints. Other aspects include determining a resource allocation adjustment as a function of the evaluating. The resource allocation adjustment is configured to achieve a maximum specified virtual machine density. Other aspects include adjusting the virtual resources based on the resource allocation adjustment.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Simon J. Kofkin-Hansen, Richard T. Lemelin, Setareh Mehrabanzad, Shawn P. Raess
  • Patent number: 10254963
    Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a data stream including one or more data blocks; determine a size of the one or more data blocks; determine a number of mappings needed for a physical block based on the size of a data block and a size of the physical block, the number of mappings being variable for different physical blocks depending on the size of the one or more data blocks storing in the physical block; retrieve a dynamically sized reverse map, the dynamically sized reverse map being a dynamic tree structure; determine a starting location in the dynamically sized reverse map for mappings of the one or more data blocks; and create an entry for the physical block in the dynamically sized reverse map.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: April 9, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sandeep Sharma, Saurabh Manchanda
  • Patent number: 10248448
    Abstract: Methods, computer-readable storage medium, and systems described herein facilitate provisioning a virtual desktop infrastructure having virtual shared storage. A provisioning manager receives a desktop pool type and provisions virtual shared storage among a cluster of hosts. The provisioning manager configures the virtual shared storage based on the desktop pool type and provisions at least one virtual machine to each host in the cluster of hosts. The provisioning manager optimizes the virtual shared storage by receiving a storage performance benchmark from each host and performing an optimization on the cluster of hosts if the storage performance benchmark results do not meet a threshold within a pre-defined tolerance.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: April 2, 2019
    Assignee: VMware, Inc.
    Inventor: Daniel James Beveridge
  • Patent number: 10242124
    Abstract: In a memory, multiple pieces of entry data sorted in ascending or descending order are stored associated with addresses. With whole addresses for storing the multiple pieces of entry data as an initial search area, the search circuit repeatedly performs a search operation for comparing entry data stored in a central address of the search area with the search data, outputting the address as a search result in the case of a match, and narrowing the search area for the next search based on a magnitude comparison result in the case of a mismatch.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: March 26, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tsutomu Makino
  • Patent number: 10241841
    Abstract: Aspects include allocating virtual resources to physical resources in a computer environment and aggregating the virtual resources, as a virtual resource pool, at a per virtual machine level in the computer environment. Other aspects include evaluating the virtual resources in the virtual resource pool against resource pool domain constraints. Other aspects include determining a resource allocation adjustment as a function of the evaluating. The resource allocation adjustment is configured to achieve a maximum specified virtual machine density. Other aspects include adjusting the virtual resources based on the resource allocation adjustment.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Simon J. Kofkin-Hansen, Richard T. Lemelin, Setareh Mehrabanzad, Shawn P. Raess
  • Patent number: 10241676
    Abstract: A hardware-based processing node of an object memory fabric can comprise a memory module storing and managing one or more memory objects within an object-based memory space. Each memory object can be created natively within the memory module, accessed using a single memory reference instruction without Input/Output (I/O) instructions, and managed by the memory module at a single memory layer. The memory module can provide an interface layer below an application layer of a software stack. The interface layer can comprise one or more storage managers managing hardware of a processor and controlling portions of the object-based memory space visible to a virtual address space and physical address space of the processor. The storage managers can further provide an interface between the object-based memory space and an operating system executed by the processor and an alternate object memory based storage transparent to software using the interface layer.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: March 26, 2019
    Assignee: Ultrata, LLC
    Inventors: Steven J. Frank, Larry Reback
  • Patent number: 10237347
    Abstract: A computerized method for enabling a client device seamless access to a plurality of remote storage devices connected to the client device via a communication network. The method comprises receiving a plurality of physical addresses by a controller communicatively coupled to the client device and to a plurality of storage servers, each of the plurality of storage servers communicatively coupled to at least one storage device, the plurality of physical addresses enabling access by the controller to the remote storage devices. A single virtual storage device having a logical address space is generated on the device, wherein each of the plurality of physical addresses is mapped by the controller to a unique logical address of the virtual storage device.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: March 19, 2019
    Assignee: Excelero Storage Ltd.
    Inventors: Yaniv Romem, Omri Mann, Ofer Oshri
  • Patent number: 10223292
    Abstract: Described are examples for securing stream data received from a stream source. A secure mode can be enabled, based on a request from an application, for storing the stream data captured from the stream source in a secured buffer. The secured buffer can be allocated in a secure memory based at least in part on enabling the secure mode. A secured buffer identifier of the secured buffer can be provided to a driver of a device providing the stream source for storing the stream data captured from the stream source in the secured buffer. The secured buffer identifier of the secured buffer can also be provided to the application for accessing the stream data stored in the secured buffer.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: March 5, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mei L. Wilson, Fabin Shen, Sathyanarayanan Karivaradaswamy, Gerrit L. Swaneveld
  • Patent number: 10216626
    Abstract: Embodiments of the invention provide a method and system for dynamic memory management implemented in hardware. In an embodiment, the method comprises storing objects in a plurality of heaps, and operating a hardware garbage collector to free heap space. The hardware garbage collector traverses the heaps and marks selected objects, uses the marks to identify a plurality of the objects, and frees the identified objects. In an embodiment, the method comprises storing objects in a heap, each of at least some of the objects including a multitude of pointers; and operating a hardware garbage collector to free heap space. The hardware garbage collector traverses the heap, using the pointers of some of the objects to identify others of the objects; processes the objects to mark selected objects; and uses the marks to identify a group of the objects, and frees the identified objects.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: David F. Bacon, Perry S. Cheng, Sunil K. Shukla
  • Patent number: 10209997
    Abstract: A system for parallel execution of program portions on different processors permits speculative execution of the program portions before a determination is made as to whether there is a data dependency between the portion and older but unexecuted portions. Before commitment of the program portions in a sequential execution order, data dependencies are resolved through a token system that tracks read access and write access to data elements accessed by the program portions.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: February 19, 2019
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Gagan Gupta, Gurindar S. Sohi
  • Patent number: 10205743
    Abstract: Embodiments are configured to receive metadata of a process intercepted on an end host when attempting to access a network. The metadata includes a hash of an application associated with the process and an endpoint reputation score of the application. Embodiments are configured to request a threat intelligence reputation score based on the hash of the application, to determine an action to be taken by the end host based, at least in part, on one or more policies and at least one of the threat intelligence reputation score and the endpoint reputation score, and to send a response indicating the action to be taken by the end host. Further embodiments request another threat intelligence reputation score based on another hash of a dynamic link library module loaded by the process on the end host, and the action is determined based, at least in part, on the other threat intelligence score.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: February 12, 2019
    Assignee: McAfee, LLC
    Inventors: Chandan Cp, Srinivasan Narasimhan
  • Patent number: 10198202
    Abstract: A device access system includes a memory having a supervisor memory, a processor, an input output memory management unit (IOMMU), and a supervisor. The supervisor includes a supervisor driver, which executes on the processor to allocate the supervisor memory and reserve a range of application virtual addresses. The supervisor driver programs the IOMMU to map the supervisor memory to the reserved range. A device is granted access to the reserved range, which is protected in host page table entries such that an application cannot modify data within the range. The supervisor driver configures the device to use the supervisor memory and receive a request including a virtual address and length from the application to use the device. The supervisor driver validates the request by verifying that the virtual address and length do not overlap the range reserved by the supervisor, and responsive to validating the request, submits the request to the device.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: February 5, 2019
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 10185679
    Abstract: A system and method of device assignment includes receiving an assignment request to assign a device to a plurality of guest virtual machines. The plurality of guest virtual machines includes a first guest virtual machine with a first guest memory having a first physical address and a second guest virtual machine with a second guest memory having a second physical address. The method includes selecting a first bus address offset and a second bus address offset different from the first bus address offset. The method includes sending, to the first guest virtual machine, the first bus address offset, and sending, to the second guest virtual machine, the second bus address offset. The method includes updating a mapping to the first physical address to include the first bus address offset, and updating a mapping to the second physical address to include the second bus address offset.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: January 22, 2019
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Marcel Apfelbaum
  • Patent number: 10180915
    Abstract: A method and an apparatus for accessing physical resources, is used to restrict access to physical resources of other light system kernel Light OSs by a first Light OS in a multi-kernel operating system and ensure security of accessing physical resources among the Light OSs. A method, executed by secure firmware, includes: receiving a physical address corresponding to a physical resource to be accessed by the first Light OS; determining whether the physical address corresponding to the physical resource is out of bounds; and if the physical address corresponding to the physical resource is within bounds, sending an access continuity signal to the first Light OS; or if the physical address corresponding to the physical resource is out of bounds, sending an access error signal to the first Light OS.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: January 15, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Chen Zheng, Long Fu, Jianfeng Zhan, Lixin Zhang
  • Patent number: 10178169
    Abstract: A storage system is provided. The storage system includes a plurality of storage nodes, each of the plurality of storage nodes having a plurality of storage units with storage memory. The system includes a first network coupling the plurality of storage nodes and a second network coupled to at least a subset of the plurality of storage units of each of the plurality of storage nodes such that one of the plurality of storage units of a first one of the plurality of storage nodes can initiate or relay a command to one of the plurality of storage units of a second one of the plurality of storage nodes via the second network without the command passing through the first network.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: January 8, 2019
    Assignee: Pure Storage, Inc.
    Inventors: Par Botes, John Hayes, Zhangxi Tan
  • Patent number: 10176110
    Abstract: A marking capability is used to provide an indication of whether a block of memory is backing an address translation structure of a control program being managed by a virtual machine manager. By providing the marking, the virtual machine manager may check the indication prior to making paging decisions. With this information, a hint may be provided to the hardware to be used in decisions relating to purging associated address translation structures, such as translation look-aside buffer (TLB) entries.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind
  • Patent number: 10163510
    Abstract: Emerging byte-addressable persistent memory technologies, generically referred to as Storage Class Memory, offer performance advantages and access similar to Dynamic Random Access Memory while having the persistence of disk. Unifying storage and memory into a memory tier that can be accessed directly requires additional burden to ensure that groups of memory operations to persistent or nonvolatile memory locations are performed sequentially, atomically, and not caught in the cache hierarchy. The present invention provides a lightweight solution for the atomicity and durability of write operations to nonvolatile memory, while simultaneously supporting fast paths through the cache hierarchy to memory. The invention includes a hardware-supported solution with modifications to the memory hierarchy comprising a victim cache and additional memory controller logic.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: December 25, 2018
    Inventors: Ellis Robinson Giles, Peter Joseph Varman
  • Patent number: 10162764
    Abstract: A marking capability is used to provide an indication of whether a block of memory is backing an address translation structure of a control program being managed by a virtual machine manager. By providing the marking, the virtual machine manager may check the indication prior to making paging decisions. With this information, a hint may be provided to the hardware to be used in decisions relating to purging associated address translation structures, such as translation look-aside buffer (TLB) entries.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: December 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind
  • Patent number: 10157148
    Abstract: A semiconductor device may include a first address cache configured to store a physical address of a semiconductor memory device and a write count associated with the physical address, an address monitor configured to update the physical address and the write count in the first address cache based on a received write request, and an arbiter configured to store a write address and write data associated with the write request in a write cache in response to a command from the address monitor, wherein the command generated by the address monitor is based on whether an update is made to the physical address and the write count in first address cache.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: December 18, 2018
    Assignee: SK hynix Inc.
    Inventors: Young-Suk Moon, Hong-Sik Kim
  • Patent number: 10152426
    Abstract: A mapping table loading method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first command; loading a first sub-logical address-physical address mapping table corresponding to the first command if an operating mode of a non-volatile rewritable memory module is a first operating mode; and loading a first logical address-physical address mapping table corresponding to the first command if the operating mode of the non-volatile rewritable memory module is a second operating mode, wherein the first logical address-physical address mapping table includes the first sub-logical address-physical address mapping table.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: December 11, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10146561
    Abstract: A processor-based device (e.g., a wireless device) may include a processor and a semiconductor nonvolatile memory to directly execute an application (e.g., an execute-in-place application) using an associated database. Within a flash memory, in one embodiment, an executable program may be separately stored in a non-fragmented manner from a resident database that includes program management information for use in an execution that does not involve a random access memory, saving time and resources.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventor: John C. Rudelic
  • Patent number: 10140060
    Abstract: A memory system having multiple memory layers includes a first memory layer comprising a volatile memory, a second memory layer comprising a first sub-memory and a second sub-memory. In response to a reference failure that occurred in the first memory layer, to which a read reference failed data and a write reference failed data are respectively loaded from lower level memory layer.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: November 27, 2018
    Assignee: SEJONG UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATION
    Inventor: Gi Ho Park
  • Patent number: 10133661
    Abstract: Disclosed herein are system, method, and computer program product embodiments for adaptively self-tuning a bucket memory manager. An embodiment operates by receiving requests for memory blocks of varying memory sizes from a client. Determining a workload for the client based on the requests. Analyzing buckets in the bucket memory manager based on the workload. Adjusting parameters associated with the bucket memory manager based on the analyzing to accommodate the requests.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: November 20, 2018
    Assignee: SAP SE
    Inventor: Tony Imbierski
  • Patent number: 10127018
    Abstract: Various embodiments include methods for dynamically modifying shared libraries on a client computing device. Various embodiment methods may include receiving a first set of code segments and a first set of code sites associated with a first application. Each code in the first set of code sites may include an address within a compiled shared library stored on the client computing device. The compiled shared library may include one or more dummy instructions inserted at each code site in the first set of code sites, and each code segment in the first set of code segments may be associated with a code site in the first set of code sites. The client computing device may insert each code segment in the first set of code segments at its associated code site in the compiled shared library.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: November 13, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Sudha Anil Kumar Gathala, Mihai Christodorescu, Mastooreh Salajegheh
  • Patent number: 10114760
    Abstract: A system and method are provided for implementing multi-stage translation of virtual addresses. The method includes the steps of receiving, at a first memory management unit, a memory request including a virtual address in a first address space, translating the virtual address to generate a second virtual address in a second address space, and transmitting a modified memory request including the second virtual address to a second memory management unit. The second memory management unit is configured to translate the second virtual address to generate a physical address in a third address space. The physical address is associated with a location in a memory.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: October 30, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Steven E. Molnar, Jay Kishora Gupta, James Leroy Deming, Samuel Hammond Duncan, Jeffrey Smith
  • Patent number: 10101931
    Abstract: Read errors following programming in a multi-level non-volatile memory are mitigated by a controller of the non-volatile memory. The controller temporarily buffers, in a cache, pages of data programmed into the non-volatile memory. In response to receiving a read request for a target page of data programmed into the non-volatile memory, where the read request is received during a delay time affecting the target page, the controller services the read request by accessing data of the target page in the cache in response to the read request hitting in the cache. The controller instead services the read request from the non-volatile memory in response to the read request missing in the cache. When servicing the read request from the non-volatile memory, the controller preferably reads the target page from the non-volatile memory utilizing a set of read voltage thresholds determined based on the read-after-write delay.
    Type: Grant
    Filed: June 4, 2017
    Date of Patent: October 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Thomas Mittelholzer, Nikolaos Papandreou, Thomas Parnell, Roman Pletka, Charalampos Pozidis, Sasa Tomic
  • Patent number: 10067783
    Abstract: One embodiment of the present invention is a method of interposing operations in a computational system that includes a virtualization system executable on an underlying hardware processor that natively supports one or more instructions that transition between host and guest execution modes.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: September 4, 2018
    Assignee: VMware, Inc.
    Inventor: Keith Adams
  • Patent number: 10055244
    Abstract: A non-transitory computer-readable storage medium storing therein a boot control program that causes a computer to execute a process includes storing booting process result data in which a first memory amount based on a sum of a memory amount allocated to a virtual machine that has been booted up and a memory amount allocated to a virtual machine to be booted up, and a boot processing time for booting the virtual machine to be booted up are associated with each other and determining a timing at which a booting process of a new virtual machine starts based on the boot processing time associated with the first memory amount having a correlation with a second memory amount based on a sum of a memory amount.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: August 21, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Hiroki Sumida, Yasuo Yoshimoto
  • Patent number: 10021218
    Abstract: I/O bandwidth reduction using storage-level common page information is implemented by a storage server, in response to receiving a request from a client for a page stored at a first virtual address, determining that the first virtual address maps to a page that is a duplicate of a page stored at a second virtual address or that the first and second virtual addresses map to a deduplicated page within a storage system, and transmitting metadata to the client mapping the first virtual address to a second virtual address that also maps to the deduplicated page. For one embodiment, the metadata is transmitted in anticipation of a request for the redundant/deduplicated page via the second virtual address. For an alternate embodiment, the metadata is sent in response to a determination that a page that maps to the second virtual address was previously sent to the client.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: July 10, 2018
    Assignee: NetApp Inc.
    Inventors: Deepak Raghu Kenchammana-Hosekote, Michael R. Eisler, Arthur F. Lent, Rahul Iyer, Shravan Gaonkar
  • Patent number: 10019332
    Abstract: A non-volatile storage system is proposed with an efficient process for recovering from programming failures. In response to determining that a program fault occurred, and prior to completing the programming, the system programs data associated with the program fault to a back-up location. After programming the data associated with the program fault to the back-up location, the system continues programming including programming data that has not yet been subject of a programming process to the back-up location. After completing the programming process, the system moves already programmed data near the location of the program fault to the back-up location.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: July 10, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Rohit Sehgal, Nian Niles Yang
  • Patent number: 10007242
    Abstract: A computer detects a request by a process for access to a shadow control page, wherein the shadow control page allows the process access to one or more devices. The computer assigns the shadow control page and a key to the process associated with the request. The computer detects a request by the process via the assigned shadow control page for creation of a subset of devices from the one or more devices. The computer inputs information detailing an association between the subset of devices and the assigned key into a subset definition table, wherein the subset definition table includes one or more keys and one or more corresponding subsets.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Fox, Hans M. Jacobson, Ravi Nair, Bryan S. Rosenburg
  • Patent number: 10001924
    Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a data stream including one or more data blocks; determine a size of the one or more data blocks; determine a number of mappings needed for a physical block based on the size of a data block and a size of the physical block, the number of mappings being variable for different physical blocks depending on the size of the one or more data blocks storing in the physical block; retrieve a dynamically sized reverse map, the dynamically sized reverse map being a dynamic tree structure; determine a starting location in the dynamically sized reverse map for mappings of the one or more data blocks; and create an entry for the physical block in the dynamically sized reverse map.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: June 19, 2018
    Assignee: HGST NETHERLANDS B.V.
    Inventors: Sandeep Sharma, Saurabh Manchanda
  • Patent number: 9986271
    Abstract: The invention provides a method and apparatus that addresses and resolves the issues currently affecting the ability to offer Enhanced TV, in particular, those issues concerning timing and synchronization, interaction with other modules in the STB, and distribution.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: May 29, 2018
    Assignee: Comcast Cable Communications Management, LLC
    Inventors: Brian Bulkowski, Carolyn Wales, Sam Hsu, James Helman, Joseph Decker, Brock Wagenaar, Mark Vickers
  • Patent number: 9965218
    Abstract: Described are techniques for processing service level objectives. A first service level objective specified for a storage group of devices may include a first value denoting a first target level of performance for I/O operations. A second service level objective specified for a first portion of the storage group may include a second value denoting a second target level of performance for I/O operations directed to the first portion. The second value may denote a higher level of performance than the first value. It may be determined whether there is a violation of any of the first service level objective and the second level objective. Responsive to determining there is the violation of any of the first service level objective and the second level objective, one or more data movements in accordance with the violation may be performed.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: May 8, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Owen Martin, Malak Alshawabkeh, Hui Wang, Xiaomei Liu, Sean C. Dolan, Adnan Sahin
  • Patent number: 9959131
    Abstract: A data identification system and method for operating the data identification system are provided. The method comprises identifying processing elements contained within the storage environment, identifying virtual processing elements contained within the processing elements, identifying virtual storage elements contained within the virtual processing elements, identifying contents of the virtual storage elements, generating the file system view of the storage environment, wherein the file system view comprises the processing elements, the virtual processing elements, the virtual storage elements, and the contents of the virtual storage elements arranged in a hierarchical order. The file system view of the storage environment is then provided.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: May 1, 2018
    Assignee: Quantum Corporation
    Inventors: Gregory L. Wade, J. Mitchell Haile
  • Patent number: 9928180
    Abstract: The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a “T” bit. The T bit of the NPT/EPT entries mapping the guest page table are set when a page walk is performed on the NPT/EPT. When modifications are made to pages mapped by NPT/EPT entries with their T bit set, changes to the TLB are made so that the TLB remains in synchronization with the guest page table. Accordingly, record/replay of virtual machines of virtualized computer systems may be performed reliably with no non-determinism introduced by stale TLBs that fall out of synchronization with the guest page table.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: March 27, 2018
    Assignee: VMware, Inc.
    Inventors: Vyacheslav Vladimirovich Malyugin, Boris Weissman, Ganesh Venkitachalam, Min Xu
  • Patent number: 9930051
    Abstract: In a cloud environment, each host computer can have its own security service processor with an independent network interface for communicating with a remote server over a network. The security service processor can provide remote management and security functionalities for various devices connected using different buses on a platform in each host computer. The security service processor can provide a centralized mechanism to verify and authenticate firmware updates for various devices using different buses. A hardware interface can allow the security service processor to provide remote debugging and diagnostic capabilities. The security service processor can also provide some of the typical functionalities of a baseboard management controller or can be used in addition to the baseboard management controller.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: March 27, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Nachiketh Rao Potlapally, Jason Alexander Harland, Derek Del Miller, Christopher James BeSerra
  • Patent number: 9918411
    Abstract: In one embodiment, a rack enclosure for housing rack-mounted equipment includes a deflection member adapted to a piece of the rack-mounted equipment and an actuator coupled to the deflection member to control a position of the deflection member between a fully closed position and a fully opened position. A variable amount of cooling airflow is to be provided to the equipment piece based on the deflection member position.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: March 13, 2018
    Assignee: Rackspace US, Inc.
    Inventors: Jordan Rinke, Joel Wineland
  • Patent number: 9916256
    Abstract: A method of accessing a persistent memory over a memory interface is disclosed. In one embodiment, the method includes allocating a virtual address range comprising virtual memory pages to be associated with physical pages of a memory buffer and marking each page table entry associated with the virtual address range as not having a corresponding one of the physical pages of the memory buffer. The method further includes generating a page fault when one or more of the virtual memory pages within the virtual address range is accessed and mapping page table entries of the virtual memory pages to the physical pages of the memory buffer. The method further includes transferring data between a physical page of the persistent memory and one of the physical pages of the memory buffer mapped to a corresponding one of the virtual memory pages.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: March 13, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: David Stanley Maxey, Nidish Ramachandra Kamath, Vikas Kumar Agrawal