Virtual Addressing Patents (Class 711/203)
  • Patent number: 11144408
    Abstract: A method, computer program product, and computer system for receiving, by a master controller, a request to create a read-only snapshot for an asynchronous source volume, wherein the master controller may be assigned ownership of the read-only snapshot. A peer controller may be assigned as a secondary owner of the read-only snapshot. Ownership of the peer controller as the secondary owner of the read-only snapshot may be revoked based upon a change in metadata of the read-only snapshot. The read-only snapshot may be replicated, asynchronously, from a replication source to a replication destination.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: October 12, 2021
    Assignee: EMC Holding Company, LLC
    Inventor: Govindaraja Nayaka B
  • Patent number: 11126464
    Abstract: Disclosed is a method for performing write-back operations to maintain coherence of remote memories in a memory pool. When a local application makes a request for a page of memory that is in the memory pool but not local, a device obtains the page through its RDMA facility and thereafter keeps track of the page for any changes made by the application to the page by storing the page locally and monitoring cache coherency events of cache lines that make up the page. If a requested page become dirty, then periodically the dirty cache lines of the dirty page are written back to the remote memory from which the pages were obtained. In addition, all dirty cache lines are written back when the local memory storing the page becomes full or the application closes a region containing the page.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: September 21, 2021
    Assignee: VMware, Inc.
    Inventors: Irina Calciu, Jayneel Gandhi, Aasheesh Kolli, Pratap Subrahmanyam
  • Patent number: 11126740
    Abstract: An application running in a container is able to access files stored on disk via normal file system calls, but in a manner that remains isolated from applications and processes in other containers. In one aspect, a namespace virtualization component is coupled with a copy-on-write component. When an isolated application is accessing a file stored on disk in a read-only manner, the namespace virtualization component and copy-on-write component grant access to the file. But, if the application requests to modify the file, the copy-on-write component intercepts the I/O and effectively creates a copy of the file in a different storage location on disk. The namespace virtualization component is then responsible for hiding the true location of the copy of the file, via namespace mapping.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: September 21, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sarosh C. Havewala, Christian Gregory Allred
  • Patent number: 11119703
    Abstract: Techniques involve: in response to receiving an access request for a logical address, determining a first virtual storage unit and a first offset within the first virtual storage unit corresponding to the logical address; determining a first set of virtual storage units to which the first virtual storage unit belongs and a position of the first virtual storage unit, determining, from the plurality of physical storage units corresponding to the first set of virtual storage units and based on the position and the first offset, a physical storage unit and a second offset within the physical storage unit corresponding to the logical address; and performing, based on an identifier of the physical storage unit and the second offset, a data access operation requested by the access request. Accordingly, I/O loads on a plurality of disks can be balanced, thereby improving overall performance of a storage system.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: September 14, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Jian Gao, Geng Han, Xinlei Xu, Jianbin Kang
  • Patent number: 11113056
    Abstract: A technique for performing store-to-load forwarding is provided. The technique includes determining a virtual address for data to be loaded for the load instruction, identifying a matching store instruction from one or more store instruction memories by comparing a virtual-address-based comparison value for the load instruction to one or more virtual-address-based comparison values of one or more store instructions, determining a physical address for the load instruction, and validating the load instruction based on a comparison between the physical address of the load instruction and a physical address of the matching store instruction.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: September 7, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John M. King, Matthew T. Sobel
  • Patent number: 11093862
    Abstract: A data index sequence indexing a dataset is received. A location of a data sample identified by a data index in the data index sequence is determined. A scheme is generated for specifying a data movement based on the location. Responsive to determining that the location is a cache of a process, the data sample in the cache can be reused without having to load the data sample from a storage device.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: August 17, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chieh Yang, Guojing Cong, Bilge Acun, Alessandro Morari
  • Patent number: 11086521
    Abstract: Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can be used to provide a unique instruction model based on triggers defined in metadata of the memory objects. This model represents a dynamic dataflow method of execution in which processes are performed based on actual dependencies of the memory objects. This provides a high degree of memory and execution parallelism which in turn provides tolerance of variations in access delays between memory objects. In this model, sequences of instructions are executed and managed based on data access. These sequences can be of arbitrary length but short sequences are more efficient and provide greater parallelism.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: August 10, 2021
    Assignee: Ultrata, LLC
    Inventors: Steven J. Frank, Larry Reback
  • Patent number: 11086778
    Abstract: Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: August 10, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kai Chirca, Timothy David Anderson, Joseph Zbiciak, David E. Smith, Matthew David Pierson
  • Patent number: 11086775
    Abstract: According to one embodiment, an information processing device includes a nonvolatile memory, assignment unit, and transmission unit. The assignment unit assigns logical address spaces to spaces. Each of the spaces is assigned to at least one write management area included in a nonvolatile memory. The write management area is a unit of an area which manages the number of write. The transmission unit transmits a command for the nonvolatile memory and identification data of a space assigned to a logical address space corresponding to the command.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 10, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Daisuke Hashimoto
  • Patent number: 11074208
    Abstract: An adaptive memory expansion scheme is proposed, where one or more memory expansion capable Hosts or Accelerators can have their memory mapped to one or more memory expansion devices. The embodiments below describe discovery, configuration, and mapping schemes that allow independent SCM implementations and CPU-Host implementations to match their memory expansion capabilities. As a result, a memory expansion host (e.g., a memory controller in a CPU or an Accelerator) can declare multiple logical memory expansion pools, each with a unique capacity. These logical memory pools can be matched to physical memory in the SCM cards using windows in a global address map. These windows represent shared memory for the Home Agents (HAs) (e.g., the Host) and the Slave Agent (SAs) (e.g., the memory expansion device).
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: July 27, 2021
    Assignee: XILINX, INC.
    Inventors: Jaideep Dastidar, Millind Mittal
  • Patent number: 11055132
    Abstract: A first processor core with an operating system installed and a second processor core controlled by the first processor core and capable of executing parallel operation processing are included. The second processor core, when detecting a page fault, stops new instruction issue and stops as an issued and uncompleted instruction can be restarted, and also sends notification of page fault detection to the first processor core. The first processor core includes a permissibility judgment part that judges whether or not the page fault is permissible in response to reception of the notification, a page table updating part that updates a page table included by the second processor core in accordance with a result of the judgment by the permissibility judgment part, and a directing part that sends a direction corresponding to a result of the judgment by the permissibility judgment part to the second processor core.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: July 6, 2021
    Assignee: NEC CORPORATION
    Inventor: Yohei Yamada
  • Patent number: 11048542
    Abstract: Implementations disclosed describe a system and a method to execute a virtual machine on a processing device, receive a request to access a memory page identified by a guest virtual memory address (GVA) in an address space of the virtual machine, translate the GVA to a guest physical memory address (GPA) using a guest page table (GPT) comprising a GPT entry mapping the GVA to the GPA, translate the GPA to a host physical address (HPA) of the memory page, store, in a translation lookaside buffer (TLB), a TLB entry mapping the GVA to the HPA, modify the GPT entry to designate the memory page as accessed, detect an attempt by an application to modify the GPT entry; generate, in response to the attempt to modify the GPT entry, a page fault; and flush, in response to the page fault, the TLB entry.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Chuanxiao Dong, Yaozu Dong, Zhiyuan Lv, Zhi Wang
  • Patent number: 11030093
    Abstract: A high efficiency garbage collection method, an associated data storage device and a controller thereof are provided. The high efficiency garbage collection method includes: starting and executing a garbage collection procedure; determining whether a Trim command from a host device is received; in response to the Trim command being received, determining whether target data of the Trim command is stored in a source block of the garbage collection procedure; in response to the target data being stored in the source block, determining whether the target data stored in the source block has been copied to a destination block of the garbage collection procedure; and in response to the target data stored in the source block having been copied to the destination block, changing at least one physical address of the target data of the Trim command to a Trim tag in a logical-to-physical address mapping table.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: June 8, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Ting-Heng Chou, Jian-Wei Sun
  • Patent number: 11030111
    Abstract: A computer-implemented method according to one embodiment includes identifying a data write to a specific position within a virtual address space, determining an entry within a metadata structure that corresponds to the specific position within the virtual address space, and adding state information associated with the data write to the entry within the metadata structure, the state information including a size of the data write within the virtual address space and an alignment of the data write within the virtual address space.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: June 8, 2021
    Assignee: International Business Machines Corporation
    Inventors: Yosef Shatsky, Asaf Porat-Stoler
  • Patent number: 11016884
    Abstract: Virtual block redirection clean-up is accomplished for a virtual block in a mapper tree for a logical volume that is redirected to a destination virtual block in the mapper tree. In response to redirection of the virtual block, a redirection notification is sent to each component in a set of dependent components. Each dependent component may store one or more pointers to pointers located within virtual blocks of the mapper tree. The redirected virtual block is cleaned up in response to determining that each dependent component has expressly indicated, in response to the redirection notification, that it does not store any pointer to any pointer that is located within the redirected virtual block.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: May 25, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Alex Soukhman, Vladimir Shveidel, Ronen Gazit, Uri Shabi
  • Patent number: 11010311
    Abstract: A processing device includes a processor configured to output a memory access instruction issued by a process executed on a virtual machine and a virtual address targeted by the memory access instruction. The processor is configured to perform first translation of translating the virtual address into a real address of a virtual memory. The processor is configured to perform second translation of translating the real address into a physical address of a physical memory. The processor is configured to determine, based on the memory access instruction and an access permission attribute of the real address, whether an access permission violation occurs. The processor is configured to perform, upon determining that an access permission violation occurs, retranslation of translating the virtual address into the real address. The processor is configured to record the virtual address and the real address obtained by the retranslation in a log area of a memory.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: May 18, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Kotaro Kuwahara, Yuki Yoshida
  • Patent number: 10999735
    Abstract: Agencies issue recording devices to personnel for administrating and monitoring controlled calls during the course of their duties. To provide flexible capabilities to agencies, a virtual number is provisioned and configured to enable an operator to administrate controlled calls without dedicated recording devices. Using the virtual number, the operator may setup a controlled call between a victim and a baddie. The victim is contacted via the virtual number by the operator and optionally informed about the controlled call process. In turn, the baddie is contacted using number information of the victim's phone and connected with the victim. Call audio between the victim and baddie is transmitted to the operator. When necessary, the operator may terminate the call remotely from the telephonic device the operator used to setup the call.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: May 4, 2021
    Assignee: CALLYO 2009 CORP
    Inventor: Christopher Ryan Bennett
  • Patent number: 10977199
    Abstract: A first command is received from a virtual or physical host associated with a storage system which includes two or more hosts. The first command comprises one or more physical request page (PRP) entries associated with the non-volatile memory express (NVMe) standard. The one or more PRP entries are modified with an indication of the virtual or physical host. A second command is sent with the modified one or more PRP entries to a solid state drive (SSD). A memory request is received from the SSD, where the memory request comprises the modified one or more PRP entries. The memory request is routed to the virtual or physical host based on the indication of the virtual or physical host in the modified one or more PRP entries.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: April 13, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Salil Suri, Yingdong Li, Szu-Hsien Ho
  • Patent number: 10963382
    Abstract: Table of contents (TOC) pointer cache entry having a pointer for a range of addresses. An address of a called routine and a pointer value of a pointer to a reference data structure to be entered into a reference data structure pointer cache are obtained. The reference data structure pointer cache includes a plurality of entries, and an entry of the plurality of entries includes a stored pointer value for an address range. A determination is made, based on the pointer value, whether an existing entry exists in the reference data structure pointer cache for the pointer value. Based on determining the existing entry exists, one of an address_from field of the existing entry or an address_to field of the existing entry is updated using the address of the called routine. The stored pointer value of the existing entry is usable to access the reference data structure for the address range defined by the address_from field and the address_to field.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: March 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10956189
    Abstract: A method performed by a physical computing system includes, with a hypervisor, presenting a virtualized Remote Direct Memory Access (RDMA) device to a guest, with the hypervisor, allocating a portion of total guest memory to the guest, with the hypervisor, determining a memory threshold for the guest, the memory threshold being based on a number of virtual machines managed by the hypervisor and a size of total guest memory, with the hypervisor, receiving from the guest, a first request to register a first size sub-portion of the portion of total guest memory to the virtualized RDMA device, and with the hypervisor, in response to determining that the first size sub-portion exceeds the memory threshold, returning a notification to the guest, the notification indicating that the first request failed. The first size sub-portion is less than the portion of total guest memory.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: March 23, 2021
    Assignee: RED HAT ISRAEL, LTD.
    Inventors: Michael Tsirkin, Marcel Apfelbaum
  • Patent number: 10949350
    Abstract: Table of contents (TOC) pointer cache entry having a pointer for a range of addresses. An address of a called routine and a pointer value of a pointer to a reference data structure to be entered into a reference data structure pointer cache are obtained. The reference data structure pointer cache includes a plurality of entries, and an entry of the plurality of entries includes a stored pointer value for an address range. A determination is made, based on the pointer value, whether an existing entry exists in the reference data structure pointer cache for the pointer value. Based on determining the existing entry exists, one of an address_from field of the existing entry or an address_to field of the existing entry is updated using the address of the called routine. The stored pointer value of the existing entry is usable to access the reference data structure for the address range defined by the address_from field and the address_to field.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: March 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10949101
    Abstract: Systems, apparatuses, and methods related to storage device operation orchestration are described. A plurality of computing devices (or “tiles”) can be coupled to a controller (e.g., an “orchestration controller”) and an interface. The controller can control operation of the computing devices. For instance, the controller can include circuitry to request a block of data from a memory device coupled to the apparatus, cause a processing unit of at least one computing device of the plurality of computing devices to perform an operation on the block of data in which at least some of the data is ordered, reordered, removed, or discarded, and cause, after some of the data is ordered, reordered, removed, or discarded, the block of data to be transferred to the interface coupled to the plurality of computing devices.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Richard C. Murphy, Glen E. Hush, Vijay S. Ramesh, Allan Porterfield, Anton Korzh
  • Patent number: 10929445
    Abstract: A distributed search framework with virtual indexing is disclosed. According to some embodiments, a virtual index that includes a first physical index is created, where the first physical index includes a first number of shards. A request to index a document is received. In response to the request, whether the first physical index has reached a capacity threshold is determined. In response to determining that the first physical index has reached the capacity threshold, a second physical index is automatically created and added to the virtual index, where the second physical index includes a second number of shards. The document is added into the second physical index.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: February 23, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Steven Y. Zhang, Cherami Liu, Lihui Su, Frank Huang, Jing Yu, Jerry Jourdain
  • Patent number: 10909516
    Abstract: A Basic Input/Output System (BIOS) agent on a Self-Service Terminal (SST) coordinates with a BIOS credential manager that determines when to communicate a BIOS credential for the SST and when to re-generate and re-set a new BIOS credential for the SST.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: February 2, 2021
    Assignee: NCR Corporation
    Inventor: Graham Flett
  • Patent number: 10896136
    Abstract: A storage device includes a storage region in which first data is stored and that is accessed using a first virtual address, and a memory controller configured to control stored data stored in the storage region. The memory controller predicts second data to be accessed using a second virtual address based on the first virtual address, prefetches the second data into an external device, and modifies a physical address mapped to the second virtual address so that the prefetched second data is accessible by a host in communication with the storage device.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: January 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Duck Ho Bae, You Ra Choi
  • Patent number: 10891224
    Abstract: A determination is made that a source group of data management units of a memory component satisfies a threshold wear condition. A wear leveling operation is performed by copying data from a first data management unit of the source group of data management units to a second data management unit of a destination group of data management units of the memory component. A logical address of the first data management unit is determined. Indicators in a mapping data structure are moved from entries associated with the first data management unit to another entries in the mapping data structure that are subsequent to the entries associated with the first data management unit. The indicators are used to access data requested by a host system at the source group of data management units or at the destination group of data management units.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: January 12, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Ning Chen, Jiangli Zhu, Ying Yu Tai
  • Patent number: 10887048
    Abstract: A sink device is configured to establish a Bluetooth connection with a source device. The sink device receives a transmission from the source device that includes a plurality of data blocks, an item of check information, and a plurality of parity blocks during a transmission time duration. The sink device determines, prior to receiving an entirety of the transmission, whether at least one of received data blocks includes an error based on at least the item of check information and, when the at least one of the received data blocks includes the error and prior to receiving all of the plurality of parity blocks, the sink device performs an error correction operation on a first one of the received data blocks based on a first one of the parity blocks.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: January 5, 2021
    Assignee: Apple Inc.
    Inventors: Alon Paycher, Naftali Sommer, Tal Inbar, Sriram Hariharan, Axel Berny, Roi Faust, Eli Ochayon, Sreeraman Anantharaman
  • Patent number: 10877768
    Abstract: Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processor. Instructions may execute out of order in a processor. Information about the logical register-to-physical register mapping resulting from each instruction is stored in entries in program order in the ROB. When the pipeline is interrupted by an instruction that fails to execute, changing program flow, all instructions following the interrupting instruction may be flushed from the processor pipeline. It is important to return the state of the RMT to the state that existed when the interrupting instruction entered the pipeline. To recover the RMT state in response to an interrupting instruction, register mapping information in the ROB entries is traversed to either undo the younger instructions that entered the pipeline after the interrupting instruction or replay the older instructions that entered the pipeline before the interrupting instruction.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: December 29, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Shivam Priyadarshi, Yusuf Cagatay Tekmen, Kiran Ravi Seth, Rodney Wayne Smith, Vignyan Reddy Kothinti Naresh
  • Patent number: 10871903
    Abstract: Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level non-volatile memory (NVM) cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is substantially similar to an intermediate read time associated with the one or more intermediate pages.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: December 22, 2020
    Assignee: Intel Corporation
    Inventors: Anand S. Ramalingam, Pranav Kalavade
  • Patent number: 10867029
    Abstract: Abstraction programming models of enclave security platforms are described, including receiving a request from an enclave client according to a client abstraction protocol, converting the request into a native enclave protocol, and sending the converted request to a native platform. The request may be, for example: a request to instantiate an enclave, verify an attestation report of an enclave, a request to call into an enclave, or a request to allocate memory that is shared with both the enclave and the enclave client.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: December 15, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Manuel Costa
  • Patent number: 10860247
    Abstract: A data writing method is provided. The method includes receiving a first write command and first data corresponding to the first write command from a host system, wherein the first write command instructs to store the first data into a first logical address; copying the first data into a register, responding to the host system that the first write command is completed, and starting to execute a first program operation to program the first data into a first physical page; and in response to determining that the first program operation is failed, reading the first data from the register according to a logical to physical addresses mapping table and mandatorily programming the first data into a second physical page.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: December 8, 2020
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventors: Heng-Lin Yen, Hung-Chih Hsieh, Tzu-Wei Fang, Yu-Hua Hsiao
  • Patent number: 10831673
    Abstract: Memory address translation apparatus comprises page table access circuitry to access page table data to retrieve translation data defining an address translation between an initial memory address in an initial memory address space, and a corresponding output memory address in an output address space; a translation data buffer to store, for a subset of the virtual address space, one or more instances of the translation data; and control circuitry, responsive to an input initial memory address to be translated, to request retrieval of translation data for the input initial memory address from the translation data buffer and, before completion of processing of the request for retrieval from the translation data buffer, to initiate retrieval of translation data for the input initial memory address by the page table access circuitry.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 10, 2020
    Assignee: Arm Limited
    Inventors: Andreas Lars Sandberg, Nikos Nikoleris, Prakash S. Ramrakhyani
  • Patent number: 10810136
    Abstract: An input data may be received. Memory pages may be identified where each of the memory pages includes one or more cache lines. A first index table that includes cache lines may be generated from the memory pages based on the input data. Subsequently, an output data may be provided based on a particular cache line from the cache lines of the first index table.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: October 20, 2020
    Assignee: Fortanix, Inc.
    Inventors: Andrew Leiserson, Jethro Gideon Beekman
  • Patent number: 10802986
    Abstract: A marking capability is used to provide an indication of whether a block of memory is backing an address translation structure of a control program being managed by a virtual machine manager. By providing the marking, the virtual machine manager may check the indication prior to making paging decisions. With this information, a hint may be provided to the hardware to be used in decisions relating to purging associated address translation structures, such as translation look-aside buffer (TLB) entries.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: October 13, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Lisa Cranton Heller, Christian Jacobi, Damian L. Osisek, Anthony Saporito
  • Patent number: 10795739
    Abstract: In one embodiment, a method includes creating, by an operating system executed by a computing device an inter process communication (IPC) channel and a port for a process executed in a user space of the operating system. The IPC channel is associated with a key, and the port comprises a port buffer mapped to a first virtual address space of a kernel of the operating system and to a second virtual address space of the process. A message for the process is written in a message buffer associated with the IPC channel. The kernel determines whether the process is actively consuming messages in the message buffer. Responsive to determining that the process is not actively consuming messages, a notification packet is written in the port buffer. The packet includes an action type and the key and causes the process to consume the message based on the action type and key.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: October 6, 2020
    Assignee: Facebook Technologies, LLC
    Inventors: Christoph Klee, Bernhard Poess, Sumit Kamath
  • Patent number: 10782885
    Abstract: A memory includes a memory array comprising a plurality of pages, a page buffer, and search logic. The page buffer includes first registers, second registers, compare logic, and third registers. The first registers store data read from a page of the memory array. The second registers store a user pattern. The compare logic compares the data stored in the first registers to the user pattern stored in the second registers. The third registers store the comparison results. The search logic is configured to identify addresses of the memory array where the comparison results stored in the third registers indicate a match between the data read from the page and column of the memory array and the user pattern. The first registers are loaded with data from a following page of the memory array concurrently with the search logic identifying addresses indicating a match in a previous page of the memory array.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Vipul Patel
  • Patent number: 10776024
    Abstract: A method for accessing data by a solid state disk is provided, which includes steps of: configuring at least one NAND die to be dedicated for writing random data and other NAND dies to be dedicated for writing sequential data; configuring one of the NAND dies dedicated for writing the sequential data to include memory cells each of which is allowed to be used for storing a data stream having the maximum number of bits; configuring one of the NAND dies dedicated for writing the random data to include memory cells each of which is used for storing a data stream having the number of bits that is smaller the maximum number of the bits; and determining the total number of the bits of one of the data streams of the random data written by the NAND dies and accordingly reconfiguring the NAND dies.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: September 15, 2020
    Assignee: ADATA TECHNOLOGY CO., LTD.
    Inventor: Kuo-Hua Yuan
  • Patent number: 10768965
    Abstract: Systems and methods are provided to reduce the number of redundant copy operations performed as part of a live migration of a virtual machine executing a guest. A hypervisor can queue the copy operations in a processing engine. While pre-copying for the live migration of the VM, the guest may continue to write to the pages. In one embodiment, the processing engine may clear a dirty page just before performing the copy operation of the modified page to a target device, thus extending the window of time to capture any future writes to that page.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: September 8, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Adi Habusha, Ali Ghassan Saidi
  • Patent number: 10762038
    Abstract: System and method for conversion of virtual machine files without requiring copying of the virtual machine payload (data) from one location to another location. By eliminating this step, applicant's invention significantly enhances the efficiency of the conversion process. In one embodiment, a file system or storage system provides indirections to locations of data elements stored on a persistent storage media. A source virtual machine file includes hypervisor metadata (HM) data elements in one hypervisor file format, and virtual machine payload (VMP) data elements.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: September 1, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Jesse St. Laurent, James E. King, III
  • Patent number: 10725918
    Abstract: Table of contents (TOC) pointer cache entry having a pointer for a range of addresses. An address of a called routine and a pointer value of a pointer to a reference data structure to be entered into a reference data structure pointer cache are obtained. The reference data structure pointer cache includes a plurality of entries, and an entry of the plurality of entries includes a stored pointer value for an address range. A determination is made, based on the pointer value, whether an existing entry exists in the reference data structure pointer cache for the pointer value. Based on determining the existing entry exists, one of an address_from field of the existing entry or an address_to field of the existing entry is updated using the address of the called routine. The stored pointer value of the existing entry is usable to access the reference data structure for the address range defined by the address_from field and the address_to field.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: July 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10713216
    Abstract: Implementations are provided herein for using relative generation numbers for deduplicating kernel events modification events. The process can identify multiple modification events that take place on the same inode within a configurable relative amount of time and deduplicate the events against one another. A hash table can be used to store a global list of events associated with inodes, and thus only the hash table need be deduplicated. Filter buffer(s) setup when an Server Message Block (“SMB”) client requests a change notifications on a file and/or directory can then use the data from the hash table(s) to notify clients of change notify events.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: July 14, 2020
    Assignee: EMC IP Holding Company LLC
    Inventor: Dipankar Roy
  • Patent number: 10705982
    Abstract: Described are examples for securing stream data received from a stream source. A secure mode can be enabled, based on a request from an application, for storing the stream data captured from the stream source in a secured buffer. The secured buffer can be allocated in a secure memory based at least in part on enabling the secure mode. A secured buffer identifier of the secured buffer can be provided to a driver of a device providing the stream source for storing the stream data captured from the stream source in the secured buffer. The secured buffer identifier of the secured buffer can also be provided to the application for accessing the stream data stored in the secured buffer.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: July 7, 2020
    Assignee: Microsoft Technology Licensing LLC
    Inventors: Mei L. Wilson, Fabin Shen, Sathyanarayanan Karivaradaswamy, Gerrit L. Swaneveld
  • Patent number: 10705983
    Abstract: Embodiments are provided for implementing a transparent conversion of common virtual storage requests to storage with limited access. Embodiments include providing a storage manager configured to perform address translation for requests, providing a data address translation (DAT) structure configured to connect a higher-level DAT table to a lower-level DAT table, and creating the DAT structure based on a request from a process. Embodiments also include responsive to receiving a storage request, performing a DAT fault process based on validating user credentials associated with an entry of the higher-level DAT table corresponding to the storage request, and responsive to the validation, updating the higher-level DAT table entry to allow access to the restricted-use portion of the common virtual storage, and otherwise, returning a DAT fault for the higher-level DAT table entry.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: July 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Elpida Tzortzatos, Michael Gary Spiegel, Karl David Schmitz, Steven Partlow, Harris M. Morgenstern, David Hom, Peter Fatzinger
  • Patent number: 10701160
    Abstract: A system and method for a function-as-a-service platform that includes creating a set of distinct webservices within a webservice hosting platform, which involves receiving a webservice resource definition, processing the webservice resource definition, and instantiating a webservice of the webservice resource definition within the webservice hosting platform; and invoking a webservice instantiated in the webservice hosting platform for a client device, which involves: receiving a webservice function call request, executing the webservice function call request on a webservice instance, and responding to the webservice function call request with a result of the webservice.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: June 30, 2020
    Assignee: Polybit Inc.
    Inventor: Keith Horwood
  • Patent number: 10691600
    Abstract: Table of contents (TOC) pointer cache entry having a pointer for a range of addresses. An address of a called routine and a pointer value of a pointer to a reference data structure to be entered into a reference data structure pointer cache are obtained. The reference data structure pointer cache includes a plurality of entries, and an entry of the plurality of entries includes a stored pointer value for an address range. A determination is made, based on the pointer value, whether an existing entry exists in the reference data structure pointer cache for the pointer value. Based on determining the existing entry exists, one of an address_from field of the existing entry or an address_to field of the existing entry is updated using the address of the called routine. The stored pointer value of the existing entry is usable to access the reference data structure for the address range defined by the address_from field and the address_to field.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10678702
    Abstract: The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the IOMMU. The controller then performs the virtual address to physical address translations using the one or more selected memory elements.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: June 9, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Sergey Blagodurov, Andrew G. Kegel
  • Patent number: 10678452
    Abstract: A method of distributed file deletion, performed by a storage system, is provided. The method includes receiving, at the storage system, a request to delete a directory and contents of the directory and adding the directory to a first set, listed in a memory in the storage system. The method includes operating on the first set, by examining each directory in the first set to identify subdirectories, adding each identified subdirectory to the first set as a directory, and adding each examined directory to a second set listed in the memory. The method includes deleting in a distributed manner across the storage system without concern for order, contents of directories, and the directories, listed in the second set.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: June 9, 2020
    Assignee: Pure Storage, Inc.
    Inventors: Ronald Karr, Robert Lee, Igor Ostrovsky
  • Patent number: 10678701
    Abstract: The presently disclosed subject matter includes various inventive aspects, which are directed to direct read access of a host computer device to a share storage space in a data storage system, as well as control of the direct read of the host computer device by a control computer device in the data storage system.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: June 9, 2020
    Assignee: Kaminario Technologies Ltd.
    Inventors: Eyal Gordon, Ilan Steinberg, Eli Malul, Shahar Salzman, Gilad Hitron, Eran Mann
  • Patent number: 10673947
    Abstract: A computerized method for enabling a client device seamless access to a plurality of remote storage devices connected to the client device via a communication network. The method comprises receiving a plurality of physical addresses by a controller communicatively coupled to the client device and to a plurality of storage servers, each of the plurality of storage servers communicatively coupled to at least one storage device, the plurality of physical addresses enabling access by the controller to the remote storage devices. A single virtual storage device having a logical address space is generated on the device, wherein each of the plurality of physical addresses is mapped by the controller to a unique logical address of the virtual storage device.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: June 2, 2020
    Assignee: Excelero Storage Ltd.
    Inventors: Yaniv Romem, Omri Mann, Ofer Oshri
  • Patent number: 10664410
    Abstract: In example implementations, mapping fields and respective operation fields may be stored in a translation lookaside buffer (TLB) of a central processing unit (CPU) that is communicatively coupled to a storage volume. The operation fields may be populated based on processes, running on the CPU, corresponding to the respective mapping fields. In response to a storage volume access request generated by one of the processes, and based on contents of one of the mapping fields that matches the storage volume access request, a memory address corresponding to a memory location in the storage volume may be identified. A translated address based on the identified memory address, and contents of the respective operation field, may be transmitted to a media controller communicatively coupled to the CPU and the storage volume.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: May 26, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B Lesartre, Derek Alan Sherlock, Russ W Herrell