Directory Tables (e.g., Dlat, Tlb) Patents (Class 711/207)
  • Patent number: 11449258
    Abstract: Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: September 20, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 11436161
    Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Ravi L. Sahita, Gilbert Neiger, Vedvyas Shanbhogue, David M. Durham, Andrew V. Anderson, David A. Koufaty, Asit K. Mallick, Arumugam Thiyagarajah, Barry E. Huntley, Deepak K. Gupta, Michael Lemay, Joseph F. Cihula, Baiju V. Patel
  • Patent number: 11422946
    Abstract: Systems, apparatuses, and methods for implementing translation lookaside buffer (TLB) striping to enable efficient invalidation operations are described. TLB sizes are growing in width (more features in a given page table entry) and depth (to cover larger memory footprints). A striping scheme is proposed to enable an efficient and high performance method for performing TLB maintenance operations in the face of this growth. Accordingly, a TLB stores first attribute data in a striped manner across a plurality of arrays. The striped manner allows different entries to be searched simultaneously in response to receiving an invalidation request which identifies a particular attribute of a group to be invalidated. Upon receiving an invalidation request, the TLB generates a plurality of indices with an offset between each index and walks through the plurality of arrays by incrementing each index and simultaneously checking the first attribute data in corresponding entries.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 23, 2022
    Assignee: Apple Inc.
    Inventors: John D. Pape, Brian R. Mestan, Peter G. Soderquist
  • Patent number: 11422945
    Abstract: A method for managing memory addresses in a memory subsystem is described. The method includes determining that a chunk of logical addresses is sequentially written such that a set of physical addresses mapped to corresponding logical addresses in the chunk are sequential. Thereafter, the memory subsystem updates an entry in a sequential write table for the chunk to indicate that the chunk was sequentially written and a compressed logical-to-physical (L2P) table based on (1) the sequential write table and (2) a full L2P table. The full L2P table includes a set of full L2P entries and each entry corresponds to a logical address in the chunk and references a physical address in the set of physical addresses. The compressed L2P table includes an entry that references a first physical address of the first set of physical addresses that is also referenced by an entry in the L2P table.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: August 23, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: David A. Palmer
  • Patent number: 11409663
    Abstract: A computer system includes a translation lookaside buffer (TLB) and a processor. The TLB comprises a first TLB array and a second TLB array, and stores entries comprising virtual address information and corresponding real address information. The processor is configured to receive a first virtual address for translation, and to concurrently determine if the TLB stores a physical address associated with the first virtual address based on a first portion and a second portion of the first virtual address. The first portion is associated with a first page size and the second portion is associated with a second page size (different from the first page size). The first portion is used to perform lookup in either one of the first TLB array and the second TLB array and the second portion is used for performing lookup in other one of the first TLB array and the second TLB array.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: August 9, 2022
    Assignee: International Business Machines Corporation
    Inventors: David Campbell, Dwain A. Hicks
  • Patent number: 11403211
    Abstract: A method of operation of a storage system includes: establishing a virtual storage device 1 including allocating portions of a storage media 1, a storage media 2, a storage media N, or a combination thereof including writing data blocks to the virtual storage device 1; determining a pinning status for the data blocks; pinning the data blocks to a logical block address (LBA) range until the pinning status indicates an unpinning of the data blocks; and relocating the data blocks to the storage media 1, the storage media 2, the storage media N, or the combination thereof within the virtual storage device 1 when the pinning status indicates unpinned.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: August 2, 2022
    Assignee: Enmotus, Inc.
    Inventors: Andrew Mills, Marshall Lee
  • Patent number: 11397689
    Abstract: A memory manager includes an internal memory and a hash function circuit. The internal memory includes a V2H (virtual address to hash function) table and an exception mapping table. The V2H table stores at least one virtual address group and a type information on a hash function mapped to the virtual address group. The exception mapping table stores at least one exception virtual address not translated into a physical address by the hash function in the virtual address group and a physical address mapped to the exception virtual address. The has function circuit checks, when a virtual address is provided from a host, type information on a hash function mapped to a virtual address group including the virtual address, by referring to the V2H table included in the internal memory. The has function translates the virtual address into a physical address by using the hash function corresponding to the type information.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: July 26, 2022
    Assignee: SK hynix Inc.
    Inventor: Kyu Hyun Choi
  • Patent number: 11386016
    Abstract: A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB. The unified TLB is configured to determine an order in which to perform a TLB lookup for at least a subset of page sizes of the plurality of page sizes based on the page size residency metadata.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 12, 2022
    Assignee: Ampere Computing LLC
    Inventors: George Van Horn Leming, III, John Gregory Favor, Stephan Jean Jourdan, Jonathan Christopher Perry, Bret Leslie Toll
  • Patent number: 11379152
    Abstract: An apparatus comprises transaction handling circuitry to issue memory access transactions, each memory access transaction specifying an epoch identifier indicative of a current epoch in which the memory access transaction is issued; transaction tracking circuitry to track, for each of at least two epochs, a number of outstanding memory access transactions issued in that epoch; barrier termination circuitry to signal completion of a barrier termination command when the transaction tracking circuitry indicates that there are no outstanding memory access transactions remaining which were issued in one or more epochs preceding a barrier point; and epoch changing circuitry to change the current epoch to a next epoch, in response to a barrier point signal representing said barrier point. This helps to reduce the circuit area overhead for tracking completion of memory access transactions preceding a barrier point.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: July 5, 2022
    Assignee: Arm Limited
    Inventors: Andrew Brookfield Swaine, Peter Andrew Riocreux
  • Patent number: 11366611
    Abstract: A data processing system may include: a host suitable for including a first physical address corresponding to a first logical address in a first command, wherein the first physical address and the first logical address are associated with data, and sending the first command with the first physical address; and a memory system suitable for performing an operation corresponding to the first command by using the first physical address received from the host, and sending a result of the performed command operation to the host as a response, the host may check a time difference between a first time point that the first command is sent and a second time point that the response corresponding to the first command is received, and may determine whether to use the first physical address in a next command, based on a result of the time difference check.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 11354251
    Abstract: A method of offloading a computing kernel from a host central processing unit (CPU) to a co-processor includes obtaining, by an application running on the host CPU, a virtual address of a packet in a user level queue of a general packet processing unit (GPPU) and initializing, by the application, the packet referenced by the virtual address using an application programming interface of a user level device driver (ULDD). The packet includes a plurality of handles corresponding to the computing kernel. The method further includes finalizing, by the ULDD, the packet by including a list of bootstrap translation addresses comprising a physical address and a virtual address for each of the plurality of handles and output by a kernel level device driver (KLDD) of an operating system running on the host CPU, and accessing, by the application using the virtual address, results obtained from the co-processor processing the computing kernel.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: June 7, 2022
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, TECHNOLOGICAL EDUCATIONAL INSTITUTE OF CRETE
    Inventors: Antonio-Marcello Coppola, Georgios Kornaros, Miltos Grammatikakis
  • Patent number: 11354128
    Abstract: In one embodiment, software executing on a data processing system that is capable of performing dynamic operational mode transitions can realize performance improvements by predicting transitions between modes and/or predicting aspects of a new operational mode. Such prediction can allow the processor to begin an early transition into the target mode. The mode transition prediction principles can be applied for various processor mode transitions including 64-bit to 32-bit mode transitions, interrupts, exceptions, traps, virtualization mode transfers, system management mode transfers, and/or secure execution mode transfers.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: June 7, 2022
    Assignee: Intel Corporation
    Inventors: Jason W. Brandt, Vedvyas Shanbhogue, Kameswar Subramaniam
  • Patent number: 11321241
    Abstract: Techniques are disclosed for processing address translations. The techniques include detecting a first miss for a first address translation request for a first address translation in a first translation lookaside buffer, in response to the first miss, fetching the first address translation into the first translation lookaside buffer and evicting a second address translation from the translation lookaside buffer into an instruction cache or local data share memory, detecting a second miss for a second address translation request referencing the second address translation, in the first translation lookaside buffer, and in response to the second miss, fetching the second address translation from the instruction cache or the local data share memory.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 3, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jagadish B. Kotra, Michael W. LeBeane
  • Patent number: 11314445
    Abstract: Aspects of a storage device are provided which allow for identification of control page patterns from previous read commands and prediction of control pages to load in advance for subsequent read commands. The storage device includes a memory configured to store data and a plurality of control pages. Each of the control pages includes a plurality of logical addresses associated with the data. A controller is configured to receive from a host device a plurality of read commands associated with a sequence of the control pages. The controller is further configured to identify and store a control page pattern based on the sequence of control pages and to predict one or more of the control pages from one or more of the other control pages in the sequence in a subsequent plurality of read commands.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: April 26, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Dinesh Kumar Agarwal, Hitesh Golechchha, Sourabh Sankule
  • Patent number: 11301392
    Abstract: A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: April 12, 2022
    Assignee: International Business Machines Corporation
    Inventors: Debapriya Chatterjee, Bryant Cockcroft, Larry Leitner, John A. Schumann, Karen Yokum
  • Patent number: 11288207
    Abstract: Apparatus comprises address translation circuitry configured to access translation data defining a set of memory address translations; transaction handling circuitry to receive translation transactions and to receive invalidation transactions, each translation transaction defining one or more input memory addresses in an input memory address space to be translated to respective output memory addresses in an output memory address space, in which the transaction handling circuitry is configured to control the address translation circuitry to provide the output memory address as a translation response; in which each invalidation transaction defines at least a partial invalidation of the translation data; transaction tracking circuitry to associate an invalidation epoch, of a set of at least two invalidation epochs, with each translation transaction and with each invalidation transaction; and invalidation circuitry to store data defining a given invalidation transaction and, for translation transactions having th
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: March 29, 2022
    Assignee: Arm Limited
    Inventor: Peter Andrew Riocreux
  • Patent number: 11281591
    Abstract: The present disclosure includes a method for implementing a virtual address space. The method includes providing an embedded system having a physical memory defining a physical address space. The method includes providing a program, executable by the embedded system, having a program range having an access characteristic and a memory layout for the virtual address space. The program range is assigned to a virtual address in the virtual address space and has a program size. The method further includes creating the virtual address space on the embedded system, which comprises segments having an identical segment size and a separate virtual start address. The method also includes creating a conversion table on the embedded system for converting a virtual address of the program range into a physical address in the physical memory. Finally, the method converts a memory access to the virtual address into the physical address using the conversion table.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: March 22, 2022
    Assignee: Endress+Hauser Conducta GmbH+Co. KG
    Inventor: Stefan Kempf
  • Patent number: 11281795
    Abstract: A system includes a random number generator generating a random number in response to an event. Control logic generates hierarchical part alignment selectors from the random number. For each secure data block to be stored in volatile storage, a physical address of a first logical address for that secure data block is set based upon the hierarchical part alignment selectors. For each data word within that secure data block, a physical address of a first logical address for that data word is set based upon the hierarchical part alignment selectors. For each data byte within that data word, a physical address of a first logical address for that data byte is set based upon the hierarchical part alignment selectors. A physical address of a logical address for a first data bit within that data byte is set based upon the hierarchical part alignment selectors.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: March 22, 2022
    Assignee: STMicroelectronics International N.V.
    Inventor: Dhulipalla Phaneendra Kumar
  • Patent number: 11269780
    Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, data is stored in memory at one or more logical addresses allocated to an application by an operating system. The data is physically stored in a first memory device of a first memory type (e.g., NVRAM). The operating system determines an access pattern for the stored data. In response to determining the access pattern, the data is moved from the first memory device to a second memory device of a different memory type (e.g., DRAM).
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth Marion Curewitz, Sean S. Eilert, Hongyu Wang, Samuel E. Bradshaw, Shivasankar Gunasekaran, Justin M. Eno, Shivam Swami
  • Patent number: 11263149
    Abstract: The present disclosure describes aspects of cache management of logical-physical translation metadata. In some aspects, a cache (260) for logical-physical translation entries of a storage media system (114) is divided into a plurality of segments (264). An indexer (364) is configured to efficiently balance a distribution of the logical-physical translation entries (252) between the segments (252). A search engine (362) associated with the cache is configured to search respective cache segments (264) and a cache manager (160) may leverage masked search functionality of the search engine (362) to reduce the overhead of cache flush operations.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: March 1, 2022
    Assignee: Marvell Asia PTE, Ltd.
    Inventors: Yu Zeng, Shenghao Gao
  • Patent number: 11262946
    Abstract: Various embodiments described herein provide for selectively sending a cache-based read command, such as a speculative read (SREAD) command in accordance with a Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) memory protocol, to a memory sub-system.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dhawal Bavishi, Patrick A. La Fratta
  • Patent number: 11256633
    Abstract: A processing system includes at least one core, a plurality of accelerator function unit (AFU) and a memory access unit. The memory access unit includes at least one pipeline resource and an arbitrator. The core develops a plurality of tasks. Each of the AFU is used to execute at least one of the tasks which corresponds to several memory access requests. The arbitrator selects one of the AFUs using a round-robin method at each clock period to transmit a corresponding memory access request of the selected AFU to the pipeline resource, so that the selected AFU executes the memory access request through the pipeline resource to read or write data related to the task.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 22, 2022
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Xiaoyang Li, Chen Chen, Zongpu Qi, Tao Li, Xuehua Han, Wei Zhao, Dongxue Gao
  • Patent number: 11256615
    Abstract: A memory system may include a memory device and a controller including a memory, suitable for generating map data for mapping between a physical address corresponding to data within the memory device in response to a command and a logical address received from a host, wherein the controller selects a memory map segment among a plurality of memory map segments, when a read count corresponding to the selected memory map segment is greater than or equal to a first threshold, calculates a map miss ratio of the memory using a total read count and a map miss count, and transmits the selected memory map segment to the host when the map miss ratio is greater than or equal to a second threshold.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: February 22, 2022
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 11243801
    Abstract: Systems and methods for memory management for virtual machines. An example method may comprise determining that a first memory page and a second memory page are mapped to respective guest addresses that are contiguous in a guest address space of a virtual machine running, wherein the first memory page is mapped to a first guest address, determining that the first memory page and the second memory page are mapped to respective host addresses that are not contiguous in a host address space of the host computer system, tracking modifications of the first memory page, causing the virtual machine to copy the first memory page to a third memory page, such that the third memory page and the second memory page are mapped to respective contiguous host addresses, and in response to determining that the first guest page has not been modified, mapping the first guest address to the third memory page.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: February 8, 2022
    Assignee: Red Hat, Inc.
    Inventors: Michael Tsirkin, Andrea Arcangeli
  • Patent number: 11243864
    Abstract: An instruction may be associated with a memory address. During execution of the instruction, the memory address may be translated to a next level memory address. The instruction may also be marked for address tracing. If the instruction is marked for address tracing, then during execution of the instruction, the memory address and the next level memory address may be recorded.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: February 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Bryant Cockcroft, John A. Schumann, Debapriya Chatterjee, Larry Leitner, Kevin Barnett, Karen Yokum
  • Patent number: 11231930
    Abstract: The present disclosure provides methods, systems, and non-transitory computer readable media for fetching data for an accelerator. The methods include detecting an attempt to access a first page of data that is not stored on a primary storage unit of the accelerator; and responsive to detecting the attempt to access the first page of data: assessing activity of the accelerator; determining, based on the assessed activity of the accelerator, a prefetch granularity size; and transferring a chunk of contiguous pages of data of the prefetch granularity size from a memory system connected to the accelerator into the primary storage unit, wherein the transferred chunk of contiguous pages of data include the first page of data.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: January 25, 2022
    Assignee: Alibaba Group Holding Limited
    Inventors: Yongbin Gu, Pengcheng Li, Tao Zhang
  • Patent number: 11231927
    Abstract: In one embodiment, an apparatus includes: an accelerator to execute instructions; an accelerator request decoder coupled to the accelerator to perform a first level decode of requests from the accelerator and direct the requests based on the first level decode, the accelerator request decoder including a memory map to identify a first address range associated with a local memory and a second address range associated with a system memory; and a non-coherent request router coupled to the accelerator request decoder to receive non-coherent requests from the accelerator request decoder and perform a second level decode of the non-coherent requests, the non-coherent request router to route first non-coherent requests to a sideband router of the first die and to direct second non-coherent requests to a computing die. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Robert D. Adler, Amit Kumar Srivastava, Aravindh Anantaraman
  • Patent number: 11232042
    Abstract: Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting a memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PA) in a processor-based system is disclosed. In disclosed examples, a dedicated in-memory TLB is supported in system memory for each process so that one process's cached page table entries do not displace another process's cached page table entries. When a process is scheduled to execute in a central processing unit (CPU), the in-memory TLB address stored for such process can be used by page table walker circuit in the CPU MMU to access the dedicated in-memory TLB for executing the process to perform VA to PA translations in the event of a TLB miss to the MMU TLB. If a TLB miss occurs to the in-memory TLB, the page table walker circuit can walk the page table in the MMU.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: January 25, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Madhavan Thirukkurungudi Venkataraman, Thomas Philip Speier
  • Patent number: 11232536
    Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: January 25, 2022
    Assignee: INTEL CORPORATION
    Inventors: Adam T. Lake, Guei-Yuan Lueh, Balaji Vembu, Murali Ramadoss, Prasoonkumar Surti, Abhishek R. Appu, Altug Koker, Subramaniam M. Maiyuran, Eric C. Samson, David J. Cowperthwaite, Zhi Wang, Kun Tian, David Puffer, Brian T. Lewis
  • Patent number: 11210308
    Abstract: A metadata table manager receives a request for time series data associated with a device, where the request comprises a device identifier associated with the device, and where the time series data comprises a most recently received data element associated with the device. The metadata table manager determines a metadata table that associates the device identifier with one or more time periods during which data associated with the device has been received, and accesses a metadata table entry for the device identifier that includes an indication of a number of data elements received at the most recent time period of the one or more time periods. The metadata table manager queries a time series data store for the first time series data based on the first time period, and outputs a portion of the first time series data, wherein the portion at least comprises the most recently received data element.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: December 28, 2021
    Assignee: Ayla Networks, Inc.
    Inventors: Pankaj Gupta, Haoqing Geng, Sudha Sundaresan
  • Patent number: 11200175
    Abstract: There is provided a data processing apparatus that includes memory circuitry that provides a physical address space, which is logically divided into a plurality of memory segments and stores a plurality of accessors with associated validity indicators. Each of the accessors controls access to a region of the physical address space in dependence on at least its associated validity indicator. Tracking circuitry tracks which of the memory segments contain the accessors and invalidation circuitry responds to a request to invalidate an accessor by determining a set of equivalent accessors with reference to the tracking circuitry, and invalidating the accessor and the equivalent accessors by setting the associated validity indicator of each of the accessor and the equivalent accessors to indicate that the accessor and the equivalent accessors are invalid.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: December 14, 2021
    Assignee: Arm Limited
    Inventor: Matthias Lothar Boettcher
  • Patent number: 11194718
    Abstract: A data processing apparatus is provided, which includes a cache to store operations produced by decoding instructions fetched from memory. The cache is indexed by virtual addresses of the instructions in the memory. Receiving circuitry receives an incoming invalidation request that references a physical address in the memory. Invalidation circuitry invalidates entries in the cache where the virtual address corresponds with the physical address. Coherency is thereby achieved when using a cache that is indexed using virtual addresses.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: December 7, 2021
    Assignee: Arm Limited
    Inventors: Yasuo Ishii, Matthew Andrew Rafacz
  • Patent number: 11194736
    Abstract: A memory controller may include a map cache configured to store one or more of a plurality of map data sub-segments respectively corresponding to a plurality of sub-areas included in each of the plurality of areas, and a map data manager configured to generate information about a map data sub-segment to be provided to a host and which is determined based on a read count for the memory device, and generate information about a map data segment to be deleted from the host and which is determined based on the read count for the memory device and a memory of the host.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: December 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Hye Mi Kang, Eu Joon Byun
  • Patent number: 11194583
    Abstract: Speculative execution using a page-level tracked load order queue includes: determining that a first load instruction targets a determined memory region; and in response to the first load instruction targeting the determined memory region, adding an entry to a page-level tracked load order queue instead of a load order queue, where the entry indicates a page address of a target of the first load instruction.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: December 7, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Krishnan V. Ramani
  • Patent number: 11194651
    Abstract: A method, apparatus, and system for handling a failure of a hardware cryptography/compression accelerator is disclosed. The operations comprise: detecting that a hardware cryptography/compression accelerator at a first data storage system has failed; determining one or more failed cryptography and/or compression operation tasks that were submitted to the hardware cryptography/compression accelerator but were not completed due to the failure of the hardware cryptography/compression accelerator; and performing a remedial operation in response to the hardware cryptography/compression accelerator failure to prevent a systemic failure.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: December 7, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Wei Lin, Yujuan Li, Tao Chen, Yong Zou, Rahul Ugale
  • Patent number: 11194618
    Abstract: This accelerator control device includes: a decision unit which, in processing flow information representing a flow by which a task generated according to a program executed by an accelerator processes data, decides, from among the data, temporary data temporarily generated during execution of a program; a determination unit which, on the basis of an execution status of the task by the accelerator and the processing flow information, determines, for every task using the decided data among the temporary data, whether or not execution of the task has been completed; and a deletion unit which deletes the decided data stored in a memory of the accelerator when execution of every task using the decided data has been completed, whereby, degradation, of processing performance by an accelerator, which occurs when a size of data to be processed by the accelerator is large is avoided.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: December 7, 2021
    Assignee: NEC CORPORATION
    Inventors: Jun Suzuki, Yuki Hayashi
  • Patent number: 11194497
    Abstract: A computer-implemented method for providing tenant aware, variable length, deduplication of data stored on a non-transitory computer readable storage medium. The method is performed at least in part by circuitry and the data comprises a plurality of data items. Each of the plurality of data items is associated with a particular tenant of a group of tenants that store data on the storage medium.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: December 7, 2021
    Assignee: Bottomline Technologies, Inc.
    Inventors: Zenon Buratta, Andy Dobbels
  • Patent number: 11169930
    Abstract: Systems, methods and apparatuses of fine grain data migration in using Memory as a Service (MaaS) are described. For example, a memory status map can be used to identify the cache availability of sub-regions (e.g., cache lines) of a borrowed memory region (e.g., a borrowed remote memory page). Before accessing a virtual memory address in a sub-region, the memory status map is checked. If the sub-region has cache availability in the local memory, the memory management unit uses a physical memory address converted from the virtual memory address to make memory access. Otherwise, the sub-region is cached from the borrowed memory region to the local memory, before the physical memory address is used.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dmitri Yudanov, Ameen D. Akel, Samuel E. Bradshaw, Kenneth Marion Curewitz, Sean Stephen Eilert
  • Patent number: 11169721
    Abstract: A memory system may include a memory device including a plurality of memory blocks; and a controller suitable for controlling the memory device. The controller may include a monitor suitable for monitoring valid data ratios of a first area and a second area and a processor suitable for comparing a first valid data ratio of the first area to a first threshold value, comparing a second valid data ratio of the second area to a second threshold value, and reallocating a target reserved memory block, which is allocated to the second area, to the first area according to the two comparison results.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 9, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 11163695
    Abstract: An information handling system and method for translating virtual addresses to real addresses including a processor for processing data; memory devices for storing the data; and a memory controller configured to control accesses to the memory devices, where the processor is configured, in response to a request to translate a first virtual address to a second physical address, to send from the processor to the memory controller a page directory base and a plurality of memory offsets. The memory controller is configured to: read from the memory devices a first level page directory table using the page directory base and a first level memory offset; combine the first level page directory table with a second level memory offset; and read from the memory devices a second level page directory table using the first level page directory table and the second level memory offset.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Mohit Karve, Brian W. Thompto
  • Patent number: 11151042
    Abstract: A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. Also, the cache memory is divided into a plurality of segments, wherein each segment of the cache memory is direct mapped to a corresponding segment of the memory bank, wherein an address of each of the second plurality of data words is mapped to a corresponding segment in the cache memory, and wherein data words from a particular segment of the memory bank only get stored in a corresponding direct mapped segment of the cache memory.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: October 19, 2021
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Benjamin Louie, Neal Berger, Lester Crudele
  • Patent number: 11144479
    Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Ravi L. Sahita, Gilbert Neiger, Vedvyas Shanbhogue, David M. Durham, Andrew V. Anderson, David A. Koufaty, Asit K. Mallick, Arumugam Thiyagarajah, Barry E. Huntley, Deepak K. Gupta, Michael Lemay, Joseph F. Cihula, Baiju V. Patel
  • Patent number: 11144249
    Abstract: A storage system includes a processor configured to request a write operation of first data corresponding to a first logical address, and requests a write operation of second data corresponding to a second logical address, a memory module including a nonvolatile memory device configured to store the first data and the second data, and a controller configured to convert the first logical address into a first device logical address, and converts the second logical address into a second device logical address based on the first device logical address and a size of the first data, and a storage device configured to store the first data in the storage device based on the first device logical address, and store the second data in the storage device based on the second device logical address.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: October 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Woo Lim, Kyu-Min Park, Do-Han Kim
  • Patent number: 11138133
    Abstract: Various embodiments are generally directed to the providing for mutual authentication and secure distributed processing of multi-party data. In particular, an experiment may be submitted to include the distributed processing of private data owned by multiple distrustful entities. Private data providers may authorize the experiment and securely transfer the private data for processing by trusted computing nodes in a pool of trusted computing nodes.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: October 5, 2021
    Assignee: INTEL CORPORATION
    Inventors: Hormuzd M. Khosravi, Baiju V. Patel
  • Patent number: 11113203
    Abstract: Provided herein may be a controller and a method of operating the same. The controller for controlling an operation of a semiconductor memory device may include a request analyzer, a map cache controller, and a command generator. The request analyzer receives a first request from a host. The map cache controller generates a first mapping segment including a plurality of mapping entries and a flag bit based on the first request, and sets a value of the flag bit depending on whether data corresponding to the first mapping segment is random data or sequential data. The command generator generates a program command for programming the mapping segment.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: September 7, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Patent number: 11113209
    Abstract: An apparatus has a translation cache (100) comprising a number of entries for specifying address translation data. Each entry (260) also specifies a translation context identifier (254) associated with the address translation data and a realm identifier (270) identifying one of a number of realms. Each realm corresponds to at least a portion of at least one software process executed by processing circuitry (8). In response to a memory access a lookup of the translation cache (100) is triggered. When the lookup misses in the cache (100), control circuitry (280) prevents allocation of address translation data to the cache when the current realm is excluded from accessing the target memory region by an owner realm specified for the target memory region. In the lookup, whether a given entry (260) matches the memory access depends on both a translation context identifier comparison and a realm identifier comparison.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: September 7, 2021
    Assignee: Arm Limited
    Inventors: Matthew Lucien Evans, Jason Parker, Gareth Rhys Stockwell, Martin Weidmann
  • Patent number: 11106600
    Abstract: A processing system adjusts a cache replacement priority of cache lines at a cache based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identifies cache lines corresponding to the physical addresses of the evicted TLB entry and evicts the cache lines or adjusts the cache replacement priority of the cache lines so that their eviction from the cache will be accelerated.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: August 31, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Gabriel H. Loh, Paul Moyer
  • Patent number: 11080203
    Abstract: High performance data storage device is disclosed, which has a memory controller dynamically updating mapping information on the temporary storage to manage physical space information mapped to a logical address recognized by a host. The memory controller uses a first bit to an Nth bit of the physical space information to indicate a physical space of the non-volatile memory or a cache address of the data cache space, without using additional bits to map the physical space information to the non-volatile memory or the data cache space, where N is a number greater than one. Among numbers formed by the first to the Nth bit, the memory controller uses numbers corresponding to non-existent physical space of the non-volatile memory to map the physical space information to the non-volatile memory or the data cache space.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: August 3, 2021
    Assignee: SILICON MOTION, INC.
    Inventors: Yang-Chih Shen, Shih-Chang Chang
  • Patent number: 11061572
    Abstract: Described are a method and processing apparatus to tag and track objects related to memory allocation calls. An application or software adds a tag to a memory allocation call to enable object level tracking. An entry is made into an object tracking table, which stores the tag and a variety of statistics related to the object and associated memory devices. The object statistics may be queried by the application to tune power/performance characteristics either by the application making runtime placement decisions, or by off-line code tuning based on a previous run. The application may add a tag to a memory allocation call to specify the type of memory characteristics requested based on the object statistics.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: July 13, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David A. Roberts, Michael Ignatowski
  • Patent number: 11061598
    Abstract: The present disclosure generally relates to relocating data in a storage device and updating a compressed logical to physical (L2P) table in response without invalidating cache entries of the L2P table. After relocating data from a first memory block associated with a first physical address to a second memory block associated with a second physical address, a version indicator of a cache entry corresponding to the first physical address in the L2P table is incremented. One or more cache entries are then added to the L2P table associating the relocated data to the second physical block without invaliding the cache entry corresponding to the first physical address. When a command to read or write the relocated data is received, the storage device searches the L2P table and reads the data from either the first memory block or the second memory block.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: July 13, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Alexander Bazarsky, Tomer Eliash, Yuval Grossman