Directory Tables (e.g., Dlat, Tlb) Patents (Class 711/207)
  • Patent number: 11030012
    Abstract: Methods, apparatus, systems, and articles of manufacture for allocating a workload to an accelerator using machine learning are disclosed. An example apparatus includes a workload attribute determiner to identify a first attribute of a first workload and a second attribute of a second workload. An accelerator selection processor causes at least a portion of the first workload to be executed by at least two accelerators, accesses respective performance metrics corresponding to execution of the first workload by the at least two accelerators, and selects a first accelerator of the at least two accelerators based on the performance metrics. A neural network trainer trains a machine learning model based on an association between the first accelerator and the first attribute of the first workload. A neural network processor processes, using the machine learning model, the second attribute to select one of the at least two accelerators to execute the second workload.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Divya Vijayaraghavan, Denica Larsen, Kooi Chi Ooi, Lady Nataly Pinilla Pico, Min Suet Lim
  • Patent number: 11003584
    Abstract: A data processing system includes support for sub-page granular memory tags. The data processing system comprises at least one core, a memory controller responsive to the core, random access memory (RAM) responsive to the memory controller, and a memory protection module in the memory controller. The memory protection module enables the memory controller to use a memory tag value supplied as part of a memory address to protect data stored at a location that is based on a location value supplied as another part of the memory address. The data processing system also comprises an operating system (OS) which, when executed in the data processing system, manages swapping a page of data out of the RAM to non-volatile storage (NVS) by using a memory tag map (MTM) to apply memory tags to respective subpages within the page being swapped out. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Kai Cong, Karanvir Grewal, Siddhartha Chhabra, Sergej Deutsch, David Michael Durham
  • Patent number: 10997019
    Abstract: The system receives a request to write a first piece of data to a non-volatile memory. The system encodes, based on an error correction code (ECC), the first piece of data to obtain a first ECC codeword which includes a plurality of ordered parts and a first parity. The system writes the plurality of ordered parts in multiple rows. The system writes the first parity to a same row in which a starting ordered part is written. The system updates, in a data structure, entries associated with the ordered parts. A respective entry indicates: a virtual address associated with a respective ordered part, a physical address at which the respective ordered part is written, and an index corresponding to a virtual address associated with a next ordered part. A first entry associated with the starting ordered part further indicates a physical address at which the first parity is written.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: May 4, 2021
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 10997071
    Abstract: Devices and techniques for enhanced flush transfer efficiency in a storage device are described herein. A flush trigger for a user data write can be identified. Here, user data corresponds to the user data write and was stored in a buffer. The size of the user data stored in the buffer is smaller than a write width for a storage device subject to the write. The difference ins the user data size in the buffer and the write width is buffer free space. Additional data can be marshalled in response to the identification of the flush trigger. Here, the additional data size is less than or equal to the buffer free space. The user data and the additional data can then be written to the storage device.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventor: David Aaron Palmer
  • Patent number: 10990538
    Abstract: A TLB receives an access request with respect to a first address and access authorization assigned to the request from an arithmetic operation control unit, translates the first address to a second address, determines the suitability of the access authorization, and outputs the access request with respect to the first address when the access authorization is not suitable. An MMU receives the access request with respect to the first address output from the TLB, translates the first address to the second address, determines the suitability of the access authorization, and outputs a notification of access prohibition to the arithmetic operation control unit when the access authorization is not suitable.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: April 27, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Masakazu Tanomoto
  • Patent number: 10977192
    Abstract: Disclosed herein is an apparatus configured to log transactions of a translation lookaside buffer (TLB) into a software-accessible buffer. The apparatus includes a memory management unit (MMU) configured to translate a logical memory address to a physical memory address for accessing a physical memory. The apparatus also includes a TLB configured to store a plurality of entries, where each entry includes a logical memory page address and an associated physical memory page address. The apparatus further includes a software-accessible buffer and a TLB event logging circuit configured to detect an event associated with an entry of the TLB and store information regarding the detected event in the software-accessible buffer.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: April 13, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Adi Habusha, Nafea Bshara
  • Patent number: 10956327
    Abstract: Disclosed embodiments relate to systems and methods structured to mitigate cache conflicts through hardware assisted redirection of pages. In one example, a processor includes a translation cache to store a physical to slice mapping in response to a cache conflict mitigation request corresponding to a page; and a cache controller to determine whether the translation cache comprises the physical to slice mapping; determine whether one of a plurality of slices in a translation table comprises the physical to slice mapping if the translation cache does not comprise the physical to slice mapping, the translation table communicably coupled to a non-volatile memory; and if the translation table does not comprise the physical to slice mapping, redirect the cache conflict mitigation request to the non-volatile memory; and allocate a new physical to slice mapping for the page to one of the plurality of slices in the translation table.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Adithya Nallan Chakravarthi, Anant Vithal Nori, Jayesh Gaur, Sreenivas Subramoney
  • Patent number: 10956341
    Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Uwe Brandt, Markus Helms, Christian Jacobi, Markus Kaltenbach, Thomas Koehler, Frank Lehnert
  • Patent number: 10936507
    Abstract: In one embodiment, an apparatus includes: a page table circuit to receive a virtual address and to generate at least a portion of a physical address therefrom; and a mapping rule table coupled to the page table circuit, the mapping rule table to receive mapping metadata of a page of a system memory and, based on the mapping metadata, output a mapping rule for the page. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Vivek Kozhikkottu, Esha Choukse, Shankar Ganesh Ramasubramanian, Melin Dadual, Suresh Chittor
  • Patent number: 10915459
    Abstract: A computer system includes a translation lookaside buffer (TLB) and a processor. The TLB comprises a first TLB array and a second TLB array, and stores entries comprising virtual address information and corresponding real address information. The processor is configured to receive a first virtual address for translation, and to concurrently determine if the TLB stores a physical address associated with the first virtual address based on a first portion and a second portion of the first virtual address. The first portion is associated with a first page size and the second portion is associated with a second page size (different from the first page size). The first portion is used to perform lookup in either one of the first TLB array and the second TLB array and the second portion is used for performing lookup in other one of the first TLB array and the second TLB array.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: David Campbell, Dwain A. Hicks
  • Patent number: 10915456
    Abstract: A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Debapriya Chatterjee, Bryant Cockcroft, Larry Leitner, John A. Schumann, Karen Yokum
  • Patent number: 10901632
    Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: January 26, 2021
    Assignee: WESTERN DITIGAL TECHNOLOGIES, INC.
    Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
  • Patent number: 10860231
    Abstract: An operating method of a memory system which includes a controller including one or more processors and a memory device including a plurality of memory blocks, the operating method comprises receiving a first write command; checking whether there is available storage space in a zeroth map segment, using a location of first logical block address (LBA) information written to the zeroth map segment; determining a pattern of the first LBA information and second LBA information corresponding to a first write command when there is no storage space in the zeroth map segment; increasing a sequential count for the second LBA information when the pattern of the first and second LBA information is determined to be a sequential pattern; and performing a map updating operation on a memory block of the memory device by variably adjusting a size of the zeroth map segment based on one or more pieces of LBA information.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 10853262
    Abstract: Memory address translation apparatus comprises page table access circuitry to access a page table to retrieve translation data; a translation data buffer to store one or more instances of the translation data, comprising: an array of storage locations arranged in rows and columns; a row buffer comprising a plurality of entries and comparison circuitry responsive to a key value dependent upon at least the initial memory address, to compare the key value with information stored in each of at least one key entry and an associated value entry for storing at least a representation of a corresponding output memory address, and to identify which of the at least one key entry, if any, is a matching key entry storing information matching the key value; and output circuitry to output, when there is a matching key entry, at least the representation of the output memory address.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: December 1, 2020
    Assignee: ARM Limited
    Inventors: Nikos Nikoleris, Andreas Lars Sandberg, Prakash S. Ramrakhyani, Stephan Diestelhorst
  • Patent number: 10848458
    Abstract: A method including providing: a switching device including a main mapping unit configured to provide a main mapping which maps virtual addresses to direct addresses; management logic configured to store a connection tracking table stored in memory and configured for storing a plurality of connection mappings each including a virtual-to-direct mapping from a virtual address to a direct address; and a migrated connection table stored in memory and configured for storing a plurality of migrated connection mappings each including a virtual-to-migrated-direct mapping from a virtual address to a migrated direct address.
    Type: Grant
    Filed: November 18, 2018
    Date of Patent: November 24, 2020
    Assignee: MELLANOX TECHNOLOGIES TLV LTD.
    Inventors: Alan Lo, Matty Kadosh, Otniel Van Handel, Yonatan Piasetzky, Marian Pritsak, Omer Shabtai
  • Patent number: 10810082
    Abstract: A system and method for improved redundancy in storage devices are disclosed. The method includes receiving a first data block for writing to a storage device; writing the first block to a journal connected with the storage device; associating a first logical address of a group of logical addresses of the journal with a first physical address of the storage; associating the first physical address to an additional second logical address of the storage device, the second logical address not of the group of logical addresses of the journal; and disassociating the first physical address from the first logical address, in response to associating the first physical address with the additional second logical address.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: October 20, 2020
    Assignee: Excelero Storage Ltd.
    Inventors: Yaniv Romem, Ofer Oshri, Omri Mann, Kirill Shoikhet, Daniel Herman Shmulyan, James Jackson
  • Patent number: 10810144
    Abstract: A method includes: providing a DDR interface between a host memory controller and a memory module; and providing a message interface between the host memory controller and the memory module. The memory module includes a non-volatile memory and a DRAM configured as a DRAM cache of the non-volatile memory. Data stored in the non-volatile memory of the memory module is asynchronously accessible by a non-volatile memory controller of the memory module, and data stored in the DRAM cache is directly and synchronously accessible by the host memory controller.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: October 20, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun Young Lim, Mu-Tien Chang, Dimin Niu, Hongzhong Zheng, Indong Kim
  • Patent number: 10802936
    Abstract: In one example a system includes a memory, and at least one memory controller to: detect a failed first memory location of the memory, remap the failed first location of the memory to a spare second location of the memory based on a pointer stored at the failed first memory location, and wear-level the memory. To wear-level the memory, the memory controller may copy data from the spare second location of the memory to a third location of the memory, and keep the pointer in the failed first memory location.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: October 13, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B Lesartre, Ryan Akkerman, Joseph F Orth
  • Patent number: 10782918
    Abstract: Methods, systems, and devices for near-memory data-dependent gathering and packing of data stored in a memory. A processing device extracts a function, a memory source address, and a memory destination address from a near-memory data-dependent gathering and packing primitive. A signal to perform gathering and packing operations based on the primitive is sent to near-memory processing circuitry of a memory device. The near-memory processing circuitry receives the signal, gathers data from the memory device based on the function and the memory source address, and packs the gathered data into the memory device based on the memory destination address.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: September 22, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Shaizeen Aga, Nuwan Jayasena
  • Patent number: 10783083
    Abstract: A cache memory is organized into a plurality of ways and a plurality of address lines. In response to a miss, the cache memory selects a way of the plurality of ways based on a first control variable indicating a way of the plurality of ways and a set of second control variables associated with the address line and with respective ways. Data associated with the miss is written to the selected way. Second control variables associated with other ways are reset if all of the second control variables indicate the associated way was recently replaced. The second control variable associated with the selected way is set to indicate the selected way was recently replaced. The first control variable is set to indicate the selected way. Current values of the first control variable and of the set of second control variables are maintained in the event of a hit.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: September 22, 2020
    Assignee: STMICROELECTRONICS (BEIJING) RESEARCH & DEVELOPMENT CO. LTD
    Inventor: Xiao Kang Jiao
  • Patent number: 10776113
    Abstract: Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit includes receiving, by a load-store unit (LSU) of the processing unit, an OoO window of instructions including a plurality of instructions to be executed OoO, and issuing, by the LSU, instructions from the OoO window. The issuing includes selecting an instruction from the OoO window, the instruction using an effective address. Further, in response to the instruction being a load instruction, it is determined whether the effective address is present in an effective address directory (EAD). In response to the effective address being present in the EAD, the load instruction is issued using the effective address. Further, in response to the instruction being a store instruction, a real address mapped to the effective address is determined from an effective-real translation (ERT) table, and the store instruction is issued using the real address.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: September 15, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher Gonzalez, Bryan Lloyd, Balaram Sinharoy
  • Patent number: 10754790
    Abstract: A memory management unit (MMU) is disclosed. The MMU is configured to receive a translation request from a processing system, wherein the translation request specifies a virtual address to be translated, search a page table stored in a physical memory system for a page table entry that specifies the virtual address, receive a translation lookaside buffer invalidation (TLBI) signal from the processing system, wherein the TLBI signal specifies the virtual address, in response to receiving the TLBI signal specifying the virtual address, invalidate a translation lookaside buffer (TLB) entry in a TLB, wherein the invalidated TLB entry specifies the virtual address and restart the search of the page table for the page table entry that specifies the virtual address.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: August 25, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Jason Norman, Piyush Patel, Rakesh Anigundi, Sadayan Ghows Ghani Sadayan Ebramsah Mo Abdul
  • Patent number: 10754787
    Abstract: The present disclosure includes apparatuses and methods related to virtual address tables. An example method comprises generating an object file that comprises: an instruction comprising a number of arguments; and an address table comprising a number of indexed address elements. Each one of the number of indexed address elements can correspond to a virtual address of a respective one of the number of arguments, wherein the address table can serves as a target for the number of arguments. The method can include storing the object file in a memory.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John D. Leidel, Kyle B. Wheeler
  • Patent number: 10747683
    Abstract: Example devices are disclosed. For example, a device may include a processor, a plurality of translation lookaside buffers, a plurality of switches, and a memory management unit. Each of the translation lookaside buffers may be assigned to a different process of the processor, each of the plurality of switches may include a register for storing a different process identifier, and each of the plurality of switches may be associated with a different one of the translation lookaside buffer buffers. The memory management unit may be for receiving a virtual memory address and a process identifier from the processor and forwarding the process identifier to the plurality of switches. Each of the plurality of switches may be for connecting the memory management unit to a translation associated with the switch when there is a match between the process identifier and the different process identifier stored by the register of the switch.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: August 18, 2020
    Assignees: AT&T Mobility II LLC, AT&T Intellectual Property I, L.P.
    Inventors: Sheldon Kent Meredith, Brandon B. Hilliard, William Cottrill
  • Patent number: 10747682
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Scott Dion Rodgers, Rajesh M. Sankaran, Camron Rust, Sebastian Schoenberg
  • Patent number: 10725932
    Abstract: Systems, methods, and computer programs are disclosed for optimizing headless virtual memory management in a system on chip (SoC) with global translation lookaside buffer shootdown. The SoC comprises an application processor configured to execute a headful virtual machine and one or more SoC processing devices configured to execute a corresponding headless virtual machine. The method comprises issuing a virtual machine mapping command with a headless virtual machine having a first virtual machine identifier. In response to the virtual machine mapping command, a current value stored in a hardware register in the application processor is saved. The first virtual machine identifier associated with the headless virtual machine is loaded into the hardware register. A translation lookaside buffer (TLB) invalidate command is issued while the first virtual machine identifier is loaded in the hardware register.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 28, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Thomas Zeng, Samar Asbe, Adam Openshaw
  • Patent number: 10725928
    Abstract: A system and method for efficiently performing maintenance on a cache. In various embodiments, control logic in a cache controller or elsewhere receives an indication for invalidating a range of virtual-to-physical mappings in a given translation lookaside buffer (TLB). The logic determines a first latency to invalidate entries of the TLB based on a number of addresses in the range and a number of supported page sizes simultaneously stored in the TLB. The logic determines a second latency based on a number of entries in the TLB. If the first latency is greater, then the logic traverses through each TLB entry and invalidates TLB entries storing a virtual address within the range. If the first latency is smaller, then the logic traverses through each address in the range and invalidates TLB entries storing a virtual address within the range.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: July 28, 2020
    Assignee: Apple Inc.
    Inventors: Brian R. Mestan, Pradeep Kanapathipillai, Joshua William Smith
  • Patent number: 10725930
    Abstract: Aspects of the present disclosure configure a memory sub-system to map logical memory addresses to physical memory addresses using a tree data structure in the memory sub-system. For example, a memory sub-system controller of the memory sub-system can generate a tree data structure on cache memory to cache, from non-volatile memory, at least one portion of mapping data, where the non-volatile memory is implemented by a set of memory components separate from the cache memory. The mapping data, stored on the non-volatile memory, can map a set of logical memory addresses to a corresponding set of physical memory addresses of the non-volatile memory, and a node of the tree data structure can comprise node data that describes a memory area of the non-volatile memory where data is written across a sequence of contiguous physical memory addresses.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: David Aaron Palmer
  • Patent number: 10713095
    Abstract: A method of controlling a multi-core processor includes allocating at least one core of the multi-core processor to at least one process for execution; generating a translation table with respect to the at least one process to translate a logical ID of the at least one core allocated to the at least one process to a physical ID; and controlling the at least one process based on the translation table generated with respect to the at least one process.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Donghoon Yoo, Bernhard Egger
  • Patent number: 10698768
    Abstract: The present invention relates generally to backups and more specifically to virtual machine (VM) backups including file exclusion. Aspects of the present invention related to using a specialized buffer to identify a file for exclusion. In embodiments, a file system used by the VM can be used to search for the specialized buffer. In embodiments, when the specialized buffer is located, offsets are noted related to the file associated with the specialized buffer. In embodiments, the offsets are used to zero out blocks associated with the offsets. Thus, the file can be effectively excluded from the backup.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: June 30, 2020
    Assignee: Druva, Inc.
    Inventor: Sudeep Jathar
  • Patent number: 10698836
    Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Markus Helms, Christian Jacobi, Ulrich Mayer, Martin Recktenwald, Johannes C. Reichart, Anthony Saporito, Aaron Tsai
  • Patent number: 10684957
    Abstract: An apparatus and method performs neighborhood-aware virtual to physical address translations. A coalescing opportunity for a first virtual address is determined, based on completing a memory access corresponding to a page walk for a second virtual address. Metadata corresponding to the first virtual address is provided to a page table walk buffer based on the coalescing opportunity and a page walk for the first virtual address is performed based on the metadata corresponding to the first virtual address.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: June 16, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael W. Lebeane, Seunghee Shin
  • Patent number: 10678476
    Abstract: A memory system and an operating method thereof are provided. The memory system includes a controller buffer memory, a host interface configured to receive non-linear host physical addresses and write data from a host, a host address translation section configured to map the non-linear host physical addresses to linear virtual addresses, and a host control section configured to buffer the write data in the controller buffer memory according to the linear virtual addresses.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong Sop Lee
  • Patent number: 10664400
    Abstract: An apparatus has an address translation cache with entries for storing address translation data. Partition configuration storage circuitry stores multiple sets of programmable configuration data each corresponding to a partition identifier identifying a corresponding software execution environment or master device and specifying a corresponding subset of entries of the cache. In response to a translation lookup request specifying a target address and a requesting partition identifier, control circuitry triggers a lookup operation to identify whether the target address hits or misses in the corresponding subset of entries specified by the set of partition configuration data for the requesting partition identifier.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: May 26, 2020
    Assignee: ARM Limited
    Inventor: Andrew Brookfield Swaine
  • Patent number: 10664409
    Abstract: A data storage apparatus includes a nonvolatile memory device including block groups, a random access memory including a sequential map table that stores a sequential map entry for consecutive sequential write logical addresses, among write addresses received from a host apparatus, greater than or equal to a predetermined threshold number, and a processor configured to determine whether or not first sequential write logical addresses are present among logical addresses corresponding to physical addresses for a first region of a first block group when a write operation for the first region of the first block group in response to a write request received from the host apparatus is completed, generate a first sequential map entry for the first sequential write logical addresses when the first sequential write logical addresses are present, and store the first sequential map entry in the sequential map table.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: May 26, 2020
    Assignee: SK hynix Inc.
    Inventors: In Jung, Byeong Gyu Park, Young Ick Cho
  • Patent number: 10657085
    Abstract: Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles W. Gainey, Jr., Klaus Meissner, Damian L. Osisek, Klaus Werner
  • Patent number: 10659556
    Abstract: Provided is a system and method for managing a progressive hybrid web application by storing web content in a local cache. In an example, the method includes receiving a HTTP request from a web application executing on the user device, determining whether requested web content included in the HTTP request is stored in a local cache storage of the user device, and in response to determining the web content associated with the HTTP request is stored in the local cache storage, fetching the web content from the local cache storage and transferring the fetched web content to the web application. According to various aspects, the web content can be provided to the web application executing on the user device via the local cache even in a situation where the user device is not connected to the remote host server of the web application.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: May 19, 2020
    Assignee: SAP SE
    Inventors: Nathan Wang, Walter Mak, Michael Tsz Hong Sung, Edward Chao
  • Patent number: 10628158
    Abstract: Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit includes receiving, by a load-store unit (LSU) of the processing unit, an OoO window of instructions including a plurality of instructions to be executed OoO, and issuing, by the LSU, instructions from the OoO window. The issuing includes selecting an instruction from the OoO window, the instruction using an effective address. Further, in response to the instruction being a load instruction, it is determined whether the effective address is present in an effective address directory (EAD). In response to the effective address being present in the EAD, the load instruction is issued using the effective address. Further, in response to the instruction being a store instruction, a real address mapped to the effective address is determined from an effective-real translation (ERT) table, and the store instruction is issued using the real address.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher Gonzalez, Bryan Lloyd, Balaram Sinharoy
  • Patent number: 10613860
    Abstract: A tagged memory organized is into memory chunks. Each memory chunk has a data field, a type field and an owner address field. The type field indicates type of data stored in the data field. The owner address field indicates which objects own which memory chunks. A memory manager has exclusive ability to allocate the memory chunks, deallocate the memory chunks, write to the memory chunks and read the memory chunks.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: April 7, 2020
    Assignee: ARM Limited
    Inventor: Vincent Roger Maurice Belliard
  • Patent number: 10613989
    Abstract: A host machine uses a range-based address translation system rather than a conventional page-based system. This enables address translation to be performed with improved efficiency, particularly when nest virtual machines are used. A data processing system utilizes range-based address translation to provide fast address translation for virtual machines that use virtual address space.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: April 7, 2020
    Assignee: Arm Limited
    Inventors: Roxana Rusitoru, Jonathan Curtis Beard, Curtis Glenn Dunham
  • Patent number: 10606751
    Abstract: An input/output (I/O) device arranged to receive an information element including a payload, determine control information from the information element, classify the information element based on the control information, and issue a write to one of a plurality of computer-readable media based on the classification of the information element, the write to cause the payload to be written to the one of the plurality of computer-readable media.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: March 31, 2020
    Assignee: INTEL CORPORATION
    Inventors: Andrew Cunningham, Mark D. Gray, Alexander Leckey, Chris MacNamara, Stephen T. Palermo, Pierre Laurent, Niall D. McDonnell, Tomasz Kantecki, Patrick Fleming
  • Patent number: 10599569
    Abstract: A technique for operating a memory management unit (MMU) of a processor includes the MMU detecting that one or more address translation invalidation requests are indicated for an accelerator unit (AU). In response to detecting that the invalidation requests are indicated, the MMU issues a raise barrier request for the AU. In response to detecting a raise barrier response from the AU to the raise barrier request the MMU issues the invalidation requests to the AU. In response to detecting an address translation invalidation response from the AU to each of the invalidation requests, the MMU issues a lower barrier request to the AU. In response to detecting a lower barrier response from the AU to the lower barrier request, the MMU resumes handling address translation check-in and check-out requests received from the AU.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bartholomew Blaner, Jay G. Heaslip, Robert D. Herzl, Jody B. Joyner
  • Patent number: 10599835
    Abstract: Embodiments are disclosed to mitigate the meltdown vulnerability by selectively using page table isolation. Page table isolation is enabled for 64-bit applications, so that unprivileged areas in the kernel address space cannot be accessed in user mode due to speculative execution by the processor. On the other hand, page table isolation is disabled for 32-bit applications thereby providing mapping into unprivileged areas in the kernel address space. However, speculative execution is limited to a 32-bit address space in a 32-bit application, and s access to unprivileged areas in the kernel address space can be inhibited.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: March 24, 2020
    Assignee: VMWARE, INC.
    Inventors: Nadav Amit, Dan Tsafrir, Michael Wei
  • Patent number: 10579410
    Abstract: A method for a virtual machine executed by a hypervisor including receiving a first request to execute a first guest application in the virtual machine, and locating, in view of a first memory context tag associated with the first guest application, an intermediate guest page table including a first mapping of a first range of guest virtual addresses (GVAs) to a first range of guest intermediate addresses (GIAs). The first range of GIAs is allocated for the first guest application in a guest physical address space separate from other addresses in the guest physical address space mapped to random access memory (RAM) for the virtual machine. The method also includes executing the first guest application using the first mapping of the first range of GVAs to the first range of GIAs allocated for the first guest application.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: March 3, 2020
    Assignee: Red Hat, Inc.
    Inventors: Michael Tsirkin, Andrea Arcangeli
  • Patent number: 10552937
    Abstract: Embodiments are generally directed to a scalable memory interface for a graphical processor unit. An embodiment of an apparatus includes a graphical processing unit (GPU) including multiple autonomous engines; a common memory interface for the autonomous engines; and a memory management unit for the common memory interface, the memory management unit including multiple engine modules, wherein each of the engine modules includes a translation-lookaside buffer (TLB) that is dedicated to providing address translation for memory requests for a respective autonomous engine of the plurality of autonomous engines, and a TLB miss tracking mechanism that provides tracking for the respective autonomous engine.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: February 4, 2020
    Assignee: INTEL CORPORATION
    Inventors: Niranjan Cooray, Nicolas Kacevas, Altug Koker, Parth Damani, Satyanarayana Nekkalapu
  • Patent number: 10552338
    Abstract: An apparatus and method are provided for making efficient use of address translation cache resources. The apparatus has an address translation cache having a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Each item of address translation data has a page size indication for a page within the memory system that is associated with that address translation data. Allocation circuitry performs an allocation process to determine the address translation data to be stored in each entry. Further, mode control circuitry is used to switch a mode of operation of the apparatus between a non-skewed mode and at least one skewed mode, dependent on a page size analysis operation.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: February 4, 2020
    Assignee: ARM Limited
    Inventors: Abhishek Raja, Michael Filippo
  • Patent number: 10552340
    Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: February 4, 2020
    Assignee: Oracle International Corporation
    Inventors: John Feehrer, Patrick Stabile, Gregory Onufer, John Johnson
  • Patent number: 10545877
    Abstract: An apparatus and method are provided for accessing an address translation cache. The address translation cache has a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. The virtual address is generated from a plurality of source values. Allocation circuitry is responsive to received address translation data, to allocate an entry within the address translation cache to store the received address translation data. A hash value indication is associated with the allocated entry, where the hash value indication is computed from the plurality of source values used to generate a virtual address associated with the received address translation data.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: January 28, 2020
    Assignee: Arm Limited
    Inventors: Abhishek Raja, Michael Filippo
  • Patent number: 10534715
    Abstract: Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more page walk caches, where operation includes: receiving, at a load/store slice, an instruction to be issued; determining, at the load/store slice, a process type indicating a source of the instruction to be a host process or a guest process; and determining, in accordance with an allocation policy and in dependence upon the process type, an allocation of an entry of the page walk cache, wherein the page walk cache comprises one or more entries for both host processes and guest processes.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dwain A. Hicks, Jonathan H. Raymond, George W. Rohrbaugh, III, Shih-Hsiung S. Tung
  • Patent number: 10534718
    Abstract: An example apparatus for memory addressing can include an array of memory cells. The apparatus can include a memory cache configured to store at least a portion of an address mapping table. The address mapping table can include a number of regions corresponding to respective amounts of logical address space of the array. The address mapping table can map translation units (TUs) to physical locations in the array. Each one of the number of regions can include a first table. The first table can include entries corresponding to respective TU logical address of the respective amounts of logical address space, respective pointers, and respective offsets. Each one of the number of regions can include a second table. The second table can include entries corresponding to respective physical address ranges of the array. The entries of the second table can include respective physical address fields and corresponding respective count fields.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Jonathan M. Haswell