Translation Tables (e.g., Segment And Page Table Or Map) Patents (Class 711/206)
  • Patent number: 11226737
    Abstract: Disclosed herein are systems and method for de-duplicating blocks of data. In one aspect, an exemplary method comprises for each previously de-duplicated block of data of a de-duplication engine, storing de-duplicated pages references by hashes and a block descriptor. The method comprises receiving, at the de-duplication engine, a new block of data for de-duplication assessment and determining a similarity of the received block to the previously de-duplicated blocks. When the received block is determined as being similar to the previously de-duplicated blocks, the method comprises storing the received block without duplication in the de-duplication engine, including pages of the block referenced by the hashes and the block descriptor.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: January 18, 2022
    Assignee: Acronis International GmbH
    Inventors: Oleg Volkov, Andrey Zaitsev, Kirill Korotaev, Serguei Beloussov, Stanislav Protasov
  • Patent number: 11221949
    Abstract: Methods, systems, and devices for multi-state purgatory for garbage collection are described. A processing device can determine a valid data count for a block of data of a memory sub-system. In some case, the valid data count can indicate that the block of data contains invalid data. The processing device can assign the block of data to a first purgatory state based on the valid data count and verify that one or more read operations for the block of data in the first purgatory state are complete based on the first purgatory state. In some examples, the processing device can assign the block of data to a second purgatory state based on the verifying.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: January 11, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Antonio David Bianco
  • Patent number: 11221914
    Abstract: According to one embodiment, a memory system copies content of a first logical-to-physical address translation table corresponding to a first region of a nonvolatile memory to a second logical-to-physical address translation table corresponding to a second region of the nonvolatile memory. When receiving a read request specifying a logical address in the second region, the memory system reads a part of the first data from the first region based on the second logical-to-physical address translation table. The memory system detects a block which satisfies a refresh condition from a first group of blocks allocated to the first region, corrects an error of data of the detected block and writes the corrected data back to the detected block.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: January 11, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11218367
    Abstract: Provided herein are devices, systems, methods and various means, including those related to providing a community internet drive that may utilize a centrally-managed hub as well as storage devices distributed among various networked machines. In some embodiments, the community internet drive can also include features to enable its users to promote and utilize the user's trusted personal relationships while also enabling an open platform for peer-to-peer and/or other types of sharing schemes.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: January 4, 2022
    Assignee: PLANETARY DATA LLC
    Inventor: Robert Alan McEntee
  • Patent number: 11216381
    Abstract: A data storage device includes a memory device and a memory controller. The memory controller selects a predetermined memory device to receive data and accordingly records multiple logical addresses in a first mapping table. The first mapping table records which logical page the data stored in each physical page of the predetermined memory block is directed to. When the predetermined memory block is full, the memory controller edits a second mapping table and a third mapping table according to the first mapping table. The second mapping table corresponds to multiple logical pages and records which memory block and which physical page is the data of each logical page stored in. The third mapping table corresponds to the physical pages of the predetermined memory block and indicates whether each physical page is a valid page or an invalid page.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: January 4, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Kuan-Yu Ke
  • Patent number: 11200183
    Abstract: Implementations of the disclosure provide processing device comprising: an interrupt managing circuit to receive an interrupt message directed to an application container from an assignable interface (AI) of an input/output (I/O) device. The interrupt message comprises an address space identifier (ASID), an interrupt handle and a flag to distinguish the interrupt message from a direct memory access (DMA) message. Responsive to receiving the interrupt message, a data structure associated with the interrupt managing circuit is identified. An interrupt entry from the data structure is selected based on the interrupt handle. It is determined that the ASID associated with the interrupt message matches an ASID in the interrupt entry. Thereupon, an interrupt in the interrupt entry is forwarded to the application container.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 14, 2021
    Assignee: Intel Corporation
    Inventors: Sanjay Kumar, Rajesh M. Sankaran, Philip R. Lantz, Utkarsh Y. Kakaiya, Kun Tian
  • Patent number: 11199997
    Abstract: In one non-limiting embodiment, a method is disclosed for performing a storage device operation on a die is provide having steps of choosing a storage device operation to perform, estimating which die is related to the storage device operation chosen to be performed and performing the storage device operation at the die based on the estimating.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: December 14, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Amir Shaharabany, Hadas Oshinsky
  • Patent number: 11194580
    Abstract: Processing of an instruction fetch from an instruction cache is provided, which includes: determining whether the next instruction fetch is from a same address page as a last instruction fetch from the instruction cache; and based, at least in part, on determining that the next instruction fetch is from the same address page, suppressing for the next instruction fetch an instruction address translation table access, and comparing for an address match results of an instruction directory access for the next instruction fetch with buffered results of a most-recent, instruction address translation table access for a prior instruction fetch from the instruction cache.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: December 7, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 11194712
    Abstract: A memory controller for controlling a memory device including memory blocks is provided. The memory controller includes: a garbage collection state determiner in communication with a host device and configured to receive a garbage collection state request from the host device and determine whether the memory device is in a state that garbage collection is necessary and a block information storage unit in communication with the garbage collection state determiner and configured to receive, from the memory device, bad block generation information including a number of bad blocks included in the memory device that are unable to store data, and store block information including a total number of the memory blocks, the number of bad blocks, and a number of free blocks included in the memory device that are assigned for garbage collection.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: December 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Mi Hee Lee, Dae Gyu Ha, Ho Ryong You
  • Patent number: 11188367
    Abstract: A method is provided for a protection module or a process to use a hypervisor to protect memory pages of a guest operating system on the hypervisor. The method includes modifying a shared memory page in a context of the process, which causes the guest operating system to allocate a private memory page to the process, copy data from the shared memory page to the private memory page, and modify the private memory page. The method further includes causing the hypervisor to protect the private memory page by monitoring the private memory page and generating an alert when the private memory page is accessed.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: November 30, 2021
    Assignee: NICIRA INC.
    Inventor: Sukrut Patil
  • Patent number: 11182302
    Abstract: A memory device, an electronic device, and associated read method are provided. The electronic device includes the memory device and a host device, which are electrically connected to each other. The memory device includes a NAND flash memory and a control logic. The NAND flash memory includes a first physical page, and the first physical page includes a plurality of first acquisition-units. The control logic is electrically connected to the NAND flash memory. The control logic receives a first-page address corresponding to the first physical page from a host device during a first page-read duration. Data stored at the plurality of first acquisition-units are respectively transferred to the host device during a second page-read duration.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: November 23, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Lien Su, Shuo-Nan Hung, Chun-Hsiung Hung
  • Patent number: 11182249
    Abstract: A data storage system includes a plurality of data blocks. A set of data blocks are protected by an erasure correcting code and each of the data blocks in the set of data blocks includes block identification information. The data storage system includes a processor and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to verify the block identification information for each of the data blocks in the set of data blocks at the time of read and, as part of reconstructing a data block, reconstruct the block identification information for the reconstructed data block, and verify the block identification information.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Mario Blaum, Steven Robert Hetzler
  • Patent number: 11175925
    Abstract: Technical solutions are described for a load-store unit (LSU) that executes a plurality of instructions in an out-of-order (OoO) window using multiple LSU pipes. The execution includes selecting an instruction from the OoO window, the instruction using an effective address; and if the instruction is a load instruction: and if the processing unit is operating in single thread mode, creating an entry in a first partition of a load reorder queue (LRQ) if the instruction is issued on a first load pipe, and creating the entry in a second partition of the LRQ if the instruction is issued on a second load pipe. Further, if the processing unit is operating in a multi-thread mode, creating the entry in a first predetermined portion of the first partition of the LRQ if the instruction is issued on the first load pipe and by a first thread of the processing unit.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher J. Gonzalez, Bryan Lloyd, Balaram Sinharoy
  • Patent number: 11175924
    Abstract: Technical solutions are described for a load-store unit (LSU) that executes a plurality of instructions in an out-of-order (OoO) window using multiple LSU pipes. The execution includes selecting an instruction from the OoO window, the instruction using an effective address; and if the instruction is a load instruction: and if the processing unit is operating in single thread mode, creating an entry in a first partition of a load reorder queue (LRQ) if the instruction is issued on a first load pipe, and creating the entry in a second partition of the LRQ if the instruction is issued on a second load pipe. Further, if the processing unit is operating in a multi-thread mode, creating the entry in a first predetermined portion of the first partition of the LRQ if the instruction is issued on the first load pipe and by a first thread of the processing unit.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher J. Gonzalez, Bryan Lloyd, Balaram Sinharoy
  • Patent number: 11163682
    Abstract: Systems, methods and apparatuses for distributed consistency memory. In some embodiments, the apparatus comprises at least one monitoring circuit to monitor for memory accesses to an address space; at least one a monitoring table to store an identifier of the address space; and at least one hardware core to execute an instruction to enable the monitoring circuit.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: November 2, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernet, Narayan Ranganathan, Karthik Kumar, Raj K. Ramanujan, Robert G. Blankenship
  • Patent number: 11157306
    Abstract: To increase the speed with which the hierarchical levels of a Second Layer Address Table (SLAT) are traversed as part of a memory access where the guest physical memory of a virtual machine environment is backed by virtual memory assigned to one or more processes executing on a host computing device, one or more hierarchical levels of tables within the SLAT can be skipped or otherwise not referenced. While the SLAT can be populated with memory correlations at hierarchically higher-levels of tables, the page table of the host computing device, supporting the host computing device's provision of virtual memory, can maintain a corresponding contiguous set of memory correlations at the hierarchically lowest table level, thereby enabling the host computing device to page out, or otherwise manipulate, smaller chunks of memory. If such manipulation occurs, the SLAT can be repopulated with memory correlations at the hierarchically lowest table level.
    Type: Grant
    Filed: August 30, 2020
    Date of Patent: October 26, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yevgeniy Bak, Mehmet Iyigun, Arun U. Kishan
  • Patent number: 11157399
    Abstract: A data storage device includes a memory device and a memory controller. The memory controller is configured to configure a first predetermined memory block which is an SLC memory block and a second predetermined memory block which is a MLC memory block as buffers to receive data. The memory controller determines to use which scheme to receive data in a predetermined period dynamically according to an amount of valid data stored in the memory device. When the memory controller determines to use a first scheme, the memory controller uses the first predetermined memory block to receive data. When the memory controller determines to use a second scheme, the memory controller uses the first predetermined memory block and the second predetermined memory block to receive data. When the memory controller determines to use a third scheme, the memory controller uses the second predetermined memory block to receive data.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: October 26, 2021
    Assignee: SILICON MOTION, INC.
    Inventor: Wen-Sheng Lin
  • Patent number: 11157404
    Abstract: Devices and techniques are disclosed herein for remapping data of flash memory indexed by logical block addresses (LBAs) of a host device in response to re-map requests received at a flash memory system from the host device or in response to re-map requests generated at the flash memory system.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: David Aaron Palmer, Nadav Grosz
  • Patent number: 11151159
    Abstract: A method, computer program product, and computer system for receiving, by a target sent from a source, a first hash signature associated with a page of data. It may be determined that the first hash signature exists on the target. The target may receive a second hash signature sent from the source associated with the page of data. A third hash signature may be generated at the target. It may be determined that the second hash signature matches the third hash signature indicating the page of data exists on the target. A data-less write command may be executed using the page of data existing on the target to deduplicate the page of data existing on the target.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: October 19, 2021
    Assignee: EMC IP Holding Company, LLC
    Inventors: David Meiri, Anton Kucherov
  • Patent number: 11144473
    Abstract: A data processing system includes a memory, a group of input/output (I/O) devices, an input/output memory management unit (IOMMU). The IOMMU is connected to the memory and adapted to allocate a hardware resource from among a group of hardware resources to receive an address translation request for a memory access from an I/O device. The IOMMU detects address translation requests from the plurality of I/O devices. The IOMMU reorders the address translation requests such that an order of dispatching an address translation request is based on a policy associated with the I/O device that is requesting the memory access. The IOMMU selectively allocates a hardware resource to the input/output device, based on the policy that is associated with the I/O device in response to the reordering.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: October 12, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Arkaprava Basu, Michael LeBeane, Eric Van Tassell
  • Patent number: 11144320
    Abstract: Processing of an instruction fetch from an instruction cache is provided, which includes: determining whether the next instruction fetch is in a same cache line of the instruction cache as a last instruction fetch; and based, at least in part, on determining that the next instruction fetch is in the same cache line, suppressing for the next instruction fetch one or more instruction cache-related directory accesses, and forcing for the next instruction an address match signal for the same cache line. The suppressing may include generating a known-to-hit signal where the next fetch is in the same cache line, and the last fetch is not a branch instruction, and issuing an instruction cache hit where a cache line segment of the same cache line having the next instruction has a valid validity bit, the valid validity bit having been retrieved and maintained based on a most-recent, instruction cache-directory-accessed fetch.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 11138128
    Abstract: An apparatus comprises address translation circuitry to perform a translation of virtual addresses into physical addresses in dependence on stored page table mappings between the virtual addresses and the physical addresses. The stored page table mappings comprise tag-guard control information. The apparatus comprises memory access circuitry to perform a tag-guarded memory access in response to a target physical address, the tag-guarded memory access comprising a guard-tag check of comparing an address tag associated with the target physical address with a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the target physical address. The memory access circuitry is arranged to perform a non-tag-guarded memory access to the addressed location in response to the target physical address without performing the guard-tag check in dependence on the tag-guard control information.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: October 5, 2021
    Assignee: ARM Limited
    Inventor: Graeme Peter Barnes
  • Patent number: 11132146
    Abstract: Memory page table invalidations for multiple execution contexts (clients or guests) of a memory system are conventionally queued in a single physical command queue. The multiple execution contexts contend to access the queue, resulting in low performance. Instead of contending with other execution contexts to insert invalidation commands into a single physical command queue, a virtual interface and one or more virtual command queues are allocated to each guest. The execution contexts may simultaneously transmit invalidation commands for the memory system through their respective virtual interface. Additionally, each execution context may also transmit other (less often issued) commands through a hypervisor. Error handling and/or illegal access checks specific to invalidation commands that were previously performed by the hypervisor are now performed by the respective virtual interface(s).
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 28, 2021
    Assignee: NVIDIA Corporation
    Inventors: Kaushal Agarwal, Alexander E. Van Brunt
  • Patent number: 11126576
    Abstract: Provided is an input/output (I/O) execution device possible for a device driver to input and output to and from an I/O device unconnected to a bridge and an I/O device connected to the bridge through the same interface. The device provided with: a device driver for accessing a virtual space area allocated to an I/O device and thereby issuing an I/O command; a device memory management unit for setting the area to a state in which the area generates a page fault when accessed; an access intercept unit for detecting a page fault generated when the device driver accesses the area, detecting the I/O command issuance, and identifying the I/O command; and an I/O packet transmission/reception unit for generating an I/O packet generated when a bridge connecting an I/O device receives the identified I/O command and transmitting the generated packet to an I/O device connected to an un-bridge connecting unit.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 21, 2021
    Assignee: NEC CORPORATION
    Inventors: Jun Suzuki, Yuki Hayashi
  • Patent number: 11099771
    Abstract: A method of deleting tombstones early includes setting an initial-flag in a first record in the storage system, setting a delete-flag in a second record in the storage system, selecting a set of one or more records in the storage system to be written to an extent of the storage system in a merge operation, each of the one or more records being associated with the first key, and performing the merge operation, wherein the second record is not written to the extent during the merge operation based at least in part on a determination that the first record having the initial-flag set is the oldest record in the set and the second record having the delete-flag set is the newest record in the set.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: August 24, 2021
    Assignee: salesforce.com, inc.
    Inventors: Thomas Fanghaenel, Terry Chong, Jameison Bear Martin
  • Patent number: 11100904
    Abstract: According to embodiments, an image drawing apparatus includes: an SRAM; and a transaction conversion unit configured to convert a transaction based on a virtual address indicating a pixel position in a storage area of the SRAM into a transaction based on a physical address in the SRAM. When the storage area is divided into a plurality of windows in a row direction and a column direction so that each window includes one or more lines, and an assigned area which is assigned the physical address in the SRAM is set in each of the windows, the transaction conversion unit converts the transaction based on the virtual address into the transaction based on the physical address based on whether the pixel position indicated by the virtual address is in the assigned area.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: August 24, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Takashi Takemoto, Yuji Hisamatsu, Shinichi Shionoya, Michio Katsuhara
  • Patent number: 11093454
    Abstract: Embodiments are directed to techniques for performing deduplication. A method includes (a) obtaining a digest of a data block logically-positioned within a filesystem, the digest providing a hash value of data of the data block, (b) searching a Most Wanted Digest Cache (MWDC) within system memory for the digest, (c) locating an entry in the MWDC using the digest, wherein this locating indicates that the data block has the same data as another data block located elsewhere within the filesystem, the other data block having been previously persistently-stored, the entry having been added to the MWDC in response to the other data block having been deduplicated at least a plurality number of times, (d) locating a mapping structure referenced by the entry located from the MWDC, the mapping structure providing metadata about the other data block, and (e) deduplicating the data block and the other data block with reference to the located mapping structure.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 17, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Philippe Armangau, Christopher A. Seibel, Bruce E. Caram, Yubing Wang, John Gillono
  • Patent number: 11088846
    Abstract: In one example a computer implemented method comprises encrypting data to be stored in a protected region of a memory using a message authentication code (MAC) having a first value determined using a first key during a first period of time, generating a replay integrity tree structure comprising security metadata for the data stored in the protected region of the memory using the first value of the MAC, and at the end of the first period of time, re-keying the MAC to have a second value determined using a second key at the end of the first period of time, decrypting the data stored in the protected region using the first value for the MAC, re-encrypting the data stored in the protected region using the second value for the MAC, and updating the replay integrity tree using the second value for the MAC. Other examples may be described.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: August 10, 2021
    Assignee: INTEL CORPORATION
    Inventors: Siddhartha Chhabra, Rajat Agarwal, David M. Durham
  • Patent number: 11082231
    Abstract: A processer is provided that includes on-die memory, a protected memory region, and a memory encryption engine (MEE). The MEE includes logic to: receive a request for data in a particular page in the protected region of memory, and access a pointer in an indirection directory, where the pointer is to point to a particular metadata page stored outside the protected region of memory. The particular metadata page includes a first portion of security metadata for use in securing the data of the particular page. The MEE logic is further to access a second portion of the security metadata associated with the particular page from the protected region of memory, and determine authenticity of the data of the particular page based on the first and second portions of the security metadata.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Siddhartha Chhabra, Vedvyas Shanbhogue
  • Patent number: 11055147
    Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Utkarsh Y. Kakaiya, Rajesh Sankaran, Sanjay Kumar, Kun Tian, Philip Lantz
  • Patent number: 11055212
    Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: July 6, 2021
    Assignee: Breker Verification Systems
    Inventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
  • Patent number: 11048623
    Abstract: A memory controller including: a memory configured to store first and second mapping tables; and a hashing module configured to receive a command including a first key from a host and retrieve a first physical address corresponding to the first key by using the first and second mapping tables, wherein the first mapping table is configured to store first region information about a first region corresponding to a partial region of the first key, the first region including at least one segment, and the second mapping table is configured to store a plurality of segments, wherein each segment includes a plurality of hash entries, the plurality of segments are grouped into a plurality of regions, and each of the plurality of hash entries stores a tag corresponding to a key and a physical address corresponding to the key,
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 29, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seung-jun Yang
  • Patent number: 11048644
    Abstract: An access device may be implemented to provide one or more access channels to non-volatile memory. Memory mapping implemented at the access device may direct a memory controller of the access device to perform access requests, replacing an initial storage location with a different storage location to access in the non-volatile memory device. Address scrambling, encryption, and other modifications to performing an access request may be implemented at the access device, in some embodiments, in addition to the memory mapping techniques.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: June 29, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Thomas A. Volpe, Mark Anthony Banse, Steven Scott Larson
  • Patent number: 11048446
    Abstract: Systems and methods for obtaining access to database files in a computing system. A method may include receiving a first call from a database management system requesting access to a database file. The method may further include transmitting a second call to an operating system interface requesting that a memory-mapped data expanse file be created. The method may also include receiving a first address representing the database file in response to successful mapping of the database file to the memory-mapped data expanse file located at the operating system interface.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: June 29, 2021
    Assignee: Uniys Corporation
    Inventors: James F Merten, Warren N Stockton, Michael J. Rieschl, James R McBreen
  • Patent number: 11042486
    Abstract: A method of managing access to a physical memory formed of n memory page frames using a set of virtual address spaces having n virtual address spaces each formed of a plurality p of contiguous memory pages. The method includes receiving a write request to write a block of data to a virtual address within a virtual address space i of the n virtual address spaces, the virtual address defined by the virtual address space i, a memory page j within that virtual address space i and an offset from the start of that memory page j; translating the virtual address to an address of the physical memory using a virtual memory table having n by p entries specifying mappings between memory pages of the virtual address spaces and memory page frames of the physical memory, wherein the physical memory address is defined by: (i) the memory page frame mapped to the memory page j as specified by the virtual memory table, and (ii) the offset of the virtual address; and writing the block of data to the physical memory address.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: June 22, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Robert Brigg, Lorenzo Belli
  • Patent number: 11023374
    Abstract: The invention introduces an apparatus for controlling data access that includes a memory, an access interface and a processing unit. The processing unit is arranged to operably receive logical-to-physical (L2P) mapping information corresponding to a programming operation through the access interface and store the L2P mapping information in the memory; searching the L2P mapping information to obtain a first logical address associated with user data stored in space of each physical address and a second logical address associated with user data stored in space of each next physical address; generating content of a plurality of entries of a link-based L2P mapping sub-table in the order of logical addresses, wherein each entry of the link-based L2P mapping sub-table stores information about a physical address and a second logical address associated with a corresponding first logical address; and store the link-based L2P mapping sub-table.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: June 1, 2021
    Assignee: SILICON MOTION, INC.
    Inventor: Shen-Ting Chiu
  • Patent number: 10997086
    Abstract: Systems and methods for providing shared virtual memory addressing support for a host system are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations. A memory management unit (MMU) is coupled to the processing resources. The MMU to support a first virtual address size for managing allocation of non-shared virtual memory and to support a second virtual address size for managing allocation of shared virtual memory that is shared between the graphics processor and a host.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Altug Koker, Aditya Navale, Ankur Shah, Murali Ramadoss, Ben Ashbaugh, Ronald Silvas
  • Patent number: 10990436
    Abstract: An information handling system includes an input/output (I/O) device and an input/output memory management unit (I/OMMU). The I/OMMU is configured to translate virtual addresses from the I/O device to physical addresses in a memory. The I/O device is configured to send a first virtual address to the I/OMMU, to receive an error indication from the I/OMMU, and to send an interrupt in response to the error indication, wherein the error indication indicates that the I/OMMU failed to translate the particular first address into a first physical address.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: April 27, 2021
    Assignee: Dell Products L.P.
    Inventor: Shyamkumar T. Iyer
  • Patent number: 10977061
    Abstract: A system and method for providing dynamic device virtualization is herein disclosed. According to one embodiment, the computer-implemented method includes providing a hypervisor and one or more guest virtual machines (VMs). Each guest VM is disposed to run a guest user process and the hypervisor is split into a device hypervisor and a compute hypervisor. The computer-implemented method further includes providing an interface between the device hypervisor and the compute hypervisor. The compute hypervisor manages an efficient use of CPU and memory of a host and the device hypervisor manages a device connected to the host by exploiting hardware acceleration of the device.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: April 13, 2021
    Assignee: Dynavisor, Inc.
    Inventor: Sreekumar Ramakrishnan Nair
  • Patent number: 10977171
    Abstract: A method for creating a multi-namespace includes steps of: returning information of a namespace data structure according to a query command from, wherein the information of the namespace data structure comprises a maximum number and a total capacity of supportable namespace; receiving and determining whether a create command for creating a plurality of namespaces is correct, wherein the create command comprises a number of a namespace and a capacity of the namespace; and if the determination is correct, creating a global host logical-flash physical address (H2F) mapping table according to the create command, wherein a number of the global H2F mapping tables is independent of the maximum number of the supportable namespaces and the number of namespace. A method for accessing data in a multi-namespace is also provided.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: April 13, 2021
    Assignee: Silicon Motion, Inc.
    Inventor: Po-Sheng Chou
  • Patent number: 10970224
    Abstract: A computer-implemented method for implementing a full space dynamic address translation (“DAT”) structure and a subspace DAT structure is provided. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space DAT structure and the subspace DAT structure is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled, and switches, by the processor, the context of the DAT structures based on determining that the new context is different from the existing context.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Elpida Tzortzatos, Steven M. Partlow, Scott B. Compton, Christine Michele Yost, Charles F. Webb, Christian Jacobi
  • Patent number: 10956079
    Abstract: Examples herein relate to re-synchronizing data between an upstream volume and a downstream volume, including by communicating data to the downstream volume, from a start point to an end point of the upstream volume, maintaining a first cursor to indicate data, from the start point to the first cursor, that has been communicated to and committed to persistent storage of the downstream volume, and maintaining a second cursor to indicate data, from the first cursor to the second cursor, that has been communicated to the downstream volume and buffered without yet being confirmed as committed to persistent storage of the downstream volume.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: March 23, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Praveen Killamsetti, Tomasz Barszczak, Monil Sanghavi
  • Patent number: 10937477
    Abstract: A circuit includes a selection circuit configured to receive a first address at a first input and a second address at a second input, pass the first address to an output when a select signal has a first logical state, and pass the second address to the output when the select signal has a second logical state different from the first logical state. The circuit also includes a decoder configured to decode the passed first address or second address.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: March 2, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., TSMC CHINA COMPANY, LIMITED, TSMC NANJING COMPANY, LIMITED
    Inventors: XiuLi Yang, Ching-Wei Wu, He-Zhou Wan, Kuan Cheng, Luping Kong
  • Patent number: 10929055
    Abstract: A memory system includes a nonvolatile memory device; and a controller configured to receive an operation command for a target logical address from a host device, and control the nonvolatile memory device in response to the operation command, wherein the controller determines a target logical address range including the target logical address among a plurality of logical address ranges, and determines whether the target logical address has a sequential attribute, based on a target count corresponding to the target logical address range among counts corresponding to the plurality of logical address ranges.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: February 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Beom Rae Jeong
  • Patent number: 10929306
    Abstract: An arithmetic processor includes a request generation circuit which generates an information request including a request address. A translation buffer associates a virtual address of a page with a physical address (PA). A page-table buffer associates data in a page table in a level other than the last level with a PA of the data, and stores the associated data and address. A controller circuit obtains, from the request address, a PA of data in a page table to be accessed when the request address is not stored in the translation buffer. The controller circuit searches in the page-table buffer for the data when the page table to be accessed is in a level other than the last level. The controller circuit obtains the data from a memory, such as a cache memory or a main memory, when the page table to be accessed is in the last level, and registers the data in the translation buffer. The translation buffer may output an erase signal to invalidate all entries in the page-table buffer.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: February 23, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Yuji Shirahige
  • Patent number: 10929061
    Abstract: According to one embodiment, a memory system is configured to include a nonvolatile memory and a controller circuit. The controller circuit is electrically connected to the nonvolatile memory. The controller circuit executes a first process and a second process. The first process manages a history of accesses to first storage areas of the nonvolatile memory. The second process manages a progress of accesses to all storage areas of the first storage areas within a first time limit, based on the history of the accesses.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: February 23, 2021
    Assignees: TOSHIBA INFORMATION SYSTEMS (JAPAN) CORPORATION, TOSHIBA MEMORY CORPORATION
    Inventors: Kouji Watanabe, Kiyotaka Iwasaki
  • Patent number: 10910025
    Abstract: Embodiments of the present invention disclose a method, computer program product, and system for utilizing a block storage device as Dynamic Random-Access Memory (DRAM) space, wherein a computer includes at least one DRAM module and at least one block storage device interfaced to the computer using a double data rate (DDR) interface. During boot up, the computer configures DRAM and block storage devices of the computer for utilization as DRAM or block storage. Then the computer determines that more DRAM space is required. Responsive to determining that more DRAM space is required, the computer transforms a block storage device into DRAM space. Once the computer determines that the transformed block storage device that is being used for DRAM space is no longer needed to be used as DRAM space, the computer transforms the block storage device back to block storage space.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: February 2, 2021
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Gary D. Cudak, Christopher J. Hardee, Adam Roberts
  • Patent number: 10901911
    Abstract: To increase the speed with which a Second Layer Address Table (SLAT) is traversed, memory having the same access permissions is contiguously arranged such that one or more hierarchical levels of the SLAT need not be referenced, thereby resulting in more efficient SLAT traversal. “Slabs” of memory are established whose memory range is sufficiently large that reference to a hierarchically lower level table can be skipped and a hierarchically higher level table's entries can directly identify relevant memory addresses. Such slabs are aligned to avoid smaller intermediate memory ranges. The loading of code or data into memory is performed based on a next available memory location within a slab having equivalent access permissions, or, if such a slab is not available, or if an existing slab does not have a sufficient quantity of available memory remaining, a new slab with the proper access permissions is established.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: January 26, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yevgeniy Bak, Mehmet Iyigun, Jonathan E. Lange
  • Patent number: 10891230
    Abstract: Systems, methods, and apparatuses relating to linear address masking architecture are described. In one embodiment, a hardware processor includes an address generation unit to generate a linear address for a memory access request to a memory, at least one control register comprising a user mode masking bit and a supervisor mode masking bit, a register comprising a current privilege level indication, and a memory management unit to mask out a proper subset of bits inside an address space of the linear address for the memory access request based on the current privilege level indication and either of the user mode masking bit or the supervisor mode masking bit to produce a resultant linear address, and output the resultant linear address.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Ron Gabor, Igor Yanover
  • Patent number: 10891237
    Abstract: An apparatus and method are described for mediate pass through and shared memory page merging. For example, one embodiment of a method comprises: generating a page identifier (PI) for each of a set of guest memory pages, wherein equivalent PIs indicate that the corresponding memory pages are the same; upon detecting that a first guest memory page and a second guest memory page have PIs that are equal, merging the first and second guest memory pages into a single memory page; detecting that the first guest memory page is to be used for a direct memory access (DMA) operation; and responsively unmerging the first and second guest memory pages.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventor: Yao Zu Dong