Abstract: An input/output memory management unit (IOMMU) can assign input/output virtual addresses (IOVA) using a predetermined randomness algorithm according to some examples. For instance, the IOMMU can determine an input/output virtual address (IOVA) using the pre-defined randomness algorithm. Then, the IOMMU can store, in a translation table, an entry which maps the IOVA to a physical memory address of a storage device. Subsequent to storing the entry in the translation table the IOMMU can receive a request from an input/output (IO) device, where the request is to access data at the IOVA. In response to receiving the request, the IOMMU can identify the physical memory address that is mapped to the IOVA in the entry. The IOMMU can then allow the IO device to access the data at the physical memory address.

Abstract: The present disclosure discloses a virtual memory management method and apparatus supporting physical addresses larger than virtual addresses. The method comprises steps of: determining a target virtual address corresponding to an instruction fetch address or a load storage address in any one of a user mode, a supervisor mode, or a machine mode; determining a target physical address corresponding to the target virtual address by accessing a virtual memory management unit, the virtual memory management unit being internally provided with page table entries that map virtual addresses to physical addresses, the bit width of the target virtual address being possibly less than or equal to that of the target physical address, particularly in a many-core application field; and finally, returning the target physical address to a corresponding instruction fetch unit or load memory unit, thereby ensuring the correctness and validity.

Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU writes, in the guest portion, information into guest buffers and/or logs used for communicating information from the IOMMU to the guest operating system. The IOMMU also reads, from the guest portion, information in guest buffers and/or logs used for communicating information from the guest operating system to the IOMMU.

Abstract: In one embodiment, a processing device includes a memory to store a plurality of memory pages having corresponding physical memory addresses in the memory, store an active multilevel page table (MPT) mapping virtual to physical memory addresses for corresponding allocated memory pages stored in the memory, and store a floating MPT at least partially mapping virtual to physical memory addresses for corresponding spare memory pages stored in the memory, the floating and active MPT using a common mapping scheme, and a processor to receive a request to add a virtual to physical address mapping for more memory pages of the plurality of memory pages to the active MPT, and in response to receiving the request, adjoin at least part of the floating MPT to the active MPT so that the active MPT provides the virtual to physical address mapping for at least some memory pages of the spare memory pages.

Abstract: An integrated circuit for translating and reverse-translating the address included in a memory request is disclosed. The integrated circuit may first comprise a processor, a first boundary function, a second boundary function, and a component device. The processor is configured to transmit a memory request to a target module over a bus of the integrated circuit. The memory request requests access to one or more memory mapped resources and the memory request includes a physical address. The first boundary function is configured to translate the physical address to a relative address which operates in or applies to a different address space than an address space that the physical address operates in or applies to. The second boundary function is configured to translate the relative address to the physical address. The device is configured utilize the physical address transmitted by the second boundary function.

Abstract: In one aspect, a computerized method for expanding a graphics processing unit (GPU) memory footprint based on a hybrid-memory of a distributed database system (DDBS) includes the step of providing the DDBS. The DDBS is modified to include a plurality of GPUs; providing a local memory of a GPU of the plurality of GPUs. The method includes the step of filling the local memory of the GPU with one or more digests from the DDBS. The method includes the step of running a distributed general-purpose cluster-computing framework instance on the local memory of the GPU. The method includes the step of fetching data from the local memory of the GPU using the distributed general-purpose cluster-computing framework instance. The method includes the step of storing a result of the fetch operation in the DDBS to extend the local memory of the GPU to handle more data than what is fitted into the local memory of the GPU.

Abstract: Methods, systems, and devices for cache block budgeting techniques are described. In some memory systems, a controller may configure a memory device with a cache. The cache may include a first subset of blocks configured to statically operate in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and a second mode. A block operating in the second mode may be configured to store relatively more bits per memory cell than a block operating in the first mode. The controller may track and store, for each block of the second subset of blocks, a respective ratio of cycles performed in the first mode to cycles performed in the second mode. The controller may select a block from the second subset of blocks to switch between modes responsive to a trigger and based on the respective ratio for the block.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for reading data with an optimization read voltage (RV) table. The method includes: determining one set of RVs for a designated memory-cell type according to a current environmental parameter of a NAND-flash module and content of the optimization RV table; and reading data on a page corresponding to the designated memory-cell type from the NAND-flash module with the set of RVs. The optimization RV table includes multiple records and each record includes one set of RV parameters and an environmental parameter associated with the set of RV parameters.

Abstract: An electronic device includes remapping hardware, a processor, and a Northbridge IC. The remapping hardware converts a virtual address included in an unconverted DMA request into a physical address. The processor executes software to configure the remapping hardware. The Northbridge IC sends the physical address to the processor. When the software changes the configuration of the remapping hardware, the remapping hardware outputs a data draining request to the Northbridge IC. When the Northbridge IC receives the data draining request at a first time, the Northbridge IC suspends unconverted DMA requests after the first time until a second time, and outputs a first data draining response to the remapping hardware at the second time. The remapping hardware receives the first data draining response and notifies the processor that the data draining request has been completed.

Abstract: A method for data defragmentation is disclosed, including: selecting a file that is stored in a content-addressable storage system, the file including a plurality of blocks, and the storage system including a plurality of deduplication chunks; arranging the plurality of blocks in block groups, each block group including a set of consecutive blocks having a combined size that matches a deduplication chunk size of the storage system; aligning each block group with a different one of the plurality of deduplication chunks of the storage system, such that the blocks in each block group are stored in the storage system in an order that is based on the order in which the blocks are positioned within the file.

Abstract: Methods, computer systems, and computer readable medium are described for low latency reads using cached deduplicated data, including: receiving a request to read data from a storage system; query, using a generated hash value associated with the request to read data, one or more deduplication tables that corresponds to the hash value; and responsive to determining that the one or more deduplication tables includes an entry that corresponds to the hash value, using a mapping contained in the entry to perform the requested to read data, wherein the mapping includes a pointer to a physical location where at least a portion of the data is stored.

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

Abstract: Compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer in processor-based devices is disclosed herein. In some aspects, a processor-based device provides a memory management unit (MMU) that includes a TLB and a TLB metadata buffer comprising a plurality of TLB metadata buffer entries storing corresponding TLB metadata. The MMU is configured to select a TLB metadata buffer entry for use in accessing the TLB of the processor-based device. After selecting the TLB metadata buffer entry, the MMU stores a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. When the MMU subsequently receives a memory access request comprising a virtual address (VA), the MMU generates a TLB entry in the TLB for the VA, and stores the active TLB metadata pointer as part of the TLB tag of the TLB entry in lieu of the TLB metadata of the TLB metadata buffer entry.

Abstract: Address translation circuitry is provided to perform address translation on receipt of a first address to generate a second address. The address translation circuitry comprises a page walk controller configured to perform sequential page table lookups in a plurality of page table levels of a page table hierarchy. Portions of the first address are used to index into sequential page table levels. Cache storage is provided to cache entries comprising translation information retrieved by the sequential page table lookups. An entry in the cache storage further comprises in association with the translation information a re-use indicator indicative of a re-use expectation for subsequent information which is subordinate to the translation information of the entry in the page table hierarchy. The address translation circuitry is configured to modify cache usage for the subsequent information in dependence on the re-use indicator.

Abstract: A data storage device stores files in its memory. The files may be logically fragmented in that various parts of a given file may be located in non-continuous logical addresses, which can be disadvantageous. The host can send a request to the data storage device to reduce such logical fragmentation. For example, the host can send a swap command to the data storage device, in response to which the data storage device swaps the logical addresses of data fragments of two different files. This results in the logical address of one or both of the data fragments being continuous with the logical address of another data fragment of the same file. This logical address swap can take place without physically moving the data in the memory.

Abstract: Systems, apparatuses, and methods to secure identity chaining between software/firmware components of trusted computing base. A memory device includes a secure memory region having access control based on cryptography. The secure memory region stores component information about a second component configured to be executed after a first component during booting. Prior to using a component identity of the second component to generate a compound identifier of the first component, health of the second component to be executed is verified based on the component information stored in the secure memory region.

Abstract: Techniques are described for communications in an L2 virtual network of a customer. In an example, the L2 virtual network includes a plurality of L2 compute instances hosted on a set of host machines and a plurality of L2 virtual network interfaces and L2 virtual switches hosted on a set of network virtualization devices. An L2 virtual network interface emulates an L2 port of the L2 virtual network. Information associated with the L2 virtual switches is collected and provided to the customer.

Abstract: A random write method includes: using a wear-leveling module to scan the number of free blocks and the number of bad blocks in a target super logic unit; using a lookup management module to iteratively update, according to the number of current remaining solid-state disk data frames, the number of historically weighted solid-state disk data frames in a long short-term memory network manner; using dynamic write arbitration to determine an adjustment stage based on the number of historically weighted solid-state disk data frames, and determining the expected number of read and write operations per second based on the adjustment stage; and re-updating the number of historically weighted solid-state disk data frames, and adjusting the actual number of read and write operations per second based on the re-updated number of historically weighted solid-state disk data frames and the expected number of read and write operations per second.

Abstract: The present disclosure generally relates to improving space efficiency when storing logical to physical (L2P) entries. Rather than writing a physical block address (PBA) spanning multiple entries, the PBA is split between a first portion stored in the buffer with the remaining bits of the PBA added to the metadata buffer. The metadata buffer is sub-optimal due to the small size of the metadata relative to the entry and therefore, adding extra bits to the metadata buffer will make the metadata buffer more optimal. In this scheme, the alignment is preserved, the system becomes more optimal in terms of DRAM access, and the metadata buffer can be easily optimized and adapted.

Abstract: A processing system includes a processor core for processing instructions and a memory that stores a page table set including an extended page table having an extended page table entry storing extended page table attributes associated with a physical memory page. The system receives a virtual address and translates the virtual address to a physical address for the physical memory page. One or more extended page attributes associated with the physical memory page are retrieved from the extended page table entry based on the virtual address.

Abstract: A method includes: creating L2P tables while programming virtual blocks (VBs) across memory planes; creating an L2P bitmap for each VB, the L2P bitmap identifying logical addresses, within each L2P table, that belong to each VB; creating a VB bitmap for each L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points; creating an updated VB bitmap for a first L2P table based on changes to the first L2P table; determining that an entry in the VB bitmap is different than the entry in the updated VB bitmap, the entry corresponding to a particular VB; identifying an L2P bitmap corresponding to the particular VB; changing a bit within the identified L2P bitmap for an L2P mapping corresponding to the entry; and employing the identified L2P bitmap to determine L2P table(s) of the respective L2P tables that contain valid logical addresses for the particular VB.

Abstract: A version control interface for data provides a layer of abstraction that permits multiple readers and writers to access data lakes concurrently. An overlay file system, based on a data structure such as a tree, is used on top of one or more underlying storage instances to implement the interface. Each tree node tree is identified and accessed by means of any universally unique identifiers. Copy-on-write with the tree data structure implements snapshots of the overlay file system. The snapshots support a long-lived master branch, with point-in-time snapshots of its history, and one or more short-lived private branches. As data objects are written to the data lake, the private branch corresponding to a writer is updated. The private branches are merged back into the master branch using any merging logic, and conflict resolution policies are implemented. Readers read from the updated master branch or from any of the private branches.

Abstract: An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.

Abstract: Multiple logical-to-physical translation tables (L2PTTs) for data storage devices having indirection units of different sizes. In one embodiment, a data storage controller includes a memory interface configured to interface with a memory, the memory including a zoned namespace, the zoned namespace including a plurality of zones. The data storage controller includes a controller memory including two or more logical-to-physical translation tables (L2PTTs), and an electronic processor. The electronic processor is configured to receive data to be stored in a zone of the plurality of zones, determine whether the zone is an active zone, select, in response to determining that the zone is the active zone, a first L2PTT having a first indirection unit size, and select, in response to determining that the zone is not the active zone, a second L2PTT having a second indirection unit size.

Abstract: First and second big data tables may be aligned into compacted and reordered tables, respectively, such that each row of the compacted table and the corresponding similarly-indexed row of the reordered table have equal keys. Advantageously, the time complexity of alignment scales linearly with the number of rows of the data tables, and the compacted and reordered tables may be subsequently joined by parsing once through the tables. Alignment may be extended to three or more big data tables.

Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

Abstract: Examples described herein relate to a system including a first management system having a primary memory including a free memory, a used memory, and a loosely reserved memory, where the loosely reserved memory comprises cache memory having a reclaimable memory; and a processing resource coupled to the primary memory. The processing resource may monitor an amount of the used memory and an amount of an available memory during runtime of the first management system. Further, the processing resource may enable a synchronized reboot of the first management system if the amount of the used memory is greater than a memory exhaustion first threshold or the amount of the available memory is less than a memory exhaustion second threshold, wherein the memory exhaustion first threshold and the memory exhaustion second threshold are determined based on usage of the reclaimable memory and a number of major page faults.

Abstract: A method of creating a trusted execution domain includes initializing, by a processing device executing a trust domain resource manager (TDRM), a trust domain control structure (TDCS) and a trust domain protected memory (TDPM) associated with a trust domain (TD). The method further includes generating a one-time cryptographic key, assigning the one-time cryptographic key to an available host key id (HKID) in a multi-key total memory encryption (MK-TME) engine, and storing the HKID in the TDCS. The method further includes associating a logical processor to the TD, adding a memory page from an address space of the logical processor to the TDPM, and transferring execution control to the logical processor to execute the TD.

Abstract: A digital signal processor, a digital signal processing (DSP) system, and a method for accessing external memory space are disclosed. The digital signal processor may include: a digital signal processing (DSP) core; and a program port and a data port which are connected to the DSP core and configured to access an external memory, where the program port and the data port are respectively configured to communicate with a memory management unit configured for management of an access address.

Abstract: A method for execution by a record processing and storage system includes receiving a plurality of records and generating a plurality of pages that include the plurality of records in accordance with a row-based format. The plurality of pages is stored via a page storage system. Segment generation determination data is generated based on storage utilization data of the page storage system. A plurality of segments is generated from the plurality of pages that include the plurality of records in a column-based format based on the segment generation determination data indicating segments be generated. The plurality of segments is stored via a segment storage system.

Abstract: A set of methods are proposed to increase data security, both in motion and at rest, by creating microshard data fragments. Microshard data fragments are subsets of a data file which are smaller than a defined atomic unit of value (e.g. a fraction of the size of a social security number or valuable password that one seeks to protect). These microshard data fragments are then dispersed across several physical locations, obscuring the value. Additional techniques are proposed to further frustrate unauthorized reassembly attempts and to create system efficiencies.

Abstract: A storage array controller may receive a write request comprising data to be stored at one or more solid-state storage devices. A write granularity associated with the write request may be generated that is less than a logical block size associated with the storage array controller. The data associated with the write request may be segmented based on the generated write granularity. The write request may be executed to store the segmented data at the one or more solid-state storage devices.

Abstract: Systems and methods for performing file-level restore operations for block-level data volumes are described. In some embodiments, the systems and methods restore data from a block-level data volume contained in secondary storage by receiving a request to restore one or more files from the block-level data volume, mounting a virtual disk to the block-level data volume, accessing one or more mount paths established by the virtual disk between the data agent and the block-level data volume, and browsing data from one or more files within the block-level data volume via the established one or more mount paths provided by the virtual disk.

Abstract: A logical-to-physical (L2P) address mapping table is maintained, wherein a plurality of sections of the L2P address mapping table is cached in a volatile memory device. A journal entry count is maintained reflecting a number of L2P journal entries associated with an L2P journal. It is determined that the journal entry count satisfies a first threshold criterion. In response to determining that the journal entry count satisfies the first threshold criterion, a writing of the L2P journal to a non-volatile memory device is triggered. A written journal count reflecting a number of L2P journals written to the non-volatile memory device is maintained. In response to determining that the written journal count satisfies a second threshold criterion, a first section of the plurality of sections of the L2P address mapping table is identified. The first section of the L2P address mapping table is written to the non-volatile memory device.

Abstract: Provided are a GPU and a method of managing a memory address thereby. TLBs are configured using an SRAM and an STT-MRAM so that a storage capacity is significantly improved compared to a case where a TLB is configured using an SRAM. Accordingly, the page hit rate of a TLB can be increased, thereby improving the throughput of a device. Furthermore, after a PTE is first written in the SRAM, a PTE having high frequency of use is selected and moved to the STT-MRAM. Accordingly, an increase in TLB update time which may occur due to the use of the STT-MRAM having a low write speed can be prevented. Furthermore, a read time and read energy consumption can be reduced.

Abstract: A non-volatile storage system includes a memory controller connected to an integrated memory assembly. The integrated memory assembly includes a memory die comprising non-volatile memory cells and a control die bonded to the memory die. The memory controller receives commands from a host, performs logical address to physical address translation (“address translation”) operations for the commands, and instructs the integrated memory assembly to perform one or more operations in support of the command. The control die also includes the ability to perform the address translation. When performing a command from the host, the memory controller can choose to perform the necessary address translation or instruct the control die to perform the address translation. When the control die performs the address translation, the resulting physical address is used by the control die to perform one or more operations in support of the command.

Abstract: Translating virtual addresses to second addresses by a memory controller local to one or more memory devices, wherein the memory controller is not local to a processor, a buffer for storing a plurality of Page Table Entries, or a Page Walk Cache for storing a plurality of page directory entries, the method including by the memory controller: receiving a page directory base and a plurality of memory offsets from the processor; reading a first level page directory entry using the page directory base and a first level memory offset; combining the second level offset and the first level page directory entry; reading a second level page directory entry using the first level page directory entry and the second level memory offset; sending to the processor the first level page directory entry or the second level page directory entry; and sending a page table entry to the processor.

Abstract: Methods, system, and apparatus, including computer programs encoded on computer storage media for data processing are provided. One of the methods includes: establishing a logic contract of a blockchain and one or more data contracts corresponding to the logic contract; deploying the logic contract and the one or more data contracts in the blockchain; storing data of a target block in the blockchain into the one or more data contracts; computing a hash value of each of the one or more data contracts; and determining a hash value of the target block in the blockchain based on the hash value of each of the one or more data contracts.

Abstract: A kernel driver on an endpoint uses a process cache to provide a stream of events associated with processes on the endpoint to a data recorder. The process cache can usefully provide related information about processes such as a name, type or path for the process to the data recorder through the kernel driver. Where a tamper protection cache or similarly secured repository is available, this secure information may also be provided to the data recorder for use in threat detection, forensic analysis and so forth.

Abstract: A controller configures a map table including a map entry associating different address schemes with each other. The controller is configured, for performing map table configuration, to find a target map entry among previous map entries in the map table, merge the current map entry into the target map entry to generate a merged map entry when the target map entry is found, and store the merged map entry in the map table. The target map entry and a current map entry include at least some information which is overlapped.

Abstract: A plurality of zone reset counters and a global reset counter are maintained. A zone reset counter represents a number of times a respective zone of a memory device has been reset. The global reset counter represents a measure of central tendency of the plurality of zone reset counters. A write command directed to a target zone of the memory device is received, and responsive to determining that a target portion of the target zone is not open, a value of the zone reset counter of het target zone is compared to the value of the global reset counter. If the value of the target zone reset counter equals or exceeds the value of the global reset counter, a portion from a free block list is allocated to the target zone. The allocated portion has a highest program erase count among the one or more portions in free block list.

Abstract: A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.

Abstract: A memory system may include a memory device including a first memory block group and a second memory block group; and a memory controller configured to designate a first memory block of memory blocks included in the first memory block group as an open block and designate a second memory block of memory blocks included in the second memory block group as the open block, and perform a program operation on the first and second memory blocks designated as the open blocks. When the first memory block designated as the open block is changed to a closed block, the memory controller may determine whether to designate a third memory block among the memory blocks included in the first or the second memory block group as a new open block based on a number of times voltage abnormalities have occurred on a voltage supplied to the memory device.

Abstract: According to one or more embodiments, lookup, insertion, and deletion operations are allowed to continue during actions required for collision remediation. When relocation operations are used to resolve a collision, information encoded in header portions of the hash table entries that store the key-value pairs indicates when the associated key-value pairs are undergoing relocation. This information facilitates continued access to the RKVS during the relocation process by allowing other processes that access the RKVS to handle relocations without failure. Furthermore, when hash table expansion is needed in order to resolve a collision, a second, larger, hash table is allocated, and lookup operations continue on both the old hash table and the new hash table. One or more embodiments further prevent insertion, lookup, and deletion failures in the RKVS using flags, encoded in header information in hash table entries, that reflect the state of the respective key-value pairs in the store.

Abstract: A hardware control system and a hardware control method are provided. The hardware control system is for controlling a function circuit, and includes a first transformation circuit, a second transformation circuit and an analysis circuit. The first transformation circuit transforms a command from an operating system to an intermediate address. The second transformation circuit transforms the intermediate address to a permission physical address according to an identifier of the operating system, wherein the permission physical address consists of a hardware physical address and a permission value. The analysis circuit analyzes the permission physical address to generate the hardware physical address and the permission value, and determines a control value corresponding to the hardware physical address according to the permission value. The control value is for permitting the operating system to control the function circuit.

Abstract: An apparatus is disclosed. The apparatus may be implemented in a database node or a storage node and includes one or more processors and memory storing instructions for causing the processor to perform a number of operations. Responsive to a page write request, the apparatus determines an identifier corresponding to the requested page, sends component blocks corresponding to the page to a storage node for appending to an append-only storage log of the storage node, receives the physical location of the stored component blocks, and associates the physical storage location of the stored component blocks with the logical identifier corresponding to the page.

Abstract: Aspects of a storage device including a memory and a controller are provided which allow for data associated with a deleted file to be recovered from the memory when the data is overwritten by a new file at the same logical address. To locate the data, the controller may identify a logical address associated with the data based on a directory entry associated with a FAT. The controller may determine a physical location of the data associated with the logical address based on one or more control entries in a L2P mapping table, such as a previous control entry in the table. The controller may also determine the physical location based on a hot count associated with the previous control entry. After the physical location is determined, the controller may associate a new logical address with the physical location of the data to recover the deleted file.

Abstract: The present disclosure describes apparatuses and methods for automatically mapping virtual functions to storage media to enable single root input output virtualization. A storage media switch manages access to virtual functions that execute behind a storage media interface managed by the switch. The switch includes a host interface through which the switch receives host commands. The switch determines virtual function identifiers associated with the host commands and automatically selects the virtual functions of the storage media based on the virtual function identifiers. The switch executes the host commands over the storage media interface using the virtual functions, and after execution, responds via the host interface to each of the host commands. By automatically mapping virtual functions in this way, the switch automatically enables single root input output virtualization of storage media, including storage media that is without native support for input output virtualization.

Abstract: Disclosed herein are systems and method for de-duplicating blocks of data. In one aspect, an exemplary method comprises receiving a block of data at a de-duplication engine that comprises a first block node and a first page node, wherein the first block node stores a single block descriptor for at least two identical blocks previously received and wherein the first page node stores single instances of identical pages in the at least two identical blocks. The method comprises comparing the received block with the at least two identical blocks. In response to determining that the received block partially matches the at least two identical blocks, the method comprises storing a block descriptor of the received block in a second block node and storing at least one page that matches between the received block and the at least two identical blocks in a second page node of the de-duplication engine.

Abstract: Systems and methods for scanning signatures in a string field. In one implementation, the invention provides a method for signature scanning. The method includes receiving a particular string field, scanning the particular string field for a plurality of signatures using a larger scan step size, scanning the particular string field for the remaining signatures that are shorter than what can be scanned by the larger scan step size separately either using the same scanning method but a smaller scan step size or using a different scan method and the same or a smaller scan step size, and outputting any identified signatures in the particular string field.