Translation Tables (e.g., Segment And Page Table Or Map) Patents (Class 711/206)
  • Patent number: 12039049
    Abstract: Systems, apparatuses, and methods to secure identity chaining between software/firmware components of trusted computing base. A memory device includes a secure memory region having access control based on cryptography. The secure memory region stores component information about a second component configured to be executed after a first component during booting. Prior to using a component identity of the second component to generate a compound identifier of the first component, health of the second component to be executed is verified based on the component information stored in the secure memory region.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: July 16, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Zhan Liu
  • Patent number: 12015552
    Abstract: Techniques are described for communications in an L2 virtual network of a customer. In an example, the L2 virtual network includes a plurality of L2 compute instances hosted on a set of host machines and a plurality of L2 virtual network interfaces and L2 virtual switches hosted on a set of network virtualization devices. An L2 virtual network interface emulates an L2 port of the L2 virtual network. Information associated with the L2 virtual switches is collected and provided to the customer.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: June 18, 2024
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Jagwinder Singh Brar, Lucas Michael Kreger-Stickles, Bryce Eugene Bockman, Peter Croft Jones, Shane Baker
  • Patent number: 12008240
    Abstract: A random write method includes: using a wear-leveling module to scan the number of free blocks and the number of bad blocks in a target super logic unit; using a lookup management module to iteratively update, according to the number of current remaining solid-state disk data frames, the number of historically weighted solid-state disk data frames in a long short-term memory network manner; using dynamic write arbitration to determine an adjustment stage based on the number of historically weighted solid-state disk data frames, and determining the expected number of read and write operations per second based on the adjustment stage; and re-updating the number of historically weighted solid-state disk data frames, and adjusting the actual number of read and write operations per second based on the re-updated number of historically weighted solid-state disk data frames and the expected number of read and write operations per second.
    Type: Grant
    Filed: January 23, 2021
    Date of Patent: June 11, 2024
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Qi Song, Baolin Zhao
  • Patent number: 11989127
    Abstract: The present disclosure generally relates to improving space efficiency when storing logical to physical (L2P) entries. Rather than writing a physical block address (PBA) spanning multiple entries, the PBA is split between a first portion stored in the buffer with the remaining bits of the PBA added to the metadata buffer. The metadata buffer is sub-optimal due to the small size of the metadata relative to the entry and therefore, adding extra bits to the metadata buffer will make the metadata buffer more optimal. In this scheme, the alignment is preserved, the system becomes more optimal in terms of DRAM access, and the metadata buffer can be easily optimized and adapted.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: May 21, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 11954026
    Abstract: A processing system includes a processor core for processing instructions and a memory that stores a page table set including an extended page table having an extended page table entry storing extended page table attributes associated with a physical memory page. The system receives a virtual address and translates the virtual address to a physical address for the physical memory page. One or more extended page attributes associated with the physical memory page are retrieved from the extended page table entry based on the virtual address.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: April 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David Kaplan, David S. Christie
  • Patent number: 11928063
    Abstract: A method includes: creating L2P tables while programming virtual blocks (VBs) across memory planes; creating an L2P bitmap for each VB, the L2P bitmap identifying logical addresses, within each L2P table, that belong to each VB; creating a VB bitmap for each L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points; creating an updated VB bitmap for a first L2P table based on changes to the first L2P table; determining that an entry in the VB bitmap is different than the entry in the updated VB bitmap, the entry corresponding to a particular VB; identifying an L2P bitmap corresponding to the particular VB; changing a bit within the identified L2P bitmap for an L2P mapping corresponding to the entry; and employing the identified L2P bitmap to determine L2P table(s) of the respective L2P tables that contain valid logical addresses for the particular VB.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Nicola Colella, Antonino Pollio, Gianfranco Ferrante
  • Patent number: 11921656
    Abstract: An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: March 5, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Krishna T. Malladi, Hongzhong Zheng
  • Patent number: 11921704
    Abstract: A version control interface for data provides a layer of abstraction that permits multiple readers and writers to access data lakes concurrently. An overlay file system, based on a data structure such as a tree, is used on top of one or more underlying storage instances to implement the interface. Each tree node tree is identified and accessed by means of any universally unique identifiers. Copy-on-write with the tree data structure implements snapshots of the overlay file system. The snapshots support a long-lived master branch, with point-in-time snapshots of its history, and one or more short-lived private branches. As data objects are written to the data lake, the private branch corresponding to a writer is updated. The private branches are merged back into the master branch using any merging logic, and conflict resolution policies are implemented. Readers read from the updated master branch or from any of the private branches.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: March 5, 2024
    Assignee: VMware, Inc.
    Inventors: Abhishek Gupta, Richard P. Spillane, Christos Karamanolis, Marin Nozhchev
  • Patent number: 11874771
    Abstract: Multiple logical-to-physical translation tables (L2PTTs) for data storage devices having indirection units of different sizes. In one embodiment, a data storage controller includes a memory interface configured to interface with a memory, the memory including a zoned namespace, the zoned namespace including a plurality of zones. The data storage controller includes a controller memory including two or more logical-to-physical translation tables (L2PTTs), and an electronic processor. The electronic processor is configured to receive data to be stored in a zone of the plurality of zones, determine whether the zone is an active zone, select, in response to determining that the zone is the active zone, a first L2PTT having a first indirection unit size, and select, in response to determining that the zone is not the active zone, a second L2PTT having a second indirection unit size.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: January 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Arvind Kumar V M, Ravishankar Surianarayanan
  • Patent number: 11868331
    Abstract: First and second big data tables may be aligned into compacted and reordered tables, respectively, such that each row of the compacted table and the corresponding similarly-indexed row of the reordered table have equal keys. Advantageously, the time complexity of alignment scales linearly with the number of rows of the data tables, and the compacted and reordered tables may be subsequently joined by parsing once through the tables. Alignment may be extended to three or more big data tables.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: January 9, 2024
    Inventors: Michael Riddle, Michael Dushkoff
  • Patent number: 11860754
    Abstract: Examples described herein relate to a system including a first management system having a primary memory including a free memory, a used memory, and a loosely reserved memory, where the loosely reserved memory comprises cache memory having a reclaimable memory; and a processing resource coupled to the primary memory. The processing resource may monitor an amount of the used memory and an amount of an available memory during runtime of the first management system. Further, the processing resource may enable a synchronized reboot of the first management system if the amount of the used memory is greater than a memory exhaustion first threshold or the amount of the available memory is less than a memory exhaustion second threshold, wherein the memory exhaustion first threshold and the memory exhaustion second threshold are determined based on usage of the reclaimable memory and a number of major page faults.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: January 2, 2024
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Christopher Murray
  • Patent number: 11860670
    Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: January 2, 2024
    Assignee: Intel Corporation
    Inventors: Monam Agarwal, Anand K. Enamandram, Wei Chen, Kerry Vander Kamp, Robert A. Branch, Yen-Cheng Liu
  • Patent number: 11829517
    Abstract: A method of creating a trusted execution domain includes initializing, by a processing device executing a trust domain resource manager (TDRM), a trust domain control structure (TDCS) and a trust domain protected memory (TDPM) associated with a trust domain (TD). The method further includes generating a one-time cryptographic key, assigning the one-time cryptographic key to an available host key id (HKID) in a multi-key total memory encryption (MK-TME) engine, and storing the HKID in the TDCS. The method further includes associating a logical processor to the TD, adding a memory page from an address space of the logical processor to the TDPM, and transferring execution control to the logical processor to execute the TD.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Hormuzd Khosravi, Dror Caspi, Arie Aharon
  • Patent number: 11782846
    Abstract: A digital signal processor, a digital signal processing (DSP) system, and a method for accessing external memory space are disclosed. The digital signal processor may include: a digital signal processing (DSP) core; and a program port and a data port which are connected to the DSP core and configured to access an external memory, where the program port and the data port are respectively configured to communicate with a memory management unit configured for management of an access address.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: October 10, 2023
    Assignee: ZTE CORPORATION
    Inventor: Xueting Sun
  • Patent number: 11755589
    Abstract: A method for execution by a record processing and storage system includes receiving a plurality of records and generating a plurality of pages that include the plurality of records in accordance with a row-based format. The plurality of pages is stored via a page storage system. Segment generation determination data is generated based on storage utilization data of the page storage system. A plurality of segments is generated from the plurality of pages that include the plurality of records in a column-based format based on the segment generation determination data indicating segments be generated. The plurality of segments is stored via a segment storage system.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: September 12, 2023
    Assignee: Ocient Holdings LLC
    Inventor: George Kondiles
  • Patent number: 11755759
    Abstract: A set of methods are proposed to increase data security, both in motion and at rest, by creating microshard data fragments. Microshard data fragments are subsets of a data file which are smaller than a defined atomic unit of value (e.g. a fraction of the size of a social security number or valuable password that one seeks to protect). These microshard data fragments are then dispersed across several physical locations, obscuring the value. Additional techniques are proposed to further frustrate unauthorized reassembly attempts and to create system efficiencies.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 12, 2023
    Assignee: SHARDSECURE, INC.
    Inventors: Louis Steinberg, Chihli Lu
  • Patent number: 11741003
    Abstract: A storage array controller may receive a write request comprising data to be stored at one or more solid-state storage devices. A write granularity associated with the write request may be generated that is less than a logical block size associated with the storage array controller. The data associated with the write request may be segmented based on the generated write granularity. The write request may be executed to store the segmented data at the one or more solid-state storage devices.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: August 29, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Gordon James Coleman, Eric Seppanen
  • Patent number: 11733877
    Abstract: Systems and methods for performing file-level restore operations for block-level data volumes are described. In some embodiments, the systems and methods restore data from a block-level data volume contained in secondary storage by receiving a request to restore one or more files from the block-level data volume, mounting a virtual disk to the block-level data volume, accessing one or more mount paths established by the virtual disk between the data agent and the block-level data volume, and browsing data from one or more files within the block-level data volume via the established one or more mount paths provided by the virtual disk.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: August 22, 2023
    Assignee: Commvault Systems, Inc.
    Inventors: Sri Karthik Bhagi, Sunil Kumar Gutta, Vijay H. Agrawal, Rahul S. Pawar
  • Patent number: 11714748
    Abstract: A logical-to-physical (L2P) address mapping table is maintained, wherein a plurality of sections of the L2P address mapping table is cached in a volatile memory device. A journal entry count is maintained reflecting a number of L2P journal entries associated with an L2P journal. It is determined that the journal entry count satisfies a first threshold criterion. In response to determining that the journal entry count satisfies the first threshold criterion, a writing of the L2P journal to a non-volatile memory device is triggered. A written journal count reflecting a number of L2P journals written to the non-volatile memory device is maintained. In response to determining that the written journal count satisfies a second threshold criterion, a first section of the plurality of sections of the L2P address mapping table is identified. The first section of the L2P address mapping table is written to the non-volatile memory device.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: August 1, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Byron Harris, Daniel Boals, Abedon Madril
  • Patent number: 11704018
    Abstract: Provided are a GPU and a method of managing a memory address thereby. TLBs are configured using an SRAM and an STT-MRAM so that a storage capacity is significantly improved compared to a case where a TLB is configured using an SRAM. Accordingly, the page hit rate of a TLB can be increased, thereby improving the throughput of a device. Furthermore, after a PTE is first written in the SRAM, a PTE having high frequency of use is selected and moved to the STT-MRAM. Accordingly, an increase in TLB update time which may occur due to the use of the STT-MRAM having a low write speed can be prevented. Furthermore, a read time and read energy consumption can be reduced.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: July 18, 2023
    Assignee: SK hynix Inc.
    Inventors: Won Woo Ro, Hyun Jae Oh
  • Patent number: 11650932
    Abstract: A non-volatile storage system includes a memory controller connected to an integrated memory assembly. The integrated memory assembly includes a memory die comprising non-volatile memory cells and a control die bonded to the memory die. The memory controller receives commands from a host, performs logical address to physical address translation (“address translation”) operations for the commands, and instructs the integrated memory assembly to perform one or more operations in support of the command. The control die also includes the ability to perform the address translation. When performing a command from the host, the memory controller can choose to perform the necessary address translation or instruct the control die to perform the address translation. When the control die performs the address translation, the resulting physical address is used by the control die to perform one or more operations in support of the command.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: May 16, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rakesh Balakrishnan, Eldhose Peter, Akhilesh Yadav, Ramanathan Muthiah, Vimal Kumar Jain
  • Patent number: 11636045
    Abstract: Translating virtual addresses to second addresses by a memory controller local to one or more memory devices, wherein the memory controller is not local to a processor, a buffer for storing a plurality of Page Table Entries, or a Page Walk Cache for storing a plurality of page directory entries, the method including by the memory controller: receiving a page directory base and a plurality of memory offsets from the processor; reading a first level page directory entry using the page directory base and a first level memory offset; combining the second level offset and the first level page directory entry; reading a second level page directory entry using the first level page directory entry and the second level memory offset; sending to the processor the first level page directory entry or the second level page directory entry; and sending a page table entry to the processor.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: April 25, 2023
    Assignee: International Business Machines Corporation
    Inventors: Mohit Karve, Brian W. Thompto
  • Patent number: 11626972
    Abstract: Methods, system, and apparatus, including computer programs encoded on computer storage media for data processing are provided. One of the methods includes: establishing a logic contract of a blockchain and one or more data contracts corresponding to the logic contract; deploying the logic contract and the one or more data contracts in the blockchain; storing data of a target block in the blockchain into the one or more data contracts; computing a hash value of each of the one or more data contracts; and determining a hash value of the target block in the blockchain based on the hash value of each of the one or more data contracts.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: April 11, 2023
    Assignee: ADVANCED NEW TECHNOLOGIES CO., LTD.
    Inventors: Haizhen Zhuo, Honglin Qiu
  • Patent number: 11620396
    Abstract: A kernel driver on an endpoint uses a process cache to provide a stream of events associated with processes on the endpoint to a data recorder. The process cache can usefully provide related information about processes such as a name, type or path for the process to the data recorder through the kernel driver. Where a tamper protection cache or similarly secured repository is available, this secure information may also be provided to the data recorder for use in threat detection, forensic analysis and so forth.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: April 4, 2023
    Assignee: Sophos Limited
    Inventor: Richard S. Teal
  • Patent number: 11620213
    Abstract: A controller configures a map table including a map entry associating different address schemes with each other. The controller is configured, for performing map table configuration, to find a target map entry among previous map entries in the map table, merge the current map entry into the target map entry to generate a merged map entry when the target map entry is found, and store the merged map entry in the map table. The target map entry and a current map entry include at least some information which is overlapped.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: April 4, 2023
    Assignee: SK hynix Inc.
    Inventors: Byoung Min Jin, Soong Sun Shin
  • Patent number: 11593018
    Abstract: A plurality of zone reset counters and a global reset counter are maintained. A zone reset counter represents a number of times a respective zone of a memory device has been reset. The global reset counter represents a measure of central tendency of the plurality of zone reset counters. A write command directed to a target zone of the memory device is received, and responsive to determining that a target portion of the target zone is not open, a value of the zone reset counter of het target zone is compared to the value of the global reset counter. If the value of the target zone reset counter equals or exceeds the value of the global reset counter, a portion from a free block list is allocated to the target zone. The allocated portion has a highest program erase count among the one or more portions in free block list.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: February 28, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Amit Bhardwaj
  • Patent number: 11561845
    Abstract: A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Samir Mittal, Gurpreet Anand, Anirban Ray, Parag R. Maharana
  • Patent number: 11526288
    Abstract: A memory system may include a memory device including a first memory block group and a second memory block group; and a memory controller configured to designate a first memory block of memory blocks included in the first memory block group as an open block and designate a second memory block of memory blocks included in the second memory block group as the open block, and perform a program operation on the first and second memory blocks designated as the open blocks. When the first memory block designated as the open block is changed to a closed block, the memory controller may determine whether to designate a third memory block among the memory blocks included in the first or the second memory block group as a new open block based on a number of times voltage abnormalities have occurred on a voltage supplied to the memory device.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: December 13, 2022
    Assignee: SK hynix Inc.
    Inventor: Gi Pyo Um
  • Patent number: 11500856
    Abstract: According to one or more embodiments, lookup, insertion, and deletion operations are allowed to continue during actions required for collision remediation. When relocation operations are used to resolve a collision, information encoded in header portions of the hash table entries that store the key-value pairs indicates when the associated key-value pairs are undergoing relocation. This information facilitates continued access to the RKVS during the relocation process by allowing other processes that access the RKVS to handle relocations without failure. Furthermore, when hash table expansion is needed in order to resolve a collision, a second, larger, hash table is allocated, and lookup operations continue on both the old hash table and the new hash table. One or more embodiments further prevent insertion, lookup, and deletion failures in the RKVS using flags, encoded in header information in hash table entries, that reflect the state of the respective key-value pairs in the store.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: November 15, 2022
    Assignee: Oracle International Corporation
    Inventors: Zahra Khatami, Avneesh Pant, Namrata Jampani
  • Patent number: 11481338
    Abstract: A hardware control system and a hardware control method are provided. The hardware control system is for controlling a function circuit, and includes a first transformation circuit, a second transformation circuit and an analysis circuit. The first transformation circuit transforms a command from an operating system to an intermediate address. The second transformation circuit transforms the intermediate address to a permission physical address according to an identifier of the operating system, wherein the permission physical address consists of a hardware physical address and a permission value. The analysis circuit analyzes the permission physical address to generate the hardware physical address and the permission value, and determines a control value corresponding to the hardware physical address according to the permission value. The control value is for permitting the operating system to control the function circuit.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: October 25, 2022
    Assignee: MEDIATEK INC.
    Inventor: Chien-Hsing Huang
  • Patent number: 11461296
    Abstract: An apparatus is disclosed. The apparatus may be implemented in a database node or a storage node and includes one or more processors and memory storing instructions for causing the processor to perform a number of operations. Responsive to a page write request, the apparatus determines an identifier corresponding to the requested page, sends component blocks corresponding to the page to a storage node for appending to an append-only storage log of the storage node, receives the physical location of the stored component blocks, and associates the physical storage location of the stored component blocks with the logical identifier corresponding to the page.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: October 4, 2022
    Assignee: Huawei Cloud Computing Technologies Co., Ltd.
    Inventors: Per-Ake Larson, Alexandre Depoutovitch
  • Patent number: 11392436
    Abstract: Aspects of a storage device including a memory and a controller are provided which allow for data associated with a deleted file to be recovered from the memory when the data is overwritten by a new file at the same logical address. To locate the data, the controller may identify a logical address associated with the data based on a directory entry associated with a FAT. The controller may determine a physical location of the data associated with the logical address based on one or more control entries in a L2P mapping table, such as a previous control entry in the table. The controller may also determine the physical location based on a hot count associated with the previous control entry. After the physical location is determined, the controller may associate a new logical address with the physical location of the data to recover the deleted file.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: July 19, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ankit Gupta, Narendhiran Chinnaanangur Ravimohan, Abhinand Amarnath
  • Patent number: 11372580
    Abstract: The present disclosure describes apparatuses and methods for automatically mapping virtual functions to storage media to enable single root input output virtualization. A storage media switch manages access to virtual functions that execute behind a storage media interface managed by the switch. The switch includes a host interface through which the switch receives host commands. The switch determines virtual function identifiers associated with the host commands and automatically selects the virtual functions of the storage media based on the virtual function identifiers. The switch executes the host commands over the storage media interface using the virtual functions, and after execution, responds via the host interface to each of the host commands. By automatically mapping virtual functions in this way, the switch automatically enables single root input output virtualization of storage media, including storage media that is without native support for input output virtualization.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: June 28, 2022
    Assignee: Marvell Asia PTE, Ltd.
    Inventors: Liping Guo, Yingdong Li, Scott Furey, Salil Suri
  • Patent number: 11334247
    Abstract: Disclosed herein are systems and method for de-duplicating blocks of data. In one aspect, an exemplary method comprises receiving a block of data at a de-duplication engine that comprises a first block node and a first page node, wherein the first block node stores a single block descriptor for at least two identical blocks previously received and wherein the first page node stores single instances of identical pages in the at least two identical blocks. The method comprises comparing the received block with the at least two identical blocks. In response to determining that the received block partially matches the at least two identical blocks, the method comprises storing a block descriptor of the received block in a second block node and storing at least one page that matches between the received block and the at least two identical blocks in a second page node of the de-duplication engine.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 17, 2022
    Assignee: Acronis International GmbH
    Inventors: Oleg Volkov, Andrey Zaitsev, Kirill Korotaev, Serguei Beloussov, Stanislav Protasov
  • Patent number: 11314412
    Abstract: According to one embodiment, a memory system includes a memory system includes a first nonvolatile memory and a controller. The controller controls the first nonvolatile memory. The second memory system includes a second nonvolatile memory. The controller manages information indicative of correspondences between private logical addresses and public logical addresses. The private logical addresses include first private logical addresses and second private logical addresses. Each of the first private logical addresses specifies a location in a first logical address space corresponding to the first nonvolatile memory. Each of the second private logical addresses specifies a location in a second logical address space corresponding to the second nonvolatile memory.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: April 26, 2022
    Assignee: Kioxia Corporation
    Inventor: Masahiro Takeshita
  • Patent number: 11314658
    Abstract: A data processing apparatus comprises processing circuitry to execute a plurality of processes. An ownership table comprises one or more entries each indicating, for a corresponding block of physical addresses, which of the processes is an owner process that has exclusive control of access to the corresponding block of physical addresses. A new process may be prevented from becoming an owner process until after successful completion of destructive overwriting. Ownership protection circuitry may detect a mismatch between an expected attribute, which is dependent on information in a page table entry, and an attribute specified in the ownership table. Each entry in the ownership table, for example, may indicate a level of encryption to be applied. Access control circuitry such as a memory management unit (MMU) may also determine whether an access request satisfies access permissions. The ownership table may also specify whether a higher privilege level process is allowed to access a block of physical addresses.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: April 26, 2022
    Assignee: Arm Limited
    Inventors: Jason Parker, Richard Roy Grisenthwaite, Andrew Christopher Rose
  • Patent number: 11282567
    Abstract: Systems and methods for read operations and management are disclosed. More specifically, this disclosure is directed to receiving a first read command directed to a first logical address and receiving, after the first read command, a second read command directed to a second logic address. The method also includes receiving, after the second read command, a third read command directed to a third logical address and determining that the first logical address and the third logical address correspond to a first physical address and a third physical address, respectively. The first physical address and the third physical address can be associated with a first word line of a memory component while the second logical address corresponds to a second physical address associated with a second word line of the memory component. The method includes executing the first read command and the third read command sequentially.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Tomoko Ogura Iwasaki, Tracy D. Evans, Avani F. Trivedi, Aparna U. Limaye, Jianmin Huang
  • Patent number: 11249918
    Abstract: A memory access system may include a first memory address translator, a second memory address translator and a mapping entry invalidator. The first memory address translator translates a first virtual address in a first protocol of a memory access request to a second virtual address in a second protocol and tracks memory access request completions. The second memory address translator is to translate the second virtual address to a physical address of a memory. The mapping entry invalidator requests invalidation of a first mapping entry of the first mapping address translator requests invalidation of a second mapping entry of the second memory address translator corresponding to the first mapping entry following invalidation of the first mapping entry and based upon the tracked memory access request completions.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: February 15, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Shawn K. Walker, Christopher Shawn Kroeger, Derek A. Sherlock
  • Patent number: 11249922
    Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: allocate a named portion of the non-volatile storage device; generate, according to a first block size, first block-wise mapping data; translate, using the first block-wise mapping data, logical addresses defined in the named portion to logical addresses defined for the entire non-volatile storage media, which can then be further translated to physical addresses in a same way for all named portions; determine a second block size; generate, according to the second block size, second block-wise mapping data; translate, using the second block-wise mapping data, the logical addresses defined in the named portion to the logical addresses defined for the entire non-volatile storage media.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: February 15, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Alex Frolikov
  • Patent number: 11249666
    Abstract: A storage control apparatus includes a processor that creates a snapshot of a first volume of a storage device. The processor deduplicates unupdated data among data of the first volume. The processor compresses the deduplicated data to create compressed data. The processor stores the compressed data in a second volume of the storage device. The processor selects, when the snapshot is created for two or more generations, the second volume corresponding to each of a plurality of snapshots of generations earlier than a predetermined generation. The processor detects unpopular data from the compressed data existing in the selected second volume based on a reference count. The processor collects and decompresses detected pieces of the unpopular data when the number of the detected pieces of the unpopular data is equal to or more than a predetermined threshold value. The processor combines and recompresses the decompressed data to create recompressed data.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: February 15, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Hideyuki Kanai
  • Patent number: 11249917
    Abstract: An operating method for a data storage device includes providing a nonvolatile memory device including a plurality of pages; segmenting an address map which maps a logical address provided from a host device and a physical address of the nonvolatile memory device, by a plurality of address map segments according to a segment size that is set depending on a quality of service time allowed to process a request of the host device and an unprocessed workload; and flushing at least one of the address map segments in the nonvolatile memory device after processing the unprocessed workload.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: February 15, 2022
    Assignee: SK hynix Inc.
    Inventors: Min Hwan Moon, Duck Hoi Koo, Soong Sun Shin, Ji Hoon Lee
  • Patent number: 11250001
    Abstract: Embodiments of the invention relate to processing data records, and for a multi-phase partitioned data reduction. The first phase relates to processing data records and partitioning the records into a first partition of records having a common characteristic and a second partition of records that are not members of the first partition. The data records in each partition are subject to intra-partition data reduction responsive to a resource constraint. The data records in each partition are also subject to an inter-partition data reduction, also referred to as an aggregation to reduce a footprint for storing the records. Partitions and/or individual records are logically aggregated and a data reduction operation for the logical aggregation of records takes place in response to available resources.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: February 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ronald J. Barber, Vincent Kulandaisamy, Sam S. Lightstone, Guy M. Lohman, Ippokratis Pandis, Vijayshankar Raman, Gregory R. Stager, Wayne J. Young, Liping Zhang
  • Patent number: 11226737
    Abstract: Disclosed herein are systems and method for de-duplicating blocks of data. In one aspect, an exemplary method comprises for each previously de-duplicated block of data of a de-duplication engine, storing de-duplicated pages references by hashes and a block descriptor. The method comprises receiving, at the de-duplication engine, a new block of data for de-duplication assessment and determining a similarity of the received block to the previously de-duplicated blocks. When the received block is determined as being similar to the previously de-duplicated blocks, the method comprises storing the received block without duplication in the de-duplication engine, including pages of the block referenced by the hashes and the block descriptor.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: January 18, 2022
    Assignee: Acronis International GmbH
    Inventors: Oleg Volkov, Andrey Zaitsev, Kirill Korotaev, Serguei Beloussov, Stanislav Protasov
  • Patent number: 11221914
    Abstract: According to one embodiment, a memory system copies content of a first logical-to-physical address translation table corresponding to a first region of a nonvolatile memory to a second logical-to-physical address translation table corresponding to a second region of the nonvolatile memory. When receiving a read request specifying a logical address in the second region, the memory system reads a part of the first data from the first region based on the second logical-to-physical address translation table. The memory system detects a block which satisfies a refresh condition from a first group of blocks allocated to the first region, corrects an error of data of the detected block and writes the corrected data back to the detected block.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: January 11, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11221949
    Abstract: Methods, systems, and devices for multi-state purgatory for garbage collection are described. A processing device can determine a valid data count for a block of data of a memory sub-system. In some case, the valid data count can indicate that the block of data contains invalid data. The processing device can assign the block of data to a first purgatory state based on the valid data count and verify that one or more read operations for the block of data in the first purgatory state are complete based on the first purgatory state. In some examples, the processing device can assign the block of data to a second purgatory state based on the verifying.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: January 11, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Antonio David Bianco
  • Patent number: 11216381
    Abstract: A data storage device includes a memory device and a memory controller. The memory controller selects a predetermined memory device to receive data and accordingly records multiple logical addresses in a first mapping table. The first mapping table records which logical page the data stored in each physical page of the predetermined memory block is directed to. When the predetermined memory block is full, the memory controller edits a second mapping table and a third mapping table according to the first mapping table. The second mapping table corresponds to multiple logical pages and records which memory block and which physical page is the data of each logical page stored in. The third mapping table corresponds to the physical pages of the predetermined memory block and indicates whether each physical page is a valid page or an invalid page.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: January 4, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Kuan-Yu Ke
  • Patent number: 11218367
    Abstract: Provided herein are devices, systems, methods and various means, including those related to providing a community internet drive that may utilize a centrally-managed hub as well as storage devices distributed among various networked machines. In some embodiments, the community internet drive can also include features to enable its users to promote and utilize the user's trusted personal relationships while also enabling an open platform for peer-to-peer and/or other types of sharing schemes.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: January 4, 2022
    Assignee: PLANETARY DATA LLC
    Inventor: Robert Alan McEntee
  • Patent number: 11199997
    Abstract: In one non-limiting embodiment, a method is disclosed for performing a storage device operation on a die is provide having steps of choosing a storage device operation to perform, estimating which die is related to the storage device operation chosen to be performed and performing the storage device operation at the die based on the estimating.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: December 14, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Amir Shaharabany, Hadas Oshinsky
  • Patent number: 11200183
    Abstract: Implementations of the disclosure provide processing device comprising: an interrupt managing circuit to receive an interrupt message directed to an application container from an assignable interface (AI) of an input/output (I/O) device. The interrupt message comprises an address space identifier (ASID), an interrupt handle and a flag to distinguish the interrupt message from a direct memory access (DMA) message. Responsive to receiving the interrupt message, a data structure associated with the interrupt managing circuit is identified. An interrupt entry from the data structure is selected based on the interrupt handle. It is determined that the ASID associated with the interrupt message matches an ASID in the interrupt entry. Thereupon, an interrupt in the interrupt entry is forwarded to the application container.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 14, 2021
    Assignee: Intel Corporation
    Inventors: Sanjay Kumar, Rajesh M. Sankaran, Philip R. Lantz, Utkarsh Y. Kakaiya, Kun Tian
  • Patent number: RE49090
    Abstract: Systems and methods for scanning signatures in a string field. In one implementation, the invention provides a method for signature scanning. The method includes receiving a particular string field, scanning the particular string field for a plurality of signatures using a larger scan step size, scanning the particular string field for the remaining signatures that are shorter than what can be scanned by the larger scan step size separately either using the same scanning method but a smaller scan step size or using a different scan method and the same or a smaller scan step size, and outputting any identified signatures in the particular string field.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: May 31, 2022
    Inventor: Qiang Wang