Directory Tables (e.g., Dlat, Tlb) Patents (Class 711/207)
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Patent number: 8180953Abstract: A data accessing method for accessing data in a plurality of physical page addresses of a plurality of physical blocks in a flash memory chip is provided. The data accessing method includes proving a plurality of logical page addresses for a host system, creating a logical page to physical page mapping table and a physical page to logical page mapping table to record the mapping between the logical page addresses and the physical page addresses. The data accessing method also includes writing data into the physical page addresses, and updating the logical page to physical page mapping table and the physical page to logical page mapping table. The data accessing method further includes determining whether the physical page addresses are valid or invalid based on the logical page to physical page mapping table and the physical page to logical page mapping table.Type: GrantFiled: March 4, 2009Date of Patent: May 15, 2012Assignee: Phison Electronics Corp.Inventor: Chien-Hua Chu
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Publication number: 20120117301Abstract: Various methods and apparatus are described for communicating transactions between one or more initiator IP cores and one or more target IP cores coupled to an interconnect. A centralized Memory Management logic Unit (MMU) is located in the interconnect for virtualization and sharing of integrated circuit resources including target cores between the one or more initiator IP cores. A master translation look aside buffer (TLB) stores virtualization and sharing information in the entries of the master TLB. A set of two or more translation look aside buffers (TLBs) locally store virtualization and sharing information replicated from the master TLB. Logic in the MMU or other software updates the virtualization and sharing information replicated from the master TLB in the entries of one or more of the set of local TLBs.Type: ApplicationFiled: November 3, 2011Publication date: May 10, 2012Applicant: SONICS, INC.Inventor: Drew E. Wingard
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Publication number: 20120117356Abstract: An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.Type: ApplicationFiled: January 13, 2012Publication date: May 10, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy J. Slegel, Lisa C. Heller, Erwin F. Pfeffer, Kenneth E. Plambeck
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Patent number: 8176295Abstract: A method for making memory more reliable involves accessing data stored in a removable storage device by translating a logical memory address provided by a host digital device to a physical memory address in the device. A logical memory address is received from the host digital device. The logical memory address corresponds to a location of data stored on the removable storage device. A physical memory address corresponding to the local address is determined by accessing a lookup table corresponding to the logical zone.Type: GrantFiled: April 20, 2009Date of Patent: May 8, 2012Assignee: Imation Corp.Inventor: Arunprasad Ramiya Mothilal
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Patent number: 8171255Abstract: A system, method and computer program product for virtualizing a processor include a virtualization system running on a computer system and controlling memory paging through hardware support for maintaining real paging structures. A Virtual Machine (VM) is running guest code and has at least one set of guest paging structures that correspond to guest physical pages in guest virtualized linear address space. At least some of the guest paging structures are mapped to the real paging structures. A cache of connection structures represents cached paths to the real paging structures. The mapped paging tables are protected using RW-bit. A paging cache is validated according to TLB resets. Non-active paging tree tables can be also protected at the time when they are activated. Tracking of access (A) bits and of dirty (D) bits is implemented along with synchronization of A and D bits in guest physical pages.Type: GrantFiled: April 20, 2010Date of Patent: May 1, 2012Assignee: Parallels IP Holdings GmbHInventors: Alexey B. Koryakin, Alexander G. Tormasov, Nikolay N. Dobrovolskiy, Serguei M. Beloussov, Andrey A. Omelyanchuk
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Patent number: 8171200Abstract: A method includes indexing a translation table stored in memory with a first index of a virtual address corresponding to a first memory region size by querying the translation table at first locations associated with the first index. Indexing the translation table with a second index of the virtual address corresponding to a second memory region size by querying the translation table at second locations associated with the second index. The translation table includes translations for mapping address tags of the virtual address to physical addresses. The first index is different than the second index, and the first memory region size is different than the second memory region size.Type: GrantFiled: November 9, 2010Date of Patent: May 1, 2012Assignee: Marvell International Ltd.Inventors: Dennis O'Connor, Stephen J. Strazdus
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Publication number: 20120102296Abstract: In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may reserve at least one of the sections for access by a subset of the request sources that use the TLB. For requests from the subset, the reserved section may be used and a location in the reserved section may be allocated to store a translation for a request from the subset that misses in the TLB. For requests for other request sources, the non-reserved section or sections may be used. In one embodiment, each way of the reserved section may be assigned to a different one of the request sources in the subset.Type: ApplicationFiled: December 28, 2011Publication date: April 26, 2012Inventor: Joseph A. Petolino, JR.
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Patent number: 8166276Abstract: In an embodiment, a first instruction is defined that comprises at least a first operand from which the execution core is configured to determine a virtual address and a second operand that specifies one or more translation attributes that exist in a page table entry that defines a translation for the virtual address. A processor executing the instruction translates the virtual address, verifies whether or not the translation attributes in the page table entry match the specified translation attributes, faults the first instruction responsive to failing to locate a translation for the virtual address, and responsive to locating a translation for the virtual address in the page table entry but with the translation attributes in the entry failing to match the specified translation attributes.Type: GrantFiled: February 27, 2009Date of Patent: April 24, 2012Assignee: Advanced Micro Devices, Inc.Inventor: Benjamin C. Serebrin
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Patent number: 8161246Abstract: A microprocessor includes a cache memory, a load unit, and a prefetch unit, coupled to the load unit. The load unit is configured to receive a load request that includes an indicator that the load request is loading a page table entry. The prefetch unit is configured to receive from the load unit a physical address of a first cache line that includes the page table entry specified by the load request. The prefetch unit is further configured to responsively generate a request to prefetch into the cache memory a second cache line. The second cache line is the next physically sequential cache line to the first cache line. In an alternate embodiment, the second cache line is the previous physically sequential cache line to the first cache line rather than the next physically sequential cache line to the first cache line.Type: GrantFiled: October 23, 2009Date of Patent: April 17, 2012Assignee: VIA Technologies, Inc.Inventors: Rodney E. Hooker, Colin Eddy
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Patent number: 8161243Abstract: Methods and apparatus relating to improving address translation caching and/or input/output (I/O) cache performance in virtualized environments are described. In one embodiment, a hint provided by an endpoint device may be utilized to update information stored in an I/O cache. Such information may be utilized for implementation of a more efficient replacement policy in an embodiment. Other embodiments are also disclosed.Type: GrantFiled: September 28, 2007Date of Patent: April 17, 2012Assignee: Intel CorporationInventors: Mahesh Wagh, Jasmin Ajanovic
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Publication number: 20120089810Abstract: The invention relates to a method and apparatus for formatting and preselecting trace data, and includes a trace message generator, an address checker, and a memory connected to the trace message generator and address checker. The trace message generator is configured to receive an address and associated data and generate a trace message with the associated data for the received address. The address checker is configured to receive the address, check the received address with the aid of the memory, and generate an output signal that indicates whether or not the trace message generated for the address is intended to be stored. The memory is configured to receive the trace message generated by the trace message generator, receive the output signal generated by the address checker, and store the received trace message if the output signal indicates that the trace message is intended to be stored.Type: ApplicationFiled: October 5, 2011Publication date: April 12, 2012Applicant: Infineon Technologies AGInventors: Albrecht Mayer, Harry Siebert
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Publication number: 20120089811Abstract: An address conversion apparatus includes a TLB, and an address conversion control section configured to count a consecutive address number indicating the number of consecutive addresses from a pair of a logical address and a physical address stored in the TLB with reference to an address conversion table, store the consecutive address number in association with the pair of the logical address and the physical address, determine whether a conversion target address is included in a range of the consecutive address number from the logical address stored in the TLB or not, and add, if the conversion target address is included in the range, a difference between the logical address and the conversion target address to the physical address which forms a pair with the logical address to calculate a converted physical address.Type: ApplicationFiled: December 19, 2011Publication date: April 12, 2012Applicant: Panasonic CorporationInventor: Takatsugu SAWAI
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Patent number: 8156309Abstract: Multiple pipelined Translation Look-aside Buffer (TLB) units are configured to compare a translation address with associated TLB entries. The TLB units operated in serial order comparing the translation address with associated TLB entries until an identified one of the TLB units produces a hit. The TLB units following the TLB unit producing the hit might be disabled.Type: GrantFiled: October 18, 2007Date of Patent: April 10, 2012Assignee: Cisco Technology, Inc.Inventor: Donald E. Steiss
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Patent number: 8156305Abstract: Described herein are method and apparatus for using an LLRRM device as a storage device in a storage system. At least three levels of data structures may be used to remap storage system addresses to LLRRM addresses for read requests, whereby a first-level data structure is used to locate a second-level data structure corresponding to the storage system address, which is used to locate a third-level data structure corresponding to the storage system address. An LLRRM address may comprise a segment number determined from the second-level data structure and a page number determined from the third-level data structure. Update logs may be produced and stored for each new remapping caused by a write request. An update log may specify a change to be made to a particular data structure. The stored update logs may be performed on the data structures upon the occurrence of a predetermined event.Type: GrantFiled: October 1, 2008Date of Patent: April 10, 2012Assignee: NetApp, Inc.Inventors: Garth R. Goodson, Rahul N. Iyer
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Publication number: 20120084488Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.Type: ApplicationFiled: December 6, 2011Publication date: April 5, 2012Applicant: International Business Machines CorporationInventors: Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer
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Publication number: 20120079164Abstract: A processor includes a first translation look-aside buffer to support a guest operating mode. A second translation look-aside buffer supports a root operating mode. Hardware resources support the guest operating mode as controlled by guest mode control registers defining guest context. The guest context is used by the hardware resources to access the first translation look-aside buffer to translate a guest virtual address to a guest physical address. The hardware resources access the second translation look-aside buffer to translate the guest physical address to a physical address.Type: ApplicationFiled: September 27, 2010Publication date: March 29, 2012Inventor: JAMES ROBERT HOWARD HAKEWILL
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Publication number: 20120079232Abstract: An apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries. The micro-page table engine allows the TLB to be an agent that determines whether data in a two-level memory hierarchy is in a hot region of memory or in a cold region of memory.Type: ApplicationFiled: September 24, 2010Publication date: March 29, 2012Inventors: Glenn Hinton, Madhavan Parthasarathy, Rajesh Parthasarathy, Muthukumar Swaminathan, Raj Ramanujan, David Zimmerman, Larry O. Smith, Adrian C. Moga, Scott J. Cape, Wayne A. Downer, Robert S. Chappell
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Patent number: 8145876Abstract: A data processing device employs a first translation look-aside buffer (TLB) to translate virtual addresses to physical addresses. If a virtual address to be translated is not located in the first TLB, the physical address is requested from a set of page tables. When the data processing device is in a hypervisor mode, a second TLB is accessed in response to the request to access the page tables. If the virtual address is located in the second TLB, the hypervisor page tables are bypassed and the second TLB provides a physical address or information to access another table in the set of page tables. By bypassing the hypervisor page tables, the time to translate an address in the hypervisor mode is reduced, thereby improving the efficiency of the data processing device.Type: GrantFiled: August 6, 2007Date of Patent: March 27, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Michael Edward Tuuk, Michael Clark
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Publication number: 20120072697Abstract: A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.Type: ApplicationFiled: March 22, 2011Publication date: March 22, 2012Inventors: Guillermo Rozas, Alexander Klaiber, H. Peter Anvin, David Dunn
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Publication number: 20120072698Abstract: According to one embodiment, a memory management device includes a history management unit, an address translation table, an address management unit, and a data management unit. The history management unit manages an access history for data stored in a nonvolatile semiconductor memory. The address translation table includes a translation table of a logical address and a physical address corresponding to the data. The address management unit specifies, based on the access history, second data to be accessed after access to first data being stored in the nonvolatile semiconductor memory, and registers a second physical address corresponding to the second data in the address translation table in association with a first logical address corresponding to the first data. The data management unit reads out the second data from the nonvolatile semiconductor memory to a buffer.Type: ApplicationFiled: September 16, 2011Publication date: March 22, 2012Inventors: Tsutomu UNESAKI, Yoshiyuki ENDO
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Patent number: 8140823Abstract: Systems and methods including a multithreaded processor with a lock indicator are disclosed. In an embodiment, a system includes means for indicating a lock status of a shared resource in a multithreaded processor. The system includes means for automatically locking the shared resource before processing exception handling instructions associated with the shared resource. The system further includes means for unlocking the shared resource.Type: GrantFiled: December 3, 2007Date of Patent: March 20, 2012Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, Erich James Plondke, Suresh Venkumahanti
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Patent number: 8140820Abstract: A data processing apparatus has address translation circuitry which is responsive to an access request specifying a virtual address, to perform a multi-stage address translation process to produce, via at least one intermediate address, a physical address in memory corresponding to the virtual address. The address translation circuitry references a storage unit, with each entry of the storage unit storing address translation information for one or more virtual addresses. Each entry has a field indicating whether the address translation information is consolidated address translation information or partial address translation information. If when processing an access request, it is determined that the relevant entry in the storage unit provides consolidated address translation information, the address translation circuitry produces a physical address directly from the consolidated address translation information.Type: GrantFiled: May 21, 2008Date of Patent: March 20, 2012Assignee: ARM LimitedInventors: David Hennah Mansell, Richard Roy Grisenthwaite
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Patent number: 8140822Abstract: Maintaining data integrity for a logical partition by enabling nonintrusive switching of page tables used during a migration of the logical partition from a source computer system to a target computer system. A first page table stores a plurality of page entries made within a logically partitioned environment. A second page table stores one or more page entries generated during the migration. After migration, the processor page table pointer is switched to point to the first page table. A page entry in the second page table corresponding to a page entry made to the first page table by the logical partition may be invalidated in response to a page table hypervisor call made by the logical partition. In parallel, a plurality of entries generated during the migration of the logical partition in the second page table may be read through and invalidated.Type: GrantFiled: April 16, 2007Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Stuart Zachary Jacobs, David Anthony Larson, Naresh Nayar, Jonathan Ross Van Niewaal, Kenneth Charles Vossen
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Publication number: 20120066474Abstract: A coprocessor performs operations on behalf of processes executing in processors coupled thereto, and accesses data operands in memory using real addresses. A process executing in a processor generates an effective address for a coprocessor request, invokes the processor's address translation mechanisms to generate a corresponding real address, and passes this real address is the coprocessor. Preferably, the real address references a block of additional real addresses, each for a respective data operand. The coprocessor uses the real address to access the data operands to perform the operation. An address context detection mechanism detects the occurrence of certain events which could alter the context of real addresses used by the coprocessor or the real addresses themselves.Type: ApplicationFiled: September 13, 2010Publication date: March 15, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Mark R. Funk
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Publication number: 20120066475Abstract: A translation lookaside buffer (TLB) is disclosed formed using RAM and synthesisable logic circuits. The TLB provides logic within the synthesisable logic for pairing down a number of memory locations that must be searched to find a translation to a physical address from a received virtual address. The logic provides a hashing circuit for hashing the received virtual address and uses the hashed virtual address to index the RAM to locate a line within the RAM that provides the translation.Type: ApplicationFiled: November 17, 2011Publication date: March 15, 2012Applicant: NYTELL SOFTWARE LLCInventors: Paulus Stravers, Jan-Willem van de Waerdt
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Patent number: 8135914Abstract: Embodiments of the invention provide techniques for managing cache metadata providing a mapping between addresses on a storage medium (e.g., disk storage) and corresponding addresses on a cache device at data items are stored. In some embodiments, cache metadata may be stored in a hierarchical data structure comprising a plurality of hierarchy levels. When a reboot of the computer is initiated, only a subset of the plurality of hierarchy levels may be loaded to memory, thereby expediting the process of restoring the cache metadata and thus startup operations. Startup may be further expedited by using cache metadata to perform operations associated with reboot. Thereafter, as requests to read data items on the storage medium are processed using cache metadata to identify addresses at which the data items are stored in cache, the identified addresses may be stored in memory.Type: GrantFiled: August 30, 2011Date of Patent: March 13, 2012Assignee: Microsoft CorporationInventors: Mehmet Iyigun, Yevgeniy M. Bak, Michael Fortin, David Fields, Cenk Ergan, Alexander Kirshenbaum
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Publication number: 20120054466Abstract: A computer implemented method optimizes memory page sizes during runtime. A process is identified from a policy file. The policy file contains at least one policy based threshold. A resource usage profiler monitors the process during runtime. The resource usage profiler determines whether the process exceeds the set of stated desired policies from the at least one policy based threshold. If the process exceeds the set of stated desired policies from the set of policy based thresholds, a performance projection for the process is executed to determine whether the process would experience a performance benefit from a different page size. Responsive to determining that the process would experience the performance benefit from the different page size, the page size for the process is changed.Type: ApplicationFiled: August 27, 2010Publication date: March 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Saravanan Devendran, Kiran Grover
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Publication number: 20120054425Abstract: In one embodiment, a processor includes an address generation unit having a memory context logic to determine whether a memory context identifier associated with an address of a memory access request corresponds to an agent memory context identifier for the processor, and to handle the memory address request based on the determination. Other embodiments are described and claimed.Type: ApplicationFiled: August 31, 2010Publication date: March 1, 2012Inventor: Ramon Matas
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Patent number: 8127072Abstract: The invention provides a method for accessing a flash memory. In one embodiment, the flash memory comprises a plurality of memory units, each of the memory units has a physical address, and an address link table records a mapping relationship between a plurality of logical addresses and a plurality of physical addresses. First, first data to be written to a first logical address is received from a host. Whether the first data is predetermined data is the determined. Whether the first logical address is mapped to a null physical address is then determined according to the address link table. When the first data is the predetermined data and the first logical address is not mapped to the null physical address according to the address link table, the address link table is modified to map the first logical address to the null physical address.Type: GrantFiled: July 4, 2009Date of Patent: February 28, 2012Assignee: Silicon MotionInventor: Bo Chen
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Patent number: 8117420Abstract: A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a read position and can store a bit indicating a valid state of a transaction request in a write entry. The control module can receive an invalidation request and modify the bit to indicate an invalid state for the transaction request and discard the transaction request when the transaction request is in the read position.Type: GrantFiled: August 7, 2008Date of Patent: February 14, 2012Assignee: QUALCOMM IncorporatedInventors: Jian Shen, Robert Allan Lester
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Patent number: 8117422Abstract: The core of this invention is the application of a fast comparison circuit to the problem of address translation. Traditional implementations generate the virtual address and the physical address in series. This invention generates the physical address and virtual address simultaneously. A bitwise operation on the base address, the offset address and each stored virtual address determines whether the base address and offset address sum equals the virtual address without requiring a carry propagate. Circular addressing is implemented in the match determination by masking bits corresponding to the circular address limit.Type: GrantFiled: February 5, 2009Date of Patent: February 14, 2012Assignee: Texas Instruments IncorporatedInventors: Timothy D. Anderson, Kai Chirca
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Publication number: 20120030445Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.Type: ApplicationFiled: August 1, 2011Publication date: February 2, 2012Applicant: NETLOGIC MICROSYSTEMS, INC.Inventors: David T. Hass, Basab Mukherjee
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Patent number: 8108650Abstract: In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may reserve at least one of the sections for access by a subset of the request sources that use the TLB. For requests from the subset, the reserved section may be used and a location in the reserved section may be allocated to store a translation for a request from the subset that misses in the TLB. For requests for other request sources, the non-reserved section or sections may be used. In one embodiment, each way of the reserved section may be assigned to a different one of the request sources in the subset.Type: GrantFiled: May 29, 2009Date of Patent: January 31, 2012Assignee: Apple Inc.Inventor: Joseph A. Petolino, Jr.
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Patent number: 8103850Abstract: A system for translating software in a first format into a second format includes a memory containing the software in the first format and an emulator coupled to the memory configured to translate the software from the first format to the second format. The system also includes a host engine coupled to the emulator and configured to perform instructions in the second format. The emulator is configured to determine whether a store command in the first format stores information to a memory page that includes instructions and to convert the store instruction to a special store instruction in the event that the target of the store instruction does not contain an instruction.Type: GrantFiled: May 5, 2009Date of Patent: January 24, 2012Assignee: International Business Machines CorporationInventors: Ravi Nair, Kevin A. Stoodley
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Patent number: 8099581Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.Type: GrantFiled: June 30, 2009Date of Patent: January 17, 2012Assignee: Intel CorporationInventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Dion Rodgers, Rajesh Madukkaraumukumana, Camron Rust, Sebastian Schoenberg
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Publication number: 20120008674Abstract: A multithread processor including: an execution unit including a physical processor; and a translation lookaside buffer (TLB) which converts, to a physical address, a logical address output from the execution unit, and logical processors are implemented on the physical processor, a first logical processor that is a part of the logical processors constitutes a first subsystem having a first virtual space, a second logical processor that is a part of the logical processors and different from the first logical processor constitutes a second subsystem having a second virtual space, each of the first and the second subsystems has processes to be assigned to the logical processors, and the logical address includes: a first TLB access virtual identifier for identifying one of the first and the second subsystems; and a process identifier for identifying a corresponding one of the processes in each of the first and the second subsystems.Type: ApplicationFiled: August 15, 2011Publication date: January 12, 2012Applicant: PANASONIC CORPORATIONInventors: Takao YAMAMOTO, Shinji OZAKI, Masahide KAKEDA, Masaitsu NAKAJIMA
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Publication number: 20120011342Abstract: A system and method to manage a translation lookaside buffer (TLB) is disclosed. In a particular embodiment, a method of managing a first TLB includes in response to starting execution of a memory instruction, setting a first field associated with an entry of the first TLB to indicate use of the entry. The method also includes setting a second field to indicate that the entry in the first TLB matches a corresponding entry in a second TLB.Type: ApplicationFiled: July 6, 2010Publication date: January 12, 2012Applicant: QUALCOMM INCORPORATEDInventors: Ajay Anant Ingle, Erich James Plondke, Muhammad T. Rab
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Patent number: 8094158Abstract: Systems and methods for using multiple versions of programmable constants within a multi-threaded processor allow a programmable constant to be changed before a program using the constants has completed execution. Processing performance may be improved since programs using different values for a programmable constant may execute simultaneously. The programmable constants are stored in a constant buffer and an entry of a constant buffer table is bound to the constant buffer. When a programmable constant is changed it is copied to an entry in a page pool and address translation for the page pool is updated to correspond to the old version (copy) of the programmable constant. An advantage is that the constant buffer stores the newest version of the programmable constant.Type: GrantFiled: January 31, 2006Date of Patent: January 10, 2012Assignee: NVIDIA CorporationInventors: Roger L. Allen, Cass W. Everitt, Henry P. Moreton, Thomas H. Kong
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Patent number: 8095773Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.Type: GrantFiled: February 26, 2008Date of Patent: January 10, 2012Assignee: International Business Machines CorporationInventors: Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer
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Publication number: 20120005453Abstract: An object is to enable efficient shredding of recording media in association with migration. An information processing device (a server device 3) receives a data input/output request in a unit of a file transmitted from a client device 2, and performs writing and reading of data to and from a storage system 10 having a recording medium (hard disk drive 171) in which a file entity specified in the received data input/output request is stored in units of data blocks. The information processing device is communicatively coupled to a different storage device which is a migration destination of data. In the case where after the migration of certain data, different data is written in a data block of the certain data in an overlapped manner, the data block is not shredded if the data block is already shredded related to either of the overlapped certain and the different data after the migration.Type: ApplicationFiled: April 9, 2010Publication date: January 5, 2012Applicant: HITACHI, LTD.Inventor: Nobuyuki Saika
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Publication number: 20120005454Abstract: Memory address translation buffering circuitry is provided comprising a primary storage bank and a secondary storage bank. Storage bank accessing circuitry is provided to perform a parallel lookup of the primary storage bank and the secondary storage bank for virtual to physical address translation entries. Buffering management circuitry is configured to transfer an address translation entry between the primary storage bank and the secondary storage bank dependent upon an occupancy level of at least one of the primary storage bank and secondary storage bank.Type: ApplicationFiled: July 1, 2010Publication date: January 5, 2012Applicant: ARM LimitedInventor: Alex James Waugh
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Publication number: 20110320762Abstract: In one embodiment, the present invention includes a processor comprising a page tracker buffer (PTB), the PTB including a plurality of entries to store an address to a cache page and to store a signature to track an access to each cache line of the cache page, and a PTB handler, the PTB handler to load entries into the PTB and to update the signature. Other embodiments are also described and claimed.Type: ApplicationFiled: June 23, 2010Publication date: December 29, 2011Inventors: Livio B. Soares, Naveen Cherukuri, Akhilesh Kumar, Mani Azimi
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Publication number: 20110320644Abstract: Address spaces are resized concurrent to accessing those address spaces. The size of an address space can be increased or decreased concurrent to performing read or write operations on the address space. Further, cache entries associated with an address space being decreased in size are purged.Type: ApplicationFiled: June 23, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Craddock, Thomas A. Gregg, Dan F. Greiner, Donald W. Schmidt
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Patent number: 8086438Abstract: A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the program simulation. In another embodiment, before storing new information in the table, another table may be consulted to determine if the location to which the new information is to be stored is protected. If the table location is protected, the new information is not stored in the table. Rather, the new information is simply passed on to the simulator.Type: GrantFiled: December 3, 2002Date of Patent: December 27, 2011Assignee: Synopsys, Inc.Inventors: Achim Nohl, Gunnar Braun, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Myer
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Patent number: 8082416Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.Type: GrantFiled: August 18, 2010Date of Patent: December 20, 2011Assignee: NetLogic Microsystems, Inc.Inventors: Gaurav Singh, Dave Hass, Daniel Chen
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Publication number: 20110307656Abstract: Lookup techniques are described, which can achieve improvements in energy efficiency, speed, and cost, of IP address lookup, for example, in devices and systems employing ternary content addressable memory (TCAM). The disclosed subject matter describes dividing a route table into several sub-tries with disjoint range boundaries. In addition, the disclosed subject matter describes storing sub-tries of a route table between a TCAM and a faster and less costly memory. The disclosed details enable various refinements and modifications according to system design and tradeoff considerations.Type: ApplicationFiled: June 14, 2011Publication date: December 15, 2011Applicant: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Mounir Hamdi, Dong Lin
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Publication number: 20110307665Abstract: Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory.Type: ApplicationFiled: June 9, 2010Publication date: December 15, 2011Inventors: John Rudelic, August Camber, Mostafa Naguib Abdulla
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Patent number: 8078806Abstract: A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch priority. The microprocessor also includes a load/store unit that generates load/store requests to transfer data between the system memory and the microprocessor. The microprocessor also includes a stream prefetch unit that generates a plurality of prefetch requests to prefetch the data stream from the system memory into the microprocessor. The prefetch requests specify the stream prefetch priority. The microprocessor also includes a bus interface unit (BIU) that generates transaction requests on the bus to transfer data between the system memory and the microprocessor in response to the load/store requests and the prefetch requests. The BIU prioritizes the bus transaction requests for the prefetch requests relative to the bus transaction requests for the load/store requests based on the stream prefetch priority.Type: GrantFiled: October 25, 2010Date of Patent: December 13, 2011Assignee: MIPS Technologies, Inc.Inventor: Keith E. Diefendorff
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Patent number: 8078792Abstract: In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specify the alternate address space for a data access, permitting the minivisor/VMM to read guest memory state via the alternate address space. In another embodiment, a processor may implement a page table base address register dedicated for the minivisor's use. In still another embodiment, the minivisor may be implemented as a specified entry point in the VMM address space.Type: GrantFiled: November 18, 2008Date of Patent: December 13, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Benjamin C. Serebrin, Michael J. Haertel
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Patent number: 8074047Abstract: A system and method for effectively increasing the amount of data that can be stored in the main memory of a computer, particularly, by a hardware enhancement of a memory controller apparatus that detects duplicate memory contents and eliminates duplicate memory contents wherein the duplication and elimination are performed by hardware without imposing any penalty on the overall performance of the system.Type: GrantFiled: May 16, 2008Date of Patent: December 6, 2011Assignee: International Business Machines CorporationInventors: Bulent Abali, Mohammad Banikazemi