Abstract: A method for translating instructions for a processor. The method includes accessing a guest instruction and performing a first level translation of the guest instruction using a first level conversion table. The method further includes outputting a resulting native instruction when the first level translation proceeds to completion. A second level translation of the guest instruction is performed using a second level conversion table when the first level translation does not proceed to completion, wherein the second level translation further processes the guest instruction based upon a partial translation from the first level conversion table. The resulting native instruction is output when the second level translation proceeds to completion.

Abstract: Embodiments of techniques and systems for protected access to virtual memory are described. In embodiments, a protected memory management architecture (“PMMA”) may be configured to control accesses to protected physical memory. The PMMA may provide a protected virtual memory window for dynamic allocation of protected memory regions. During forward translation of virtual memory addresses, the PMMA may check a region ID of a process before allowing access. During reverse translation of a physical memory address, the PMMA may prevent accesses to protected physical memory addresses. The PMMA may also dynamically allocate physical memory to protected memory regions in virtual memory and may authenticate the physical memory as available before allocation. Other embodiments may be described and claimed.

Abstract: A method for creating virtual machine, a virtual machine monitor and a virtual machine system are provided in the embodiments of this application. The method comprises: mapping guest frame number (GFN) corresponding to a pseudo-physical memory of a virtual machine to a shared zero page, the shared zero page being a page having content of all zeros in physical memory; when the GFN is written by the virtual machine and if a page exception occurs, allocating a physical memory page to relieve the mapping relation between the guest frame number (GFN) and the shared zero page, and establishing a mapping relation between the guest frame number (GFN) and a machine frame number (MFN) of the physical memory page. The method can reduce the amount of memory used in virtual machine startup, improve virtual machine density, and support the concurrent startup of a memory overcommitted number of virtual machine.

Abstract: Mechanisms are provided, in a data processing system, for accessing a memory location in a physical memory of the data processing system. With these mechanisms, a request is received from an application to access a memory location specified by an effective address in an application address space. A translation is performed, at a user level of execution, of the effective address to a real address table index (RATI) value corresponding to the effective address. At a hardware level of execution, a lookup operation is performed that looks-up the RATI value in a real address table data structure maintained by trusted system level hardware of the data processing system, to identify a real address for accessing physical memory. A memory location in physical memory is thereafter accessed based on the identified real address.

Abstract: A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device (e.g., a graphics processing unit, GPU). The non-CPU may support virtual to physical address mapping and may thus be aware of the memory pages, which may not be pinned but may be accessed by the non-CPU. The non-CPU may notify or send such information to a run-time component such as a device driver associated with the CPU. In one embodiment, the device driver may, dynamically, perform pinning of such memory pages, which may be accessed by the non-CPU. The device driver may even unpin the memory pages, which may be no longer accessed by the non-CPU. Such an approach may allow the memory pages, which may be no longer accessed by the non-CPU to be available for allocation to the other CPUs and/or non-CPUs.

Abstract: A technique for permitting multiple virtual file system having the same VFS identifier to be served by a single storage system. A data frame descriptor data structure is modified to include a storage pool index value that indexes into a storage pool array to identify a storage pool descriptor. The storage pool (SP) descriptor includes a SP ID, which is used in conjunction with a VFS ID to uniquely identify the VFS to which dirtied data is to be written.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Abstract: The page tables in existing art are modified to allow virtual address resolution by mapping to multiple overlapping entries, and resolving a physical address from the most specific entry. This enables more efficient use of system resources by allowing smaller frames to shadow larger frames. A page table is selected. When a virtual address in a request corresponds to an entry in the page table, which identifies a next page table associated with the large frame, a determination is made that the virtual address corresponds to an entry in the next page table, the entry in the next page table referencing a small frame overlay for the large frame. The virtual address is mapped to a physical address in the small frame overlay using data of the entry in the next page table. The physical address in a process-specific view of the large frame is returned.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Abstract: In a computer system having virtual machines, one or more unused bits of a guest virtual address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, sub-pages can be virtually addressed at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, sub-pages can be virtually addressed at a granularity that is 1/(2M)-th of a memory page. The granularity of page sizes can be selected according to particular use cases. In the case of COW optimization, page sizes can be set statically between 4 KB and 2 MB or configured dynamically among multiple page sizes.

Abstract: A method and system for tracking accesses to virtual addresses are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of receiving a virtual address from a client requesting to access memory in a graphics context, updating access state information corresponding to a virtual page associated with the graphics context in which the virtual address resides, after the virtual address successfully maps to a physical memory location, and determining whether to evict a physical page associated with the graphics context based on the access state information.

Abstract: One embodiment illustrated herein includes a method that may be practiced in a computing environment. The method includes acts for providing direct access to hardware to virtual machines. The method includes determining that a virtual machine should have access to a piece of hardware. The method further includes a virtual machine requesting access to the hardware from the host wherein a host is a special partition that controls the physical hardware of a computing system and manages virtual machines. The method further includes the host configuring the hardware to allow access to the hardware directly by the virtual machine by the host mapping hardware resources into the virtual machine's address space. The method further includes the virtual machine directly accessing the hardware without going through the host once the hardware has been configured by the host.

Abstract: An apparatus comprising an arbiter circuit, a translation circuit and a controller circuit. The arbiter circuit may be configured to generate one or more first control signals and a data write signal in response to an input signal and a read data signal. The translation circuit may be configured to generate a one or more second control signals in response to the one or more first control signals and the write address signal. The controller circuit may be configured to generate an address signal in response to the one or more second control signals.

Abstract: A system TLB accepts translation prefetch requests from initiators. Misses generate external translation requests to a walker port. Attributes of the request such as ID, address, and class, as well as the state of the TLB affect the allocation policy of translations within multiple levels of translation tables. Translation tables are implemented with SRAM, and organized in groups.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: A controller, a data storage device and a data storage system including the controller, and a data processing method are provided. The controller may process a plurality of instructions in parallel by including a plurality of address translation central processing units (CPUs) in a multi-channel parallel array structure, thereby improving the performance of a semiconductor memory system.

Abstract: Space sharing between logical volumes is achieved through a technique that enables available storage space to be flexibly consumed and released by the logical volumes. Each logical volume is associated with an address tree that defines how available storage space is consumed by the logical volume. The technique involves receiving an input/output (I/O) operation that specifies a logical address within an address tree associated with the logical volume, parsing the address tree to identify an entry therein, if any, that is associated with the logical address, where the entry stores physical address information that is associated with the logical address. If it is determined that the entry exists, then one or more translated I/O operations are generated based on the physical address information and forwarded to a physical device manager to carry out the translated one or more I/O operations.

Abstract: A method of operating a cluster of machines includes receiving a request for a disruption, determining a subset of machines of the cluster affected by the requested disruption, and determining a set of jobs having corresponding tasks on the affected machines. The method also includes computing a drain time for a drain that drains the tasks of the jobs from the affected machines, and scheduling on a drain calendar stored in non-transitory memory a drain interval for the drain. The drain interval has a start time and an end time. A maintenance system that includes a scheduler may execute such a method to maintain a cluster of machines.

Abstract: In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device.

Abstract: Disclosed is an information processing device provided with: a plurality of processing units each having a TLB (Translation Lookaside Buffer); a means for acquiring a designation of a processing unit, from among the plurality of processing units, where TLB information is to be collected, and for acquiring a designation of the timing at which the TLB information is to be collected; and a means for collecting the TLB information from the designated processing unit at the designated timing.

Abstract: A communication interface for providing an interface between a data link and a data processor, the data processor being capable of supporting an operating system and a user application, the communication interface being arranged to: support a first queue of data received over the link and addressed to a logical data port associated with a user application; support a second queue of data received over the link and identified as being directed to the operating system; and analyze data received over the link and identified as being directed to the operating system or the data port to determine whether that data meets one or more predefined criteria, and if it does meet the criteria transmit an interrupt to the operating system.

Abstract: A system and method for tuning a solid state disk memory includes computing a metric representing a usage trend of a solid state disk memory. Whether one or more parameters need to be adjusted to provide a change in performance is determined. The parameter is adjusted in accordance with the metric to impact the performance of running workloads. These steps are repeated after an elapsed time interval.

Abstract: A processor system according to the present invention includes a storage unit, a control information area that stores an access prohibit flag capable of switching from an allow side to a prohibit side, a main PEa that issues an access request to the storage unit and a request for rewriting a copy register, a security PE that evaluates whether or not the request for rewriting the copy register is valid, the copy register that stores, when the access prohibit flag is set to the allow side, a value corresponding to the allowance and, when the access prohibit flag is set to the prohibit side, a value corresponding to an evaluation result by the security PE, and an access control circuit that controls whether or not to allow access from the main PEa to the storage unit based on an output value from the copy register.

Abstract: There is provided a system and a computer program product for detecting a conflict between a transaction and a TLB (Translation Lookaside Buffer) shootdown in a transactional memory in which a TLB shootdown operation message is received by a processor to invalidate at least one entry in a TLB of the processor corresponding to at least one page. The processor tracks pages touched by the transaction. The processor determines whether the received TLB shootdown operation message is associated with one of the touched pages. The processor aborts the transaction in response to determining that the received TLB shootdown operation message is associated with one of the touched pages.

Abstract: There is provided a method for detecting a conflict between a transaction and a TLB (Translation Lookaside Buffer) shootdown in a transactional memory in which a TLB shootdown operation message is received by a processor to invalidate at least one entry in a TLB of the processor corresponding to at least one page. The processor tracks pages touched by the transaction. The processor determines whether the received TLB shootdown operation message is associated with one of the touched pages. The processor aborts the transaction in response to determining that the received TLB shootdown operation message is associated with one of the touched pages.

Abstract: This disclosure is related to systems and methods for selective metadata storage in a system having multiple memories. In one example, a device may include a control circuit configured to selectively store a metadata base map in a first memory or a second memory. The metadata base map may include information to determine a physical memory address from a logical block address. The control circuit may also be configured to store metadata updates separately from the metadata base map. The metadata updates may comprise changes to the metadata base map. The control circuit may also be configured to selectively store the metadata updates in the first memory or the second memory based on characteristics of the device.

Abstract: Managing data in a computing system comprising a plurality of cores includes: assigning an address within a memory address space for access by one of a plurality of memory controllers coupled to different respective cores based on a designated portion of the address. The designated portion is selected to exclude one or more highest order bits and bits that correspond to a cache line associated with the memory address. In response to a memory access request at one of the cores to access data stored at the address, the system determines which of the plurality of memory controllers to which the memory access request is to be directed based on the designated portion of the address.

Abstract: A system and method including, in some embodiments, receiving a request for a graphics memory address for an input/output (I/O) device assigned to a virtual machine in a system that supports virtualization, and installing, in a graphics memory translation table, a physical guest graphics memory address to host physical memory address translation.

Abstract: Translation management instructions are used in a multi-node data processing system to facilitate remote management of address translation data structures distributed throughout such a system. Thus, in multi-node data processing systems where multiple processing nodes collectively handle a workload, the address translation data structures for such nodes may be collectively managed to minimize translation misses and the performance penalties typically associated therewith.

Abstract: A method for processing data of a control unit in a data communication device, which has a first memory area and a second memory area, and is connected to the control unit through an interface. Data from the control unit is transmitted to the data communication device through the interface. A value is stored identically in the first memory area and in the second memory area. The data communication device tests whether a first trigger is present, and if present, storage in the first memory area is discontinued, or the trigger class of the first trigger is tested and storage in the first memory area is discontinued only in the presence of a predefined trigger class. Subsequently, values of the data are read out from the first memory area, whereby values arriving chronologically after the first trigger are stored in the second memory area by the data communication device.

Abstract: A management method of a virtual-to-physical address translation system includes the following steps: providing a first storage space, wherein the first storage space includes a plurality of buffer entries; providing a second storage space, wherein the second storage space includes a plurality of translation entries, and the translation entries correspond to a plurality of translation indices; and when receiving a write instruction to write a first virtual-to-physical address translation into a specific buffer entry of the buffer entries, storing the first virtual-to-physical address translation in a write translation entry of the translation entries according to a first part of bits of a first virtual address corresponding to the first virtual-to-physical address translation, and storing the first virtual address and a write translation index corresponding to the write translation entry in the specific buffer entry.

Abstract: Embodiments of the present invention provide an approach for protecting visible data during computerized process usage. Specifically, in a typical embodiment, when a computerized process is identified, a physical page key (PPK) is generated (e.g., a unique PPK may be generated for each page of data) and stored in at least one table. Based on the PPK a virtual page key (VPK) is generated and stored in at least one register. When the process is later implemented, and a request to access a set of data associated the process is received, it will be determined whether the VPK is valid (based on the PPK). Based on the results of this determination, a data access determination is made.

Abstract: Activity level of memory pages is classified in virtual machine environment, so that processes such as live VM migration and checkpointing, among others, can be carried out more efficiently. The method includes the steps of scanning page table entries of hypervisor-managed page tables continuously over repeating scan periods to determine whether memory pages have been accessed or not, and for each memory page, determining an activity level of the memory page based on whether the memory page has been accessed or not since a prior scan and storing the activity level of the memory page. The activity level of the memory page may be represented by one or more bits of its page table entry and may be classified as having at least two states ranging from hot to cold.

Abstract: An address translation table stores therein an association relation between a logical address and a physical address, change information indicating a change in the association relation when the association relation is changed such that a physical address having been associated with each logical address is associated with a different logical address, and the different logical address. A table control unit, when receiving a command to move data between logical addresses from a CPU, changes the association relation in the address translation table such that a movement-destination logical address is associated with a physical address in which the data is stored, sets change information in a movement-source logical address, and stores the movement-destination logical address as a different logical address associated with the movement-source logical address.

Abstract: A memory system comprises a translation lookaside buffer (TLB) configured to receive a virtual address and to search for a TLB entry matching the virtual address, and a translation information buffer (TIB) configured to be connected to the TLB and determine whether a physical address corresponding to the virtual address falls into a continuous mapping area if the TLB entry matching the virtual address is not found.

Abstract: A computer system and a method are provided that reduce the amount of time and computing resources that are required to perform a hardware table walk (HWTW) in the event that a translation lookaside buffer (TLB) miss occurs. If a TLB miss occurs when performing a stage 2 (S2) HWTW to find the PA at which a stage 1 (S1) page table is stored, the MMU uses the IPA to predict the corresponding PA, thereby avoiding the need to perform any of the S2 table lookups. This greatly reduces the number of lookups that need to be performed when performing these types of HWTW read transactions, which greatly reduces processing overhead and performance penalties associated with performing these types of transactions.

Abstract: Two or more processes for executing a source application are emulated using: a virtual trampoline memory in which each emulated process has a respective private trampoline memory; and a shared code heap memory. Each emulated process only sees the shared code heap and its respective private trampoline memory. A respective equivalent target instruction fragment for writing to the code heap is generated for each of multiple source instruction fragments from the application, each target instruction fragment being indexed by its physical address in the code heap. Each of at least one jump instruction in the fragment is replaced with a jump to a corresponding slot in the virtual trampoline memory. A trap is written to each corresponding private trampoline slot, each trap adapted to be replaced by a jump to an address in the code heap corresponding to the jump destination.

Abstract: The invention relates to controlling memory-usage of a functional component, e.g. a network interface of a router or a switch. A portion of a virtual memory organized to comprise virtual memory pages is reserved (201) for the use of the functional component. Mapping between the virtual memory pages and physical memory areas implemented with a physical memory is formed (202), and data items providing accesses to the physical memory areas are written (203) to one or more of the physical memory areas. The functional component is enabled to directly access to a physical memory area mapped to a virtual memory page so that the data item that provides access to this physical memory area is read (204) from the physical memory with the aid of the mapping and a virtual memory address related to the virtual memory page, and the read data item is delivered (205) to the functional component.

Abstract: The disclosed embodiments provide a system that uses broadcast-based TLB-sharing techniques to reduce address-translation latency in a shared-memory multiprocessor system with two or more nodes that are connected by an electrical interconnect. During operation, a first node receives a memory operation that includes a virtual address. Upon determining that one or more TLB levels of the first node will miss for the virtual address, the first node uses the electrical interconnect to broadcast a TLB request to one or more additional nodes of the shared-memory multiprocessor in parallel with scheduling a speculative page-table walk for the virtual address. If the first node receives a TLB entry from another node of the shared-memory multiprocessor via the electrical interconnect in response to the TLB request, the first node cancels the speculative page-table walk. Otherwise, if no response is received, the first node instead waits for the completion of the page-table walk.

Abstract: A system and method for efficiently handling translation look-aside buffer (TLB) misses. A memory management unit (MMU) detects when a given virtual address misses in each available translation-lookaside-buffer (TLB). The MMU determines whether a memory access operation associated with the given virtual address is the oldest, uncompleted memory access operation in a scheduler. If this is the case, a demand table walk (TW) request may be stored in an available entry in a TW queue. During this time, the utilization of the memory subsystem resources may be low. While a demand TW request is stored in the TW queue, subsequent speculative TW requests may be stored in the TW queue. When the TW queue does not store a demand TW request, no more entries of the TW queue may be allocated to store TW requests.

Abstract: A data writing method and a memory controller and a memory storage apparatus using the same are provided. The method includes selecting physical units as a global random area and building a global random searching table for recording update information corresponding to updated logical pages that data stored in the global random area belongs to. The method also includes receiving updated data belonging to a logical page of a logical unit, assigning an index number for the logical unit, writing the updated data into the global random area, and using the index number to record update information corresponding the logical page in the global random searching table. Accordingly, a global random searching table having smaller size can be used for recording update information corresponding to updated logical pages that data stored in the global random area belongs to.

Abstract: Methods, devices, and instructions for performing a reverse translation lookaside buffer (TLB) look-up using a physical address input, including obtaining with a first processor the physical address input, wherein the physical address input indicates a physical address corresponding to a shared memory, obtaining a first mask associated with a first virtual address from a first TLB entry within a TLB associated with the first processor, wherein the obtained first mask is a bit pattern, obtaining from the first TLB entry a first page frame number associated with the shared memory, applying the obtained first mask to the obtained first page frame number to generate a first value, applying the obtained first mask to the obtained physical address input to generate a second value, and comparing the first value and the second value to determine whether the first value and the second value match.

Abstract: The disclosed embodiments provide techniques for reducing address-translation latency and the serialization latency of combined TLB and data cache misses in a coherent shared-memory system. For instance, the last-level TLB structures of two or more multiprocessor nodes can be configured to act together as either a distributed shared last-level TLB or a directory-based shared last-level TLB. Such TLB-sharing techniques increase the total amount of useful translations that are cached by the system, thereby reducing the number of page-table walks and improving performance. Furthermore, a coherent shared-memory system with a shared last-level TLB can be further configured to fuse TLB and cache misses such that some of the latency of data coherence operations is overlapped with address translation and data cache access latencies, thereby further improving the performance of memory operations.

Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.

Abstract: Providing for address translation in a virtualized system environment is disclosed herein. By way of example, a memory management apparatus is provided that comprises a shared translation look-aside buffer (TLB) that includes a plurality of translation types, each supporting a plurality of page sizes, one or more processors, and a memory management controller configured to work with the one or more processors. The memory management controller includes logic configured for caching virtual address to physical address translations and intermediate physical address to physical address translations in the shared TLB, logic configured to receive a virtual address for translation from a requester, logic configured to conduct a table walk of a translation table in the shared TLB to determine a translated physical address in accordance with the virtual address, and logic configured to transmit the translated physical address to the requester.

Abstract: A method and apparatus for virtual address mapping are provided. The method includes determining an offset value respective of at least a first portion of code stored on a code memory unit, generating a first virtual code respective of the first portion of code and a second virtual code respective of a second portion of code stored on the code memory unit; mapping the first virtual code to a first virtual code address and the second virtual code to a second virtual code address; generating a first virtual data respective of the first portion of data and a second virtual data respective of the second portion of data; and mapping the first virtual data to a first virtual data address and the second virtual data to a second virtual data address.

Abstract: A memory management unit (MMU) is disclosed for storing mappings between virtual addresses and physical addresses. The MMU includes a translation look-aside buffer (TLB) and a memory management unit controller. The TLB stores mappings between a virtual address and a physical address. The MMU controller receives a request to insert an entry into the TLB and performs a set of operations based on the received request. The MMU controller determines whether an entry stored in the TLB is associated with the virtual address of the request, removes the entry stored in the TLB that is associated with the virtual address and inserts the requested entry into the TLB.

Abstract: Mechanisms, in a data processing system comprising a processor and an address translation cache, for caching address translations in the address translation cache are provided. The mechanisms receive an address translation from a server computing device to be cached in the data processing system. The mechanisms generate a cache key based on a current valid number of mirror copies of data maintained by the server computing device. The mechanisms allocate a buffer of the address translation cache, corresponding to the cache key, for storing the address translation and store the address translation in the allocated buffer. Furthermore, the mechanisms perform an input/output operation using the address translation stored in the allocated buffer.

Abstract: An integrated circuit with a pulse clock unit having shared gating control includes one or more logic blocks, each including a clock distribution network configured to distribute a clock signal. The integrated circuit also includes a clock unit coupled to the one or more logic blocks and configured to generate a pulse clock signal formed using a chain of inverting logic gates. The clock unit may be further configured to provide the pulse clock signal to the clock distribution network. The clock unit may also include an enable input that is coupled to one input of one of the inverting logic gates. In addition, the clock unit may be configured to selectively enable and disable the pulse clock signal in response to an enable signal on the enable input.