Abstract: An apparatus for storing selectors directly into segment registers within a single processor cycle. New selectors are stored into addressable segment registers prior to being validated. Old selectors which are shifted into temporary register space prior to being overwritten. If a selector fails validation tests, and requires restoration, the old selector is shifted back into the appropriate segment register thereby restoring the state of the selector.

Abstract: Address translation means for distributed memory massively parallel processing (MPP) systems include means for defining virtual addresses for processing elements (PE's) and memory relative to a partition of PE's under program control, means for defining logical addresses for PE's and memory within a three-dimensional interconnected network of PE's in the MPP, and physical addresses for PE's and memory corresponding to identities and locations of PE modules within computer cabinetry. As physical PE's are mapped into or out of the logical MPP, as spares are needed, logical addresses are updated. Address references generated by a PE within a partition in virtual address mode are converted to logical addresses and physical addresses for routing on the network.

Abstract: The amount of real memory space used by descriptor tables of a computer system is reduced. On system initialization, sufficient contiguous virtual memory space for each table is allotted for descriptors in the tables to define all memory space in both central storage and expanded storage. However, only descriptors for on-line storage locations, relative to a particular partition, are placed in these tables. As the system operates, the tables are continuously updated, removing descriptors for storage locations taken off-line and adding descriptors for blocks of memory brought on-line so that the tables reflect only the storage locations then on-line in the particular partition.