Varying Address Bit-length Or Size Patents (Class 711/212)
  • Patent number: 10613862
    Abstract: An instruction architecturally defined to be a looping instruction, in which a loop is configured to repeat a plurality of times to perform an operation on up to a defined number of units of data, is to be processed. The processing includes replicating a selected character a number of times to provide a replicated selected character, and using a sequence of operations to perform the operation, the sequence of operations replacing the loop and providing a non-looping sequence to perform the operation on up to the defined number of units of data. The sequence of operations is configured to repeat one or more times, and to terminate based on the replicated selected character.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 10592421
    Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Carlos V. Rozas, Ilya Alexandrovich, Ittai Anati, Alex Berenzon, Michael A. Goldsmith, Barry E. Huntley, Anton Ivanov, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Rinat Rappoport, Scott D. Rodgers, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith, William C. Wood
  • Patent number: 10592407
    Abstract: Short pointer mode applications are able to execute in long pointer mode environments. A plurality of actions is performed to prepare a short pointer mode application for execution in the long pointer mode environment. These actions include allocating memory for one or more in-memory short pointers of the application. The memory being allocated for an in-memory short pointer is of a size corresponding to a size of the in-memory short pointer. Further, a register is allocated for an in-register short pointer of the application. The register is allocated at a size corresponding to a long pointer mode. The size corresponding to the long pointer mode is different from the size of the in-memory short pointer.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 10585790
    Abstract: Short pointer mode applications are able to execute in long pointer mode environments. A plurality of actions is performed to prepare a short pointer mode application for execution in the long pointer mode environment. These actions include allocating memory for one or more in-memory short pointers of the application. The memory being allocated for an in-memory short pointer is of a size corresponding to a size of the in-memory short pointer. Further, a register is allocated for an in-register short pointer of the application. The register is allocated at a size corresponding to a long pointer mode. The size corresponding to the long pointer mode is different from the size of the in-memory short pointer.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 10545992
    Abstract: A method, system and computer program product for providing consolidated access to data of a plurality of source databases. Tables of each of the source databases are replicated to a shared accelerator. The source DBMSs are configured to dispatch queries to the accelerator for accelerating query execution. The accelerator is configured such that the replicated tables can only be accessed by the source DBMS having provided said tables for executing a dispatched query. A user can select one of the source DBMSs to act as a consolidated DBMS—C-DBMS. The C-DBMS provides the consolidated access. The user is enabled to select tables managed by another one of the DBMSs. In response to receiving the selection of the tables, the accelerator is re-configuring such that the C-DBMS is granted access also to the copies of the selected tables in the accelerator.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peter Bendel, Oliver Benke, Namik Hrle, Ruiping Li, Daniel Martin, Maryela E. Weihrauch
  • Patent number: 10528345
    Abstract: Instructions and logic provide atomic range operations in a multiprocessing system. In one embodiment an atomic range modification instruction specifies an address for a set of range indices. The instruction locks access to the set of range indices and loads the range indices to check the range size. The range size is compared with a size sufficient to perform the range modification. If the range size is sufficient to perform the range modification, the range modification is performed and one or more modified range indices of the set of range indices is stored back to memory. Otherwise an error signal is set when the range size is not sufficient to perform said range modification. Access to the set of range indices is unlocked responsive to completion of the atomic range modification instruction. Embodiments may include atomic increment next instructions, add next instructions, decrement end instructions, and/or subtract end instructions.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: January 7, 2020
    Assignee: Intel Corporation
    Inventors: Ilan Pardo, Oren Ben-Kiki, Arch D. Robison, Nadav Chachmon, James H. Cownie
  • Patent number: 10481816
    Abstract: Apparatus, systems, methods, and computer program products for providing dynamically assignable data latches are disclosed. A non-volatile memory die includes a non-volatile memory medium. A plurality of sets of data latches of a non-volatile memory die are configured to facilitate transmission of data to and from a non-volatile memory medium, and each of the sets of data latches are associated with a different identifier. An on-die controller is in communication with a sets of data latches. An on-die controller is configured to receive a first command for a first memory operation comprising a selected identifier. An on-die controller is configured to execute a first memory operation on a non-volatile memory medium using a set of data latches of a plurality of sets of data latches, and the set of data latches is associated with a selected identifier.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: November 19, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Mark Shlick, Hadas Oshinsky, Amir Shaharabany, Yoav Markus
  • Patent number: 10452682
    Abstract: A method, system and computer program product for providing consolidated access to data of a plurality of source databases. Tables of each of the source databases are replicated to a shared accelerator. The source DBMSs are configured to dispatch queries to the accelerator for accelerating query execution. The accelerator is configured such that the replicated tables can only be accessed by the source DBMS having provided said tables for executing a dispatched query. A user can select one of the source DBMSs to act as a consolidated DBMS—C-DBMS. The C-DBMS provides the consolidated access. The user is enabled to select tables managed by another one of the DBMSs. In response to receiving the selection of the tables, the accelerator is re-configuring such that the C-DBMS is granted access also to the copies of the selected tables in the accelerator.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Peter Bendel, Oliver Benke, Namik Hrle, Ruiping Li, Daniel Martin, Maryela E. Weihrauch
  • Patent number: 10324723
    Abstract: Disclosed is a digital processor comprising an instruction memory having a first input, a second input, a first output, and a second output. A program counter register is in communication with the first input of the instruction memory. The program counter register is configured to store an address of an instruction to be fetched. A data pointer register is in communication with the second input of the instruction memory. The data pointer register is configured to store an address of a data value in the instruction memory. An instruction buffer is in communication with the first output of the instruction memory. The instruction buffer is arranged to receive an instruction according to a value at the program counter register. A data buffer is in communication with the second output of the instruction memory. The data buffer is arranged to receive a data value according to a value at the data pointer register.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: June 18, 2019
    Assignee: NXP USA, Inc.
    Inventors: Peter J Wilson, Brian C Kahne, Jeffrey W Scott
  • Patent number: 10140126
    Abstract: A variable length instruction processor system and method is provided. Before a processor core executes an instruction, the system and method applied in a processor field convert the instruction into micro-operation(s) and the micro-operation(s) can be filled into a cache system that can be directly accessed by a processor core, reducing the depth of a pipeline and improving efficiency of the pipeline.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: November 27, 2018
    Assignee: Shanghai XinHao Microelectronics Co. Ltd.
    Inventor: Kenneth Chenghao Lin
  • Patent number: 10133653
    Abstract: Recording and playback of trace log data and video log data for programs is described. In one aspect, a method for viewing log data recorded during execution of a program includes causing a display of recorded images depicting prior visual user interaction with the program during a particular time period. The method also includes causing a display of messages tracing and describing prior execution of the program during the particular time period. The display of the messages and the display of the recorded images are synchronized.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: November 20, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, David Varghese
  • Patent number: 9990282
    Abstract: An address range expander associated with a processor and a physical memory device determines that address transformation has been enabled with respect to an address indicated on the processor's address bus. The expander generates, using one or more address expansion parameter registers, a transformed address corresponding to the untransformed address within an address range of the physical memory device, and transmits the transformed address to a controller of the physical memory device.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: June 5, 2018
    Assignee: Oracle International Corporation
    Inventors: Joseph Wright, Erik Michael Schlanger, Eric DeVolder
  • Patent number: 9798551
    Abstract: A method and apparatus for providing a scalable compute fabric are provided herein. The method includes determining a workflow for processing by the scalable compute fabric, wherein the workflow is based on an instruction set. A pipeline in configured dynamically for processing the workflow, and the workflow is executed using the pipeline.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: October 24, 2017
    Assignee: Intel Corporation
    Inventors: Scott Krig, Teresa Morrison
  • Patent number: 9535702
    Abstract: An asset management method implemented on an integrated circuit uses a keys memory storing keys, each key being associated with an asset identifier, and a data memory storing asset information. The method comprises: receiving an input command for an asset comprising an asset identifier and asset information, computing addresses to Keys memory from the asset identifier, the computing addresses comprising calculating hashes from the asset identifier, finding or allocating an entry in keys memory for the asset, based on the computed set of addresses, depending on the input command, computing a data address to the data memory for the asset from the address and position in the keys memory at which an entry has been found or allocated for the asset; reading data in the data memory at the computed data address; and executing the input command based on the data read in the data memory at the data address.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 3, 2017
    Assignee: ENYX SA
    Inventor: Edward Kodde
  • Patent number: 9430384
    Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.
    Type: Grant
    Filed: March 31, 2013
    Date of Patent: August 30, 2016
    Assignee: Intel Corporation
    Inventors: Carlos V Rozas, Ilya Alexandrovich, Ittai Anati, Alex Berenzon, Michael A Goldsmith, Barry E Huntley, Anton Ivanov, Simon P Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Rinat Rappoport, Scott Dion Rodgers, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H Smith, William Colin Wood
  • Patent number: 9075599
    Abstract: Due to the ever expanding number of registers and new instructions in modern microprocessor cores, the address widths present in the instruction encoding continue to widen, and fewer instruction opcodes are available, making it more difficult to add new instructions to existing architectures without resorting to inelegant tricks that have drawbacks such as source destructive operations. The disclosed invention utilizes specialized decode and address calculation hardware that concatenates a fixed number of least significant bits of the instruction address onto the most significant side of each register address portion contained in the instruction, yielding the full register address, instead of providing the full register address widths for every register used in the instruction. This frees up valuable opcode space for other instructions and avoids compiler complexity. This aligns nicely with how most loops are unrolled in assembly language, where independent operations are near each other in memory.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: July 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mark J. Hickey, Adam J. Muff, Matthew R. Tubbs, Charles D. Wait
  • Publication number: 20150095613
    Abstract: An asset management method implemented on an integrated circuit uses a keys memory storing keys, each key being associated with an asset identifier, and a data memory storing asset information. The method comprises: receiving an input command for an asset comprising an asset identifier and asset information, computing addresses to Keys memory from the asset identifier, the computing addresses comprising calculating hashes from the asset identifier, finding or allocating an entry in keys memory for the asset, based on the computed set of addresses, depending on the input command, computing a data address to the data memory for the asset from the address and position in the keys memory at which an entry has been found or allocated for the asset; reading data in the data memory at the computed data address; and executing the input command based on the data read in the data memory at the data address.
    Type: Application
    Filed: September 30, 2014
    Publication date: April 2, 2015
    Inventor: Edward KODDE
  • Patent number: 8990166
    Abstract: A data size characteristic of contents of a related unit of data to be written to a storage by an input/output module of a data storage application can be determined, and a storage page size consistent with the data size can be selected from a plurality of storage page sizes. The related unit of data can be assigned to a storage page having the selected storage page size, and the storage page can be passed to the input/output module so that the input/output module physically clusters the contents of the related unit of data when the input/output module writes the contents of the related unit of data to the storage. Related methods, systems, and articles of manufacture are also disclosed.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: March 24, 2015
    Assignee: SAP SE
    Inventors: Dirk Thomsen, Axel Schroeder, Ivan Schreter
  • Patent number: 8966180
    Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: February 24, 2015
    Assignee: Intel Corporation
    Inventors: Daehyun Kim, Christopher J. Hughes, Yen-Kuang Chen, Partha Kundu
  • Patent number: 8954674
    Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: February 10, 2015
    Assignee: Intel Corporation
    Inventors: Daehyun Kim, Christopher J. Hughes, Yen-Kuang Chen, Partha Kundu
  • Patent number: 8943293
    Abstract: A method includes receiving an address at a tag state array of a cache, wherein the cache is configurable to have a first size and a second size that is smaller than the first size. The method further includes identifying a first portion of the address as a set index, wherein the first portion has a same number of bits when the cache has the first size as when the cache has the second size. The method further includes using the set index to locate at least one tag field of the tag state array, identifying a second portion of the address to compare to a value stored at the at least one tag field, locating at least one state field of the tag state array that is associated with a particular tag field that matches the second portion, identifying a cache line based on a comparison of a third portion of the address to at least one status bit of the at least one state field when the cache has the second size, and retrieving the cache line.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: January 27, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Christopher Edward Koob, Ajay Anant Ingle, Lucian Codrescu, Jian Shen
  • Patent number: 8918559
    Abstract: Partitioning of a variable length scatter gather list including a processor for performing a method that includes requesting data from an I/O device comprising an I/O buffer. The requesting includes initiating a subchannel. The method further includes determining whether the subchannel supports data divisions by requesting SSQD data from the I/O device and inspecting at least one bit in the SSQD data. A determination is made whether the requested data includes a metadata block in response to determining that the subchannel support data divisions. Also, the subchannel is notified that the requested data includes the metadata block in response to determining that the requested data includes the metadata block. A location of storage is identified in an SBAL in response to notifying the subchannel.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stefan Amann, Gerhard Banzhaf, Ralph Friedrich, Raymond M. Higgs, George P. Kuch, Bruce H. Ratcliff
  • Patent number: 8898439
    Abstract: A serial flash memory and an address transmission method thereof. The serial flash memory selectively addresses a first memory space according to a first address length or addresses a second memory space according to a second address length longer than the first address length. If the first memory space is addressed according to the first address length, a first memory address is completely received within an address time duration so that data corresponding to the first memory address is initially outputted from a starting clock. In the address transmission method, if the second memory space is addressed according to the second address length, a portion of a second memory address is received within the address time duration. The other portion of the second memory address is received within a waiting time duration so that data corresponding to the second memory address is initially outputted from the starting clock.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: November 25, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuen-Long Chang, Yufe-Feng Lin, Chun-Hsiung Hung
  • Patent number: 8806132
    Abstract: An information processing device according to the present invention includes an operation unit that outputs an access request, a storage unit including a plurality of connection ports and a plurality of memories capable of a simultaneous parallel process that has an access unit of a plurality of word lengths for the connection ports, and a memory access control unit that distributes a plurality access addresses corresponding to the access request received for each processing cycle from the operation unit, and generates an address in a port including a discontinuous word by one access unit for each of the connection ports.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 12, 2014
    Assignee: NEC Corporation
    Inventor: Yasuhiro Nishigaki
  • Patent number: 8806439
    Abstract: A system having a processor receiving a copy of a program and modifying the copy to create a modified program and a memory including a memory stack, the modified program being stored in the memory stack, wherein a first image of the memory stack storing the modified program is different from a second image of the memory stack storing the copy of the program.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: August 12, 2014
    Assignee: AT & T Intellectual Property II, LP
    Inventor: Michael L. Asher
  • Patent number: 8719503
    Abstract: A method includes receiving an address at a tag state array of a cache. The cache is configurable to have a first size or a second size that is larger than the first size. The method includes identifying a first portion of the address as a set index and using the set index to locate at least one tag field of the tag state array. The method also includes identifying a second portion of the address to compare to a value stored at the at least one tag field and locating at least one state field of the tag state array associated with a particular tag field that matches the second portion. The method further includes identifying a cache line based on a comparison of a third portion of the address to at least two status bits of the at least one state field and retrieving the cache line.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: May 6, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Christopher Edward Koob, Ajay Anant Ingle, Lucian Codrescu, Jian Shen
  • Publication number: 20140089632
    Abstract: Divisions by numbers that are not divisible by two (2) can be performed in a computing system based on a summation that estimates and/or approximates the reciprocal of the dividing number or denominator value. By way of example, dividing by three (3) can be calculated based on a summation that approximates or estimates one third (?) represented as the sum of a selected group of the inverses of the powers of two (2) in a pattern, namely the sum of: ¼, 1/16, 1/64, 1/256, . . . ). Applications of the division techniques are virtually unlimited and include memory mapping of global memory addresses to memory channel addresses by dividing a global memory address into the number of memory channels, allowing memory mapping to be performed in an efficient manner even for large memory spaces using a number of memory channels that are not divisible by two, including prime numbers.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 27, 2014
    Inventor: Jeremy Branscome
  • Patent number: 8677100
    Abstract: An integrated circuit memory device has a memory array and control logic with at least a first addressing mode in which the instruction includes a first instruction code and an address of a first length; and a second addressing mode in which the instruction includes the first instruction code and an address of a second length. The first length of the address is different from the second length of the address.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: March 18, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Yulan Kuo, Kuen-Long Chang, Chun-Hsiung Hung
  • Patent number: 8656139
    Abstract: A digital processor stores pointers of different sizes in memory. The processor, specifically, executes instructions to store a long or short pointer. Long pointers reference any address in the memory's logical address space, while short pointers merely reference any address in a subset of that space. However, short pointers are smaller in size as stored in memory than long pointers. Long pointers thus support relatively large address range capabilities, while short pointers use less memory. The processor also executes instructions to load a long or short pointer into the register file, and does so in a way that does not require the processor to distinguish between the different pointers when executing other instructions. Specifically, the processor converts long and short pointers into a common format for loading into the register file, and converts pointers in the common format back into long or short pointers for storing in the memory.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: February 18, 2014
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Stephan Meier, John G. Favor, Evan Gewirtz, Robert Hathaway, Eric Trehus
  • Patent number: 8645404
    Abstract: A split data word including a portion of each of two word-aligned data words stored at two word-aligned address boundaries within a memory is read from a displaced-read memory address relative to the word-aligned address boundaries within the memory. The portions of each of the two word-aligned data words within the split data word are compared with corresponding portions of a word-aligned search pattern. A determination is made that a potential complete match for the word-aligned search pattern exists within at least one of the two word-aligned data words based upon an identified match of at least one of the portions of the two word-aligned data words within the split data word with a corresponding at least one portion of the word-aligned search pattern.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: K. S. Sadananda Aithal, Ajay K. Sami
  • Patent number: 8627015
    Abstract: A data processing system includes a storage system and caching storage controllers coupled to the storage system and to a storage network. The storage controllers operate in an active-active fashion to provide access to volumes of the storage system from any of the storage controllers in response to storage commands from the storage network. The storage controllers employ a distributed cache protocol in which (a) each volume is divided into successive chunks of contiguous blocks, and (b) either chunk ownership may be dynamically transferred among the storage controllers in response to the storage commands, or storage commands sent to a non-owning controller may be forwarded to the owning controller.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: January 7, 2014
    Assignee: EMC Corporation
    Inventors: Colin D. Durocher, Roel van der Goot
  • Patent number: 8578097
    Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: November 5, 2013
    Assignee: Intel Corporation
    Inventors: Daehyun Kim, Christopher J. Hughes, Yen-Kuang Chen, Partha Kundu
  • Patent number: 8578106
    Abstract: A method for writing data to submission queues in a storage controller including receiving an input/output (I/O) request from a client application, where the client application is associated with a virtual port and where the virtual port is associated with a physical port. The method further includes determining a size of the I/O request, identifying a queue group based on the size of the I/O request and the virtual port, where the queue group includes submission queues and is associated with the virtual port. The method further includes identifying a submission queue, sending the I/O request to a storage controller over the physical port, where the queue group is located in memory operatively connected to the storage controller and where the storage controller is configured to place the I/O request in the submission queue.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: November 5, 2013
    Assignee: DSSD, Inc.
    Inventor: Michael W. Shapiro
  • Patent number: 8516187
    Abstract: Certain embodiments described herein include a memory system which can communicate with a host system such as a disk controller of a computer system. The memory system can include volatile and non-volatile memory and a controller which are configured such that the controller backs up the volatile memory using the non-volatile memory in the event of a trigger condition. In order to power the system in the event of a power failure or reduction, the memory system can include a secondary power source which is not a battery and may include, for example, a capacitor or capacitor array. The memory system can be configured such that the operation of the volatile memory is not adversely affected by the non-volatile memory or the controller when the volatile memory is interacting with the host system.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: August 20, 2013
    Assignee: Netlist, Inc.
    Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott Milton, Jayesh Bhakta
  • Patent number: 8489856
    Abstract: Provided are a system and article of manufacture for providing an address format compatible with different addressing formats used for addressing different sized address spaces. An address format is used in an operating system to address storage space in a storage device comprising a first region and a second region of storage space. A first group of applications uses the address format to only address the storage space in the first region and is not coded to use the address format to access the second region and a second group of applications uses the address format to address the storage space in the first and second regions.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Harry Morris Yudenfriend, Richard Anthony Ripberger, Peter Grimm Sutton, Matthew Joseph Kalos, Wayne Erwin Rhoten, James B. Cammarata, John Glenn Thompson, Josephine M. Edwards, Michelle Dais
  • Patent number: 8429326
    Abstract: A method and system for identifying a NAND-Flash without reading a device ID. The method includes: executing an identification flow for setting a first page of a block as a target block, utilizing a combinations table to query a target block, evaluating a result by comparing a identifying information in the target block with the combinations table, trying all combinations in the combinations table until correctly identifying the NAND-Flash by having a positive match result or returning an error if none of the combinations match.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: April 23, 2013
    Assignee: MediaTek Inc.
    Inventors: Huey-Tyug Chua, Yann-Chang Lin, Ching-Lin Hsu
  • Patent number: 8423682
    Abstract: Apparatus and systems, as well as methods and articles, may operate to detect an input/output access operation associated with a configuration memory address and a first memory address bit size. The configuration memory address and associated configuration data may be combined into a packet having a second memory address bit size (e.g., 64 bits) greater than the first memory address bit size (e.g., 32 bits). The packet may be used to establish compatibility for legacy operating systems that attempt to communicate with peripheral component interconnect (PCI) interface-based peripherals, and similar platform devices, that have been integrated into the same package as the processor.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: April 16, 2013
    Assignee: Intel Corporation
    Inventors: Sham M. Datta, Robert Greiner, Frank Binns, Keshavan Tiruvallur, Rajesh Parthasarathy, Madhavan Parthasarathy
  • Patent number: 8386750
    Abstract: A multiprocessor computer system has a plurality of first processors having a first addressable memory space, and a plurality of second processors having a second addressable memory space. The second addressable memory space is of a different size than the first addressable memory space, and the first addressable memory space and second addressable memory space comprise a part of the same common address space.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: February 26, 2013
    Assignee: Cray Inc.
    Inventors: Michael Parker, Timothy J. Johnson, Laurence S. Kaplan, Steven L. Scott, Robert Alverson, Skef Iterum
  • Publication number: 20120324205
    Abstract: A memory management table processing method for storing a plurality of entries belonging to a plurality of memory management tables into a buffer memory of a memory storage apparatus is provided, wherein each of the entries has at least one invalid bit. The present method includes following steps. An area corresponding to each of the memory management tables is configured in the buffer memory. Invalid bit information corresponding to each of the memory management tables is recorded. The invalid bit in each of the entries is removed according to the invalid bit information corresponding to each of the memory management tables, so as to generate a valid data stream corresponding to each of the entries. Each of the valid data streams is written into the corresponding area in the buffer memory. Accordingly, the storage space of the buffer memory can be efficiently utilized.
    Type: Application
    Filed: August 21, 2011
    Publication date: December 20, 2012
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei-Chen Teo, Ming-Jen Liang, Chih-Kang Yeh
  • Publication number: 20120297162
    Abstract: A method, apparatus and algorithm for quickly detecting an address match in a deeply pipelined processor design in a manner that may be implemented using a minimum of physical space in the critical area of the processor. The address comparison is split into two parts. The first part is a fast, partial address match comparator system. The second part is a slower, full address match comparator system. If a partial match between a requested address and a registry address is detected, then execution of the program or set of instructions requesting the address is temporarily suspended while a full address match check is performed. If the full address match check results in a full match between the requested address and a registry address, then the program or set of instructions is interrupted and stopped. Otherwise, the program or set of instructions continues execution.
    Type: Application
    Filed: November 15, 2011
    Publication date: November 22, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Miles Robert Dooley, Scott Bruce Frommer, David Allen Hrusecky, Sheldon B. Levenstein
  • Patent number: 8281052
    Abstract: A microprocessor system having a microprocessor and a double data rate memory device having separate groups of external pins adapted to receive addressing, data, and control information and a memory controller adapted to set a burst type of the double data rate memory to interleaved or sequential by sending a signal through one of the external pins of the double data rate memory device, such that when a read command is sent by the controller, depending on the burst type set, the double data rate memory device returns interleaved or sequentially output data to the memory controller.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: October 2, 2012
    Assignee: Round Rock Research, LLC
    Inventor: Christopher S. Johnson
  • Patent number: 8266409
    Abstract: In a particular embodiment, a cache is disclosed that includes a tag state array that includes a tag area addressable by a set index. The tag state array also includes a state area addressable by a state address, where the set index and the state address include at least one common bit.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: September 11, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Christopher Edward Koob, Ajay Anant Ingle, Lucian Codrescu, Jian Shen
  • Publication number: 20120131252
    Abstract: Systems and methods of routing data units such as data packets or data frames that provide improved system performance and more efficient use of system resources. The disclosed systems and methods employ memory mapping approaches in conjunction with transaction ID tag fields from the respective data units to assign each tag value, or at least one range of tag values, to a specified address, or at least one range of specified addresses, for locations in internal memory that store corresponding transaction parameters. The disclosed systems and methods can also apply selected bits from the transaction ID tag fields to selector inputs of one or more multiplexor components for selecting corresponding transaction parameters at data inputs to the multiplexor components. The disclosed systems and methods may be employed in memory-read data transfer transactions to recover the transaction parameters necessary to determine destination addresses for memory locations where the memory-read data are to be transmitted.
    Type: Application
    Filed: November 24, 2010
    Publication date: May 24, 2012
    Inventor: Frank Rau
  • Patent number: 8180994
    Abstract: During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: May 15, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Steven Sprouse, Jianmin Huang, Chris Avila, Yichao Huang, Emilio Yero
  • Patent number: 8171200
    Abstract: A method includes indexing a translation table stored in memory with a first index of a virtual address corresponding to a first memory region size by querying the translation table at first locations associated with the first index. Indexing the translation table with a second index of the virtual address corresponding to a second memory region size by querying the translation table at second locations associated with the second index. The translation table includes translations for mapping address tags of the virtual address to physical addresses. The first index is different than the second index, and the first memory region size is different than the second memory region size.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: May 1, 2012
    Assignee: Marvell International Ltd.
    Inventors: Dennis O'Connor, Stephen J. Strazdus
  • Patent number: 8161216
    Abstract: An interface transmission device and method are disclosed. The interface device, located in a first device, includes a transmission interface and a receiving circuit. The transmission interface receives an initialization signal and an interface signal. The receiving circuit receives the initialization signal through the transmission interface, and acquires a bit length of the interface signal according to the initialization signal. Thereby, the first device resolves the interface signal according to the bit length.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: April 17, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventors: Wen-Hsia Kung, Wen-Che Wu, Hsin-Hung Yi
  • Patent number: 8156262
    Abstract: One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: April 10, 2012
    Assignee: Round Rock Research, LLC
    Inventor: Christopher S. Johnson
  • Patent number: 8127110
    Abstract: A method of transmitting data between processors, including: establishing and storing an encoding method for each area of virtual address space of a first processor in a predetermined storage device; determining an area of virtual address space corresponding to data to be transmitted to a second processor; and determining the encoding method corresponding to the determined area of the virtual address space with reference to the storage device and transmitting the data to the second processor by using the determined encoding method.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: February 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keun Soo Yim, Jeong Joon Yoo, Jung Keun Park, Chae Seok Im, Jan Don Lee, Woon Gee Kim, Seung Hyun Choi
  • Patent number: 8099723
    Abstract: A method, apparatus, and computer instructions for referencing a constant pool. A determination is made as to whether a bytecode references the constant pool. A relative offset to the constant pool is identified for the bytecode, in response to the bytecode referencing the constant pool. The bytecode is then replaced with a new bytecode containing the relative offset. The relative offset is used to reference the constant pool.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: January 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Peter Wiebe Burka, Graham Alan Chapman, Trent A. Gray-Donald, Karl Michael Taylor
  • Patent number: RE45486
    Abstract: The present invention relates to a method for addressing the memory locations of a memory card. There are several memory locations in a memory card for storing data, in which case in order to address a specific memory location an address is formed. At least one parameter is stored in the memory card, on the basis of which parameter the number of memory locations of a memory card can be calculated, and a specific number of bits is reserved for said at least one parameter. In the method, two or more memory locations are addressed with one address, and/or the number of bits that can be used in an address is increased. The invention also relates to a system and a memory card in which the method is applied.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: April 21, 2015
    Assignee: Memory Technologies LLC
    Inventors: Marko Ahvenainen, Kimmo Mylly