Abstract: A central processing unit (CPU) is described including a register file and an execution core coupled to the register file. The register file includes a standard register set and an extended register set. The standard register set includes multiple standard registers, and the extended register set include multiple extended registers. The execution core fetches and executes instructions, and receives a signal indicating an operating mode of the CPU. The execution core responds to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes a prefix portion including information needed to access the at least one extended register. The standard registers may be general purpose registers of a CPU architecture associated with the instruction. The number of extended registers may be greater than the number of general purpose registers defined by the CPU architecture.

Abstract: One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. This embodiment includes an option to segment the cache. When the cache is segmented, the cache line size is halved. The segmentation allows the entire cache to be accessed without doubling the amount of tag address storage locations. The non-segmented cache may be used for memory systems using a burst length of eight bytes, while the segmented cache may be used for memory systems using a burst length of four bytes.

Abstract: A universal automated order processing system represents multiple (e.g., hundreds or thousands) participating merchants who offer their products through the system. Customers become qualified for using the system by supplying a set of information (e.g., name, credit card number, shipping address) that is stored in a customer database. When a customer wishes to order a product, the customer calls the system, customer identity is automatically confirmed, the customer enters a product order number and the complete order is routed to the appropriate merchant with the information necessary for the merchant to fulfill the order. Available credit verification and other aspects of credit card transactions may be handled by either the system operator or the merchant. The system operator may offer revolving credit. The system may also be used to provide potential customers of the merchants with free product information.

Abstract: The present invention relates to a method for addressing the memory locations of a memory card. There are several memory locations in a memory card for storing data, in which case in order to address a specific memory location an address is formed. At least one parameter is stored in the memory card, on the basis of which parameter the number of memory locations of a memory card can be calculated, and a specific number of bits is reserved for said at least one parameter. In the method, two or more memory locations are addressed with one address, and/or the number of bits that can be used in an address is increased. The invention also relates to a system and a memory card in which the method is applied.

Abstract: A data processor includes the normal mode providing narrow access space of CPU and the advance mode providing wide access space. Even in the normal mode, the transfer control section assures data transfer control exceeding the address range for access from CPU. Even when programs are generated exceeding the limit of program capacity for the access range of CPU in the normal mode, if the programs exceeding such limit are stored in the non-access area of ROM 6 in the normal mode, the transfer control section accesses such programs and transfers these programs to RAM. Thereby CPU in the normal mode can use such programs transferred to RAM by making access thereto. Accordingly, limit of program capacity can be alleviated, while maintaining good program execution efficiency in the rather small access space of CPU in the data processor.

Abstract: A method and apparatus for loading comparand data into a content addressable memory system. For one embodiment, the CAM system includes a CAM array, a comparand register and select logic. The CAM array includes a plurality of rows of CAM cells each segmented into a plurality of row segments each having a plurality of CAM cells. The comparand register includes a plurality of segments for storing comparand data for comparing with data stored in the CAM array. The select logic selectively enables each segment of the comparand register to store a portion of the comparand data in response to configuration information. The configuration information is indicative of the width and depth of the CAM array. The select logic may also enable each segment of the comparand register to simultaneously load the comparand data.

Abstract: A CAM system having intra-row configurability. For one embodiment, the CAM system includes a CAM array having a number of rows of CAM cells each segmented into row segments. Each row segment includes a number of CAM cells coupled to a corresponding match line segment. Individual row segments or groups of row segments are uniquely addressable by address logic in response to configuration information that indicates a width and depth configuration of the CAM array. The configuration information may be stored in a configuration register. Data may be communicated with an addressed row segment or group of row segments using data access circuitry. Priority encoding circuitry may be included to generate the address of a row segment or group of row segments that stores data matching comparand data in response to the configuration information.

Abstract: A method and apparatus for detecting a match in an intra-row configurable CAM system. For one embodiment, the CAM system includes a CAM array and match flag logic. The CAM array includes a plurality of rows of CAM cells each segmented into a plurality of row segments having a plurality of CAM cells coupled to a corresponding match line segment. The match flag logic is coupled to the match line segments and determines when first comparand data matches data stored in at least one of the row segments in response to first configuration information, and determines when second comparand data matches data stored in at least one group of row segments in response to second configuration information. The first configuration information is indicative of a first width and depth configuration of the CAM array, and the second configuration information is indicative of a second width and depth configuration of the CAM array.

Abstract: A method and apparatus for determining a match address in an intra-row configurable CAM system. For one embodiment, the CAM system includes a CAM array and priority encoding circuitry. The CAM system includes a plurality of rows of CAM cells each segmented into a plurality of row segments having a plurality of CAM cells coupled to a corresponding match line segment. The priority encoding circuitry is coupled to the match line segments and has inputs to receive configuration information indicative of a width and depth configuration of the CAM array. The priority encoding circuitry is configured to generate a first match address in the CAM array corresponding to a row segment that stores data matching first comparand data in response to first configuration information, and is further configured to generate a second match address in the CAM array corresponding to a group of row segments that store data matching second comparand data in response to the second configuration information.

Abstract: The present invention is based on the finding that free CPU operation code identifiers of a CPU or CPU operation code identifiers useable for any reason can be used to control supporting means upstream of the CPU, which is able to form, responsive to these operation code identifiers, a new, for example, physical address in relation to a second memory area having a second memory which is larger than the, for example, logic memory size addressable by the CPU. By means of the special operation code identifiers, it is thus possible in the course of an executable machine code to address the supporting means which monitors the data traffic via which the operation codes to be processed or the operation code identifiers are provided to the CPU, from the memory to the CPU, and which can take measures in relation to the new formed address when certain special operation code identifiers occur.

Abstract: A method for increasing the internal memory in a processor. The method includes providing an extended memory in the processor, adding bits to data addresses and register addresses with an address extender, and adding bits to stack addresses with a stack pointer generator so that the processor is capable of accessing memory addresses larger than the bit width of the command set of the processor. The method also includes carrying over the bits when the stack address exceeds the limit of the conventional memory and accessing the stack data exceeding the limit of the conventional memory in the extended memory.

Abstract: A memory address decoding method for determining if a given address is located in one of a plurality of sections. Each section has a plurality of memory units and each memory unit has a unique corresponding address, the corresponding address using the binary system. The method includes making the corresponding address in a section with greater size smaller than the corresponding address in a section with smaller size, bbuilding asingle bit-pattern for each section from all corresponding addresses, and comparing if at least one comparative bit of the given address matches those in any of the bit-patterns so as to determine the given address is located in one of the sections based on the comparison.

Abstract: Presented herein are systems and methods for two address map for transactions between an X-bit processor and a Y-bit wide memory. A processor subsystem comprises a first address space, a second address space, and a bridge. The first address space stores data words of a first length. The second address space stores data words of a second length. The bridge performs one transaction after receiving a transaction with an address corresponding to the first address space and performs two transactions after receiving a transaction with the address corresponding to the second address space.

Abstract: There is provided a data processing apparatus capable of increasing a number of general purpose registers while maintaining upper compatibility. Register designating information for designating a register is divided in two portions. The two portions are arranged in separate basic units on the basic units of an instruction code. When one instruction code is made ignorable and the ignorable instruction code is ignored, a control unit (CONT) executes register selecting operation by implicitly assuming predetermined register designating information. Thereby, when only a general purpose register (existing general purpose register) capable of being designated implicitly is used, the ignorable instruction code can be ignored and accordingly, the instruction codes are not increased. When an at least conventionally equivalent general purpose register is used, a conventionally equivalent instruction code may be used. By preventing the instruction codes from increasing, processing speed is not reduced.

Abstract: A processor supports instruction pointer (IP) relative addressing in at least one operating mode of the processor. For example, in some implementations, IP relative addressing is supported in an operating mode or modes in which the address size is greater than 32 bits (e.g. up to 64 bits). In some embodiments, the displacement may be limited to less than the address size (e.g. 32 bits, in one implementation) when such operating modes are active. Code density may be higher than if the displacements were expanded, and flexibility in the placement of variables in memory may be achieved. For example, static variables may be placed in memory with flexibility, and IP relative addressing may be used to locate the static variables.

Abstract: A dual mode memory interface includes a bus switch and a register/buffer operatively coupled to the bus switch. The dual mode memory interface may include, operatively coupled to the bus switch and the register/buffer, enable/disable pins configured so that only one of the bus switch and the register/buffer is active at a time. The bus switch may be a transistor configured as a pass gate. The dual mode memory interface may be implemented in a single integrated circuit package. The dual mode memory interface may further include a system controller for detecting a type of memory module connected to the dual mode memory interface and enabling one of the bus switch and register/buffer based on the type of memory module detected.

Abstract: A semiconductor device with adjustable number of pages and page depth is disclosed. The semiconductor device includes multiple memory cell array blocks, a page control circuit for generating a control signal which varies the number of pages and the page depth in response to a page control signal, and a sense amplifying and write driving circuit. The page control circuit controls a row address and a column address to generate the control signal, that is, to vary the number of pages and the page depth. The sense amplifying and write driving circuit senses, amplifies and outputs data from a memory cell array block, and writes data into a memory cell array block in response to the control signal. The page control circuit includes an address buffer, a block controller and a control signal generator. The address buffer buffers the most significant bit (MSB) of the row address and outputs the buffered result, or ignores the MSB depending on the page control signal.

Abstract: The present invention provides an 8-bit microcontroller capable of supporting expanded addressing capability in one of three address modes. The microcontroller operates in either the traditional 16-bit address mode, a 24-bit paged address mode or in a 24-bit contiguous address mode based on the setting of a new Address Control (ACON) Special Function Register (SFR). The 24-bit paged address mode is binary code compliant with traditional compilers for the standard 16-bit address range, but allows for up to 16M bytes of program memory and 16M bytes of data memory to be supported via a new Address Page (AP) SFR, a new first extended data pointer (DPX) SFR and a new second extended data pointer (DPX1) register. The 24-bit contiguous mode requires a 24-bit address compiler that supports contiguous program flow over the entire 24-bit address range via the addition of an operand and/or cycles to either basic instructions.

Abstract: A memory including a plurality of memory cells combined into multiple physical sectors, in which the memory cells combined into one physical sector are capable of being erased only together, and in which the interface includes interrogation apparatus, arrangement, and structure that interrogates memory data encompassing sector data, and an allocation apparatus, arrangement, and structure that, incorporating the sector data, allocates multiple memory cells to each logical block, and in which allocation of the memory cells to the respective logical blocks is performed based on application-specific and/or memory-specific block data conveyed to the interface, which are represented by block information data that can be modified independently of data that constitute a program code. A method for providing variable configuration of a memory apparatus that includes at least one memory, and an apparatus for carrying out that method.

Abstract: A FIFO memory device for use in data transfer between data processing apparatuses having different data bus widths, has an input circuit 11 with a data bus width of k bits, an output circuit 12 with a data bus width of N×k bits (where N>1) that outputs data within the FIFO memory device, a writing pointer 2 that points to a data writing address of the FIFO memory device, a reading pointer 4 that points to a data reading address of the FIFO memory device, and a valid/invalid indicating circuit 6 that indicates whether or not data output to the output circuit 12 is valid.

Abstract: Method for producing a predetermined length page memory pointer record, according to a selected page size and a selected page address, the method including the procedures of: determining a dynamic location of a separator bit within the page memory pointer record, according to the selected page size and an initial page size, the initial page size being respective of the smallest page size in a given memory system, writing a predetermined value to the dynamic location, writing a sequence of values opposite to the predetermined value to selected page size bits of the page memory pointer record, when the selected page size is different than the initial page size, and writing the selected page address to selected page address bits of the page memory pointer record.

Abstract: A semiconductor device is disclosed that has a plurality of I/O pins that are configurable to selectively output three sets of signals selected from the group consisting of (i) a read enable signal and a write enable signal, (ii) a combined read and write enable signal, (iii) a read enable signal and a pair of byte write enable signals, and (iv) a row address strobe signal, and a column address strobe signal.

Abstract: A method for associating with a first address a second address of reduced size, comprising: calculating a first intermediary address by the first address, the first intermediary address having a reduced size with respect to the first address; then choosing as a second address the first intermediary address if this second address is not associated with another first address, or, otherwise, calculating a second intermediary address by a first polynomial division of the first address, the second intermediary address having a reduced size as compared to the first address; then choosing as a second address the second intermediary address.

Abstract: A processing system supports memory access based on distinct memory space access instructions as well as universal access instructions that are independent of memory space partitions. Conventional memory-space dependent instructions, such as MOV, MOVX, and MOVC, provide an optimized addressing scheme, and an extended memory-space independent instruction EMOV provides an optimized code efficiency, processing speed, and ease of code generation. A mapping between the discrete memory space partitions and a “universal” memory space allocation is provided. The processing hardware interprets the universal address to determine the corresponding memory space, and provides the access to an address within that memory space.

Abstract: A method for asserting an address alignment of an address for a memory-mapped device in a logic design is disclosed. An align primitive comprising an alignment size port, an input address port and an output address port is used. The alignment size port has data indicating a desired address boundary. The input address port is used for an address to be verified against the desired address boundary. The output address port is used to provide an address that is on the desired address boundary. The address to be verified against the desired address boundary is provided at the output address port when that address meets the desired address boundary. Another method for specifying an offset address for a memory-mapped device in a logic design is disclosed. An offset primitive is used to assert an address for the memory-mapped device. The offset primitive comprises an incoming address port, an outgoing address port and an offset value port. The offset value port has a data value indicating a desired address offset.

Abstract: Method for producing a predetermined length page memory pointer record, according to a selected page size and a selected page address, the method including the procedures of: determining a dynamic location of a separator bit within the page memory pointer record, according to the selected page size and an initial page size, the initial page size being respective of the smallest page size in a given memory system, writing a predetermined value to the dynamic location, writing a sequence of values opposite to the predetermined value to selected page size bits of the page memory pointer record, when the selected page size is different than the initial page size, and writing the selected page address to selected page address bits of the page memory pointer record.

Abstract: The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two ×16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these ×16 memories, the full address is provided. If the address is within the two columns of the second ×16 memory, the full address is also provided to the second ×16 memory. If the address is to the first of the ×16 memories, the second ×16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte.

Abstract: A memory controller provides programmable flexibility, via one or more configuration registers, for the configuration of the memory. The memory may be optimized for a given application by programming the configuration registers. For example, in one embodiment, the portion of the address of a memory transaction used to select a storage location for access in response to the memory transaction may be programmable. In an implementation designed for DRAM, a first portion may be programmably selected to form the row address and a second portion may be programmable selected to form the column address. Additional embodiments may further include programmable selection of the portion of the address used to select a bank. Still further, interleave modes among memory sections assigned to different chip selects and among two or more channels to memory may be programmable, in some implementations.

Abstract: A soft cache system compares tag bits of a virtual address with tag fields of a plurality of soft cache register entries, each entry associated with an index to a corresponding cache line in virtual memory. A cache line size for the cache line is programmable. When the tag bits of the virtual address match the tag field of one of the soft cache entries, the index from that entry is selected for generating a physical address. The physical address is generated using the selected index as an offset to a corresponding soft cache space in memory.

Abstract: An apparatus comprising one or more memory blocks in a programmable logic device. The memory blocks may be configured as content-addressable memory having arbitrarily adjustable tag and data widths.

Abstract: Updating a content addressable memory (CAM) involves identifying a new entry that is to be added to the CAM, identifying a free location in the CAM that is the fewest number of prefix levels away from the prefix level of the new entry, moving an existing CAM entry into the free location to create a newly freed location that is a fewer number of prefix levels away from the prefix level of the new entry, repeating the move process until a free location is created at the desired prefix level of the new entry, and then adding the new entry into the newly freed location. The specific algorithm for moving entries to free a location in the desired prefix level is a function of whether the prefix level of the first free location is above or below the prefix level of the new entry.

Abstract: A method for controlling access to at least one external cache memory in a processing system, the at least one external cache memory having a number of lines of data and a number of bytes per line of data, the method includes determining a smallest cache memory size for use in the at least one external cache memory, and configuring a tag array of the at least one external cache memory to support the smallest determined cache memory size. A system for controlling access to at least one external cache memory in a processing system, the at least one external cache memory having a number of lines of data and a number of bytes per line of data, includes a circuit for configuring each tag field of a plurality of tag fields in a tag array in the at least one external cache memory to have a number of bits sufficient to support a smallest determined cache memory, and utilizing each tag field to determine whether data being accessed resides in the at least one external cache memory.

Abstract: The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two x16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these x16 memories, the full address is provided. If the address is within the two columns of the second x16 memory; the full address is also provided to the second x16 memory. If the address is to the first of the x16 memories, the second x16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte.

Abstract: A processor supports a processing mode in which the default address size is greater than 32 bits and the default operand size is 32 bits. The default address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the processing mode. The processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Additionally, an instruction prefix may be coded into an instruction to override the default address and/or operand size. Thus, an address size of 32 bits may be used when desired, and an operand size of 64 bits may be used when desired.

Abstract: A memory for searching information through prefix analysis, in particular for building routing tables for nodes of high speed communication networks, such as Internet network, has a memory element which stores a set of information items each associated with a mask information indicative of the number of significant characters in the respective prefix and with a target information. For the implementation of a search criterion based on the longest prefix match, each cell comprises an information field that provides either an address of a next row for the continuation of a search or an information relating to a target reached, and a pair of flags (GO, TARGET) specifying the contents of the information field.

Abstract: An information processing apparatus has a DRAM for storing at least predetermined data, a system bus to which the DRAM is connected, a CPU for controlling the DRAM, and a CPU bus to which the CPU is connected. The information processing apparatus also has an SRAM connected to the system bus and the CPU bus, for storing data transferred from the DRAM, an address counter for generating an address of the SRAM based on an initial value, and a DMA controller for controlling data transfer between the DRAM and the SRAM using the address generated by the address counter. At a certain time, the DMA controller outputs an address D2 next to an initial address in the DRAM via the system bus to the DRAM, reads data B from the address D2, and outputs the data B via the system bus to the SRAM. At the same time, the address counter increments a stored address S1 into an address S2, and outputs the address S2 to the SRAM, which stores the data B at the address S2.

Abstract: A microprocessor capable of functioning in an expanded address mode is disclosed, including: a control unit for determining whether an external instruction is to be used for a normal address mode or to be used for an expanded address mode and for generating control signals; a program counter for generating a first address in response to an output from the control unit during the normal and expanded address modes; an address generator for generating a second address during the expanded address mode, in response to an output from the control unit; an address bus for transferring the first address out of the microprocessor; and a data bus for transferring the second address out of the microprocessor. The microprocessor also includes an address interface circuit for transferring the second address out of the microprocessor through the data bus.

Abstract: A processor supports an operating mode in which the default address size is greater than 32 bits and the default operand size is 32 bits. The default address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the operating mode. The operating mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Additionally, a first instruction prefix may be coded into an instruction to override the default operand size to a first non-default operand size (e.g. 64 bits). Furthermore, a second instruction prefix may be coded into an instruction in addition to the first instruction prefix to override the default operand size to a second non-default operand size (e.g. 16 bits).

Abstract: A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.

Abstract: An instruction decode unit is described including circuitry coupled to receive an instruction. The instruction identifies multiple operands, one of which is a destination operand. The circuitry responds to the instruction by producing: (i) operand codes specifying the operands, wherein the operand codes are produced in the order in which the operands are identified within the instruction, and (ii) a destination operand signal identifying the destination operand. In one embodiment, the decode unit responds to the instruction by producing the operand codes, operand address information, control signals, and the destination operand signal. A processor including the instruction decode unit is also described, as is a computer system including the processor. The instruction may include operand information which identifies the operands. The instruction may also include destination operand information which indicates which of the operands is the destination operand.

Abstract: A first-in-first-out (FIFO) memory device includes a plurality of FIFO memory cores that contain a plurality of cells. A variable cell size circuit supports user programmable cell sizes in a FIFO memory device to permit selection of a wide range of cell sizes. The variable cell size circuit controls successive accesses to a cell in the memory device, and it resets a byte count when the byte; count equals the cell size value to initialize the circuit for a subsequent access operation. The variable cell size circuit further includes a prediction circuit that indicates completion of access to the cell a predetermined number of counts prior to completion of the actual access. An alignment circuit generates data for write operations in cells that store an odd number of bytes per cell to compensate for the two byte per cell read operations. Each FIFO memory core includes a circuit that generates a cell available signal to indicate whether a cell in a corresponding FIFO memory core is available for reading.

Abstract: A method and algorithm to handle a memory bank queue using a low processing power 8-bit microcontroller is provided. The microcontroller is used to receive information in the form of a data packet from a communication interface shared with an external system. Each received packet is temporarily stored in a logical FIFO queue while the first packet in the queue packet is processed, modified or decoded according to a process or algorithm made by the user. The result keeps the same queue position until a second system is able to receive it through a second communication interface. In the same manner, any information packet coming from the second system is queued and processed back to retrieve a result to the first processor. This invention provides a mechanism to maintain two or more logic queues sharing the same physical RAM, one for each kind of process related to packets flowing from one interface to another.

Abstract: A bit-parallel system and method for allocating storage space for data objects using a bitmap. It is determined whether a suffix of free space bits in a previous bitmap word can be used with a prefix of free space bits in a current word that is contiguous to the previous word. If so, this renders a string of free space bits spanning multiple words, and it is determined whether the string represents a sufficiently large number of contiguous blocks (“the target”) to store the data object. If not, it is determined whether sufficient contiguous free space bits in the current word exist to fulfill the target. If the target still can't be achieved, the longest suffix of free space bits in the current word is found for possible use with the prefix of the next contiguous word, and the next word is then retrieved and processed. The algorithm for finding the suffix preferably is undertaken by considering bits in parallel.

Abstract: A controller for executing instructions has one the order of five addressing modes and can allow executing of processes concurrently in multiple modes. A specific embodiment can effectively run legacy code written for the Z80 micoprocessor without requiring recompiling of code. An optional embodiment includes autonomous Multiply/Accumulator Engine (MAC) optimized to perform sum-of-products (SOP) operations with little controller overhead, making the invention capable of more effectively handling a number of processing tasks, particularly tasks related to digital signal processing (DSP).

Abstract: An apparatus and method for efficiently transferring a plurality of segmented data with various sizes. An address translation storage unit stores an address translation table which provides a plurality of translation descriptor domains to support a plurality of translation step sizes. Depending on the segment size of each data block to be transferred, a translation descriptor domain selection unit chooses a suitable translation descriptor domain within the address translation table. Data segment mapping is then performed with translation descriptors in the selected translation descriptor domain.

Abstract: A microprocessor configured to rapidly decode variable-length instructions is disclosed. The microprocessor is configured with a predecoder and an instruction cache. The predecoder is configured to expand variable-length instructions to create fixed-length instructions by padding instruction fields within each variable-length instruction with constants until each field reaches a predetermined maximum width. The fixed-width instructions are then stored within the instruction cache and output for execution when a corresponding requested address is received. The instruction cache may store both variable- and fixed-width instructions, or just fixed-width instructions. An array of pointers may be used to access particular fixed-length instructions. The fixed-length instructions may be configured to all have the same fields and the same lengths, or they may be divided into groups, wherein instructions within each group have the same fields and the same lengths.

Abstract: A system and method for transparent handling of extended register states. A set of additional registers, or an extended register file, is added to the base architecture of a microprocessor. The extended register file includes two dedicated registers and a plurality of general-use registers. The extended register file is mapped to a region in main memory. One dedicated register of the extended register file stores the physical base address of the memory region. Another dedicated register of the extended register file is used to store bits to indicate the status of the extended register file. A set of extended instructions is implemented for transferring data to and from the extended register file.

Abstract: The current disclosure concerns dynamic variable page size translation of addresses. Such translation can be achieved at higher clock speeds than have heretofore been possible due to the use of a translation lookaside buffer (TLB) with RAM cells which eliminate the need to utilize circuitry external to the TLB. Such translation can also be bypassed at higher speeds than have heretofore been possible due to the use of translation bypass circuitry which eliminates the need to utilize circuitry external to the TLB.

Abstract: A cache with a translation lookaside buffer (TLB) that reduces the time required for retrieval of a physical address from the TLB when accessing the cache in a system that supports variable page sizing. The TLB includes a content addressable memory (CAM) containing the virtual page numbers corresponding to pages in the cache and a random access memory (RAM) storing the physical page numbers of the pages corresponding to the virtual page numbers in the CAM. The physical page number RAM stores a page mask along with the physical page numbers, and includes local multiplexers which perform virtual address bypassing of the physical page number when the page has been masked.

Abstract: When a decision circuit (217) incorporated in a control circuit (21) in an instruction decode unit (2) in a microprocessor (1) decides that an integer operation unit (4) can not execute a following sub instruction, the decision circuit (217) controls each of selectors (211, 214, and 215) and an exchange circuit (216) so that a memory access unit (3) that has already executed a preceding sub instruction can execute the following sub instruction.