Abstract: A method of operating a processor (30). The method comprises a first step of fetching an instruction (20). The instruction includes an instruction opcode, a first data operand bit group corresponding to a first data operand (D1′), and a second data operand bit group corresponding to a second data operand (D2′). At least one of the first data operand and the second data operand consists of an integer number N bits (e.g., N=32). The instruction also comprises at least one immediate bit manipulation operand consisting of an integer number M bits, wherein 2M is less than the integer number N. The method further includes a second step of executing the instruction, comprising the step of manipulating a number of bits of one of the first data operand and the second data operand. Finally, the number of manipulated bits is in response to the at least one immediate bit manipulation operand, and the manipulating step is further in response to the instruction opcode.

Abstract: An integrated circuit includes a first and second memory, with the first memory being configurable between a first data format and a second data format. An external address bus is connected to the second memory, and an internal bus is connected to the first memory. A rerouting circuit is connected between the external address bus and the internal bus. The rerouting circuit forms one of two connections between the external address bus and the internal bus dependent upon the configuration of the first memory.

Abstract: A tag RAM is coupled to an address bus that is adapted to carry a variable width address field. The tag RAM includes a memory section coupled to the address bus and a comparator coupled to the address bus and the memory section. The tag RAM further includes a selection module coupled to the address bus and coupled to the comparator. The selection module selects one or more bits of the address field as tag field bits depending on the width of the address field and the size of the cache memory coupled to the tag RAM.

Abstract: The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. Furthermore, additional aspects of the invention are realized by having instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. Thus, multiple operations are performed during each clock cycle, reducing the total number of clock cycles necessary to perform a task. The exemplary DSP includes a set of three data buses over which data may be exchanged with a register bank and three data memories.

Abstract: A method and system for performing write-through store operations of valid data of varying sizes in a data processing system, where the data processing system includes multiple processors that are coupled to an interconnect through a memory hierarchy, where the memory hierarchy includes multiple levels of cache, where at least one lower level of cache of the multiple of levels of cache requires store operations of all valid data of at least a predetermined size. First, it is determined whether or not a write-through store operation is a cache hit in a higher level of cache of the multiple levels of cache. In response to a determination that cache hit has occurred in the higher level of cache, the write-through store operation is merged with data read from the higher level of cache to provide a merged write-through operation of all valid data of at least the predetermined size to a lower level of cache.

Abstract: An integral modular cache. One embodiment includes a processor portion and a cache memory portion. The cache memory portion includes an array portion having tag logic and a set portion. The array portion extends along substantially all of a first axis of the processor. Control logic is to receive a cache size indicator and is capable of operating the cache with the one set portion or with additional set portions.

Abstract: A high-speed linear address generator (LAGEN) and method for generating a linear address are disclosed, which generator is operable to generate a linear address very quickly. In a preferred embodiment, the LAGEN has a parallel design, rather than a serial design, which allows the LAGEN to generate a linear address substantially faster than 1 nanosecond after receiving input operands. The LAGEN generates a linear address within a single clock cycle of a clock operating at 1 gigahertz (GHz). The LAGEN receives three 32-bit operands IMM[31:0], SRC1[31:0], and SRC2[31:0], and compresses them into two 32-bit operands. The LAGEN then sums the two operands producing a 32-bit result res[32:0]. The LAGEN allows for both 32-bit mode operation and 16-bit mode operation. In either mode of operation the lower 16 bits of the result, res[15:0], are output for the lower 16 bits of the generated linear address.

Abstract: A tag array retains a plurality of tag data, and performs matching of the tag data with a retrieval keyword. The tag array includes matching circuits provided corresponding to the tag data. Each of the matching circuits has CM and CC cells provided corresponding to a plurality of bits of the corresponding tag data. Each CM cell retains a corresponding bit of the tag data, and performs matching of the retaining bit with a corresponding bit of the retrieval keyword. Each CC cell, not only functions as the CM cell, but also retains a comparison condition signal input in advance, and invalidates, according to the comparison condition signal, the mismatch detected between corresponding bits of the tag data and the retrieval keyword. As a result, it becomes possible to variably set the number of bits, of an input retrieval keyword, being matched with the tag data.

Abstract: Logical addresses start from different base addresses for respective numbers of bits of data making up words. One physical address in a main memory corresponds to a plurality of logical addresses, and an address converter has an association table of physical and logical addresses. The address converter decides which base address an entered logical address belongs to for thereby determining the number of bits of data of one word, and determines a physical address so as to be able to read words corresponding to the number of bits from the main memory. Words made up of different numbers of bits can quickly be converted from logical addresses into physical addresses.

Abstract: There is disclosed DTLB in a microprocessor of the present invention, comprising an adder for adding a base address and a sign-extended offset address; a comparator for judging whether or not upper side 20 bits [31:12] of the base address match the base address stored in a upper side address storage section in CAM 35, and upper side 4 bits [15:12] of the offset address match the offset address stored in the CAM; a comparator for judging whether or not a carry signal outputted from the adder and a carry signal stored in a carry storage section in the CAM are matched; and a match detector for outputting a match signal when comparison results of the comparators are matched. With lower side 12 bits of the virtual address, the judgment of match/mismatch is performed only with the carry signal. Therefore, the match/mismatch of the virtual address can be judged before the addition processing in the adder is completed.

Abstract: A physically non-distributed microprocessor-based computer includes a microprocessor, and a random access memory device, a mass storage device, and an input-output port device, all operable from the microprocessor and including an interface for receiving and transmitting data in packet form. A novel packet-based data channel extends between the microprocessor and the interfaces of the devices to provide communication between the microprocessor and the devices. By varying the blank size of the cache in accordance with actual data transmission requirements improved computer performance is achieved.

Abstract: A method and apparatus for accessing successive memory locations without the need for multiple index register writes and without the need for a wide address bus from the controller into a memory control system. The memory control system includes an index register and a data register. The index register has a connection to the controller and the buffer. The data storage register has a connection to the buffer and to the controller. The index register receives an address to a location in the buffer. Each time the contents of the index register are changed, data associated with the address are automatically written into the data storage register. Each time the data storage register is accessed (read or written), the index register in incremented. The controller is able to read or write unlimited numbers of sequential locations up to the full buffer space, using only a single controller access per byte.

Abstract: A data management method is first used for registering the plurality of entry data having n-bit length and performing match retrieval by masking a (n−m(i)) bit from the least significant bit side, whereby to detect the value of an m(i) bit from the side of the most significant bit matching a specific entry data. Then match retrieval is performed repeatedly by shifting a bit to be masked by an m(i+1) bit each time toward the low order side and detecting a corresponding value of m(i+1) bit until no bit to be masked exists so as to detect the value of an n bit matching the entry data. Further, an entry address at which the specific entry data matching the value of the n bit thus detected has been registered is obtained in order that a new entry data is registered at the entry address. A data management apparatus has a control circuit for controlling the operation of the associative memory in accordance with the data management method according to the present invention.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single part memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: A processor architecture and associated method improve efficiency of memory accesses and thereby reduces power consumption. New addressing modes reduce most instructions to one or two bytes in length, including immediate addressing of 32-bit addresses. A full instruction set provides complete arithmetic and logical operations using index registers and accumulator while minimizing external memory access.

Abstract: A data carrier (1) for the communication of transmission information (UI) to communication station (2), including program memory means (9) for the storage of a program code (PC) including instruction information (II) and associated address information (AI) in at least one program code line (PCZ), and including data memory means (10) for the storage of data information (DI) and including computing means (8) for the execution of the stored program code (PC) in order to process the communicated transmission information (UI), where for each program code line (PCZ) address mode information (AAI) included in the instruction information (II) and the associated address information (AI) can be determined and can be processed in order to access a memory location of the program memory means (9) or the data memory means (10), now includes address mode extension means (12), which in the presence of specific address information (AI) are adapted to determine stored additional address mode information (ZAAI) which identifies

Abstract: A data buffer apparatus stores first data objects containing a plurality of first data items and second data objects containing one or more second data items in a number of different ways depending upon a mode of operation. The apparatus includes an encoder (1290) for rearranging the order of the first data items within the first data objects in accordance with first arranging mode, prior to storing in the buffer (1293). The apparatus also includes a decoder (1291) for rearranging the order of a plurality first data items read from the buffer, in accordance with a second arranging mode.

Abstract: A method and apparatus for prefetching superblocks in a computer processing system having a fetch mechanism for fetching instructions for execution includes the step of controlling the fetch mechanism to begin fetching at a starting address of a current superblock. A superblock includes a set of instructions in consecutive address locations terminated by a branch instruction known to have been taken. A Superblock Target Buffer (STB) is supplied with the starting address of the current superblock. The STB has a plurality of entries each indexed by a starting address of a superblock and including a run length of the superblock and a target address of the terminating branch of the superblock. The run length corresponds to the sum of a length of the terminating branch and the difference between a starting address of the terminating branch of the superblock and the starting address of the superblock.

Abstract: A method and apparatus for supporting multiple overlapping address spaces on a shared bus includes both an address comparator and an address size indicator. The address comparator compares an address, corresponding to a request to be issued on the bus, to a plurality of address spaces. The address size indicator indicates a first address space of the plurality of address spaces to which the address corresponds.

Abstract: A processor of a mainframe host is provided with a variable length/fixed length format conversion function, and furthermore, provided with a function capable of connecting with a disk array provided outside a frame of the mainframe host by a fixed length interface. As a result, data to which the mainframe host, a UNIX server, and a PC server separately access can be commonly stored into the disk array equipped with the fixed length format interface. An interface for connecting a mainframe unit to an open system, is made identical to another interface for connecting a disk array which commonly stores thereinto data accessed by, for example, a UNIX server and a PC server, to both the mainframe host and the open system. As a result, a management step number of the computer system can be reduced, and the computer system can be easily utilized.

Abstract: A tag RAM is coupled to an address bus that is adapted to carry a variable width address field. The tag RAM includes a memory section coupled to the address bus and a comparator coupled to the address bus and the memory section. The tag RAM further includes a selection module coupled to the address bus and coupled to the comparator. The selection module selects one or more bits of the address field as tag field bits depending on the width of the address field and the size of the cache memory coupled to the tag RAM.

Abstract: A first-in-first-out (FIFO) memory device includes a plurality of FIFO memory cores that contain a plurality of cells. A variable cell size circuit supports user programmable cell sizes in a FIFO memory device to permit selection of a wide range of cell sizes. The variable cell size circuit controls successive accesses to a cell in the memory device, and it resets a byte count when the byte: count equals the cell size value to initialize the circuit for a subsequent access operation. The variable cell size circuit further includes a prediction circuit that indicates completion of access to the cell a predetermined number of counts prior to completion of the actual access. An alignment circuit generates data for write operations in cells that store an odd number of bytes per cell to compensate for the two byte per cell read operations. Each FIFO memory core includes a circuit that generates a cell available signal to indicate whether a cell in a corresponding FIFO memory core is available for reading.

Abstract: The invention provides a volatile or non-volatile memory and a latching circuit wherein data held in a first memory location is used to address the next memory location, in addition to providing a synchronous portion of the code. Accordingly, the data at the next memory address is used as a succeeding address and a subsequent portion of the code. The data is organized to repeat when the data stored in the address location is equal to the starting address.

Abstract: A ternary content addressable memory is employed to perform a longest prefix match search. Each CAM cell within the ternary CAM has an associated mask cell so that the CAM cells may be individually masked so as to effectively store either a logic 0, a logic 1, or a don't care for compare operations. For example, Classless Inter-Domain Routing (CIDR) addresses are pre-sorted and loaded into the ternary CAM such that the CAM entry having the longest prefix is located at the lowest numerical address or index of the ternary CAM, and the CAM entry with the shortest prefix is located at the highest numerical address or index. The prefix portions of the CIDR addresses are used to set the mask cells associated with each CAM entry such that during compare operations, only the unmasked prefix portion of each CAM entry is compared to an incoming destination address stored as the CAM search key.

Abstract: A first-in-first-out (FIFO) memory device includes a plurality of FIFO memory cores that contain a plurality of cells. A variable cell size circuit supports user programmable cell sizes in a FIFO memory device to permit selection of a wide range of cell sizes. The variable cell size circuit controls successive accesses to a cell in the memory device, and it resets a byte count when the byte count equals the cell size value to initialize the circuit for a subsequent access operation. The variable cell size circuit further includes a prediction circuit that indicates completion of access to the cell a predetermined number of counts prior to completion of the actual access. An alignment circuit generates data for write operations in cells that store an odd number of bytes per cell to compensate for the two byte per cell read operations. Each FIFO memory core includes a circuit that generates a cell available signal to indicate whether a cell in a corresponding FIFO memory core is available for reading.

Abstract: In one embodiment, there is a single integrated circuit microprocessor (10). The microprocessor has an instruction pipeline (12) which comprises an execution stage (12a) operable to process an information unit of a first length. The microprocessor further includes a cache circuit (20) comprising a memory (34) operable to store a transfer unit of information of a second length and accessible by the instruction pipeline. The second length corresponding to the capability of the cache circuit is greater than the first length corresponding to the execution stage operability. Lastly, the microprocessor includes a block move circuit (24) coupled to the cache circuit and operable to read/write a transfer unit of information of the first length into the memory of the cache circuit.

Abstract: A method and apparatus for extending an on-chip processing device's access to memory are accomplished by depositing a processing circuit, memory, and configuration circuitry on a die. When the memory has sufficient digital storage capabilities for the processing circuit, the configuration circuitry directly couples an address bus and data bus between the memory and the processing device. When the memory does not have sufficient digital storage capabilities for the processing circuit, the configuration circuitry reconfigures the memory. In additional, the configuration circuitry extends the address bus to an external memory and combines the internal data bus with an external data bus. Configured in this manner, the processing device can access both the on-chip memory and the external memory as a single addressable memory, thereby increasing the memory available to the processing circuit.

Abstract: An address translation unit for supporting multiple page modes, with each page mode having a different page size.

Abstract: A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.

Abstract: A computing apparatus has a mode selector configured to select one of a long-bus mode corresponding to a first memory size and a short-bus mode corresponding to a second memory size which is less than the first memory size. An address bus of the computing apparatus is configured to transmit an address consisting of address bits defining the first memory size and a subset of the address bits defining the second memory size. The address bus has N communication lines each configured to transmit one of a first number of bits of the address bits defining the first memory size in the long-bus mode and M of the N communication lines each configured to transmit one of a second number of bits of the address bits defining the second memory size in the short-bus mode, where M is less than N.

Abstract: A method and apparatus for storing a variable length operand offset in a computer instruction is provided. An operand base is stored in a computer instruction. Also stored in the computer instruction is a variable length operand offset that is associated with the operand base. In addition, an operand offset length is stored within the computer instruction that defines the length of the variable length operand offset. Storing an operand offset length with each variable length operand offset in a computer instruction provides for the reduction of unused space.

Abstract: An address generator for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a lock size by a logical block number, to obtain the start address for a memory array read or write operation. The dedicated multiplier circuit advantageously provides very quick computation of these relatively large numbers, which typically involves a 32 bit by 16 bit multiplication. The multiplier includes a shift register initially holding the logical block number which is shifted a particular number of times, the number of shift pulses representing a value of the block length. The output of the shift register is the desired address.

Abstract: A technique for conserving digital memory space is disclosed. This technique includes sequentially transmitting a first address and a second address on a first bus coupled to a FIFO memory. The first address is stored in the memory and compared to the second address to determine a first value corresponding to a difference between the first and second addresses. This first value is written in the memory to represent the second address and has a bit size smaller than the second address. A method to decode the first value to regenerate the second address is also disclosed. These techniques may be further enhanced by only storing an address in a sequential access memory when it differs from the most recently stored address in the memory.

Abstract: A computer system with a multiplexed address bus that is shared by both system memory and by slave devices is described. The slave devices are incorporated into an existing system memory configuration by providing a bus controller to execute a two-cycle address sequence on the multiplexed address bus. The address sequence is followed by a transfer of data. A random latency can exist between the time of receiving address information and the time of receiving data corresponding to the address information. This random latency can be exploited by the system CPU for other computational purposes. The bus controller of the system executes multiple, or pipelined, data writes to the bus before an acknowledgement for the first data write is received. In this scheme, the acknowledgement for the first data write is typically sent during the same time period that the subsequent data writes are being received. Consequently, data transfer acknowledgements overlap data writes.

Abstract: A method for providing a base address register in a computer system that allows the length of the base address portion of an address to be changed and thereby allows various sizes of address spaces to be supported by the same base address register. The method employs steps that enable and disable bits of the base address register to properly support the desired address space size. Some embodiments of the method set disabled bits of the base address register to a known value. An apparatus that employs the method includes a second register connected to the base address register to supply signals that enable and disable bits of the base address register appropriately.

Abstract: In a method and apparatus for addressing memory there is a procedure for providing a word with fixed width, having a fixed number of bits to be used for addressing variable width data, and having a width defining field and address field, is disclosed. In addition, a procedure for addressing memory with a fixed width word, having a fixed number of bits, to be used for addressing data and having a substitution field and an address field, is discussed.

Abstract: A system, method and computer program product for virtual memory support for TLBs with multiple page sizes that require only minor revisions to existing operating system code and remains compatible with existing applications. The virtual memory support provided herein is transparent to many existing operating system procedures and application programs. Various page sizes such as 4 KB, 64 KB, 256 KB, 1 MB, 4 MB and 16 MB page sizes can be used by application programs and each process can use multiple page sizes. Base page sized PTEs and data structures associated with physical pages (PFDATs) are maintained. Maintaining PFDATs and PTEs at a base page level facilitates upgrading and downgrading of memory pages. In addition, different processes can have different views of the same data. Support is provided for upgrading and downgrading memory pages. Examples of operating system methods that can be used for virtual memory support for multiple page sized TLBs are provided herein.

Abstract: The memory management system is operational in a database system and functions to gracefully transition data from the allocated memory space to run files on disk only as needed. The memory management system accommodates variable length input records in the workspace of a database sort operation, requires no extra copying of records in memory, and maintains memory utilization at a high level. This memory management system therefore minimizes the amount of data written to disk during run formation and enables the use of the replacement selection algorithm even with variable length input records, which improves performance of sorting and overall operational efficiency of the database system.

Abstract: Multiple format addressing is implemented in a microcontroller that has both ROM and RAM memory facility, processing facility, and bus facility for interconnecting the memory and processing facilities, through using a low address field for local addressing, and at least one facultative high address field for extended addressing. In particular, the high address field is provided in a first addressing format as a segment address, and in a second addressing format as containing a RAM/ROM selection bit. More in particular, the high address field can be provided in a third addressing format as containing a RAM/ROM selection bit and a segment address in respective mutually exclusive fields.

Abstract: A microprocessor is configured to execute a stride instruction. In response to the stride instruction, the microprocessor performs a series of load memory operations. The address corresponding to a particular load memory operation is the sum of a stride operand of the stride instruction and the address corresponding to another load memory operation immediately preceding the particular load memory operation in the series. A base address operand specifies the address of the first load memory operation in the series, and a repetition count operand specifies the number of load memory operations in the series. The cache lines corresponding to the series of load memory operations (i.e. the cache lines storing the bytes addressed by the load memory operations) are fetched into the data cache of the microprocessor in response to the series of load memory operations.

Abstract: A system and method of accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor. The system includes a plurality of external registers which are connected to the processor over a data bus, address translation means, connected to the processor over the data bus and an address bus, for calculating, based on an index written to the data bus, an address associated with one of the memory locations, and transfer means, connected to the plurality of external registers, for transferring data between the addressed memory location and one of the external registers.

Abstract: A microcontroller is presented including additional hardware which generates multiple auxiliary address signals needed to expand the memory address space of the microcontroller. The auxiliary address signals allow access to memory locations within external memory devices which would not otherwise be accessible while advantageously maintaining software compatibility with previous microcontroller products. The auxiliary address signals form the most significant bits of augmented addresses, thereby dividing memory locations within the external memory devices into multiple memory banks of equal size. When memory banking is enabled, software instructions select the desired memory bank by writing appropriate values to address bit positions within a memory banking control (MBC) register. The auxiliary address signals are normally produced having values stored within corresponding bit positions of the MBC register.

Abstract: Apparatus, methods and computer program products are disclosed that enable a compiler to generate efficient code to access stack registers on a register stack. The invention operates by transforming a three-operand instruction, within a compiler's intermediate representation, to one or more fewer-than-three-operand instructions. The invention also transforms the instruction's operand addressing from an access to a pseudo-named register to an access to a stack register through stack offset into a register stack. The invention also determines the register stack state at each instruction responsive to register stack permutations and maps the stack offset accordingly for each subsequent access to a stack register.

Abstract: In order to allow an external memory space to enter into the memory space of a microprocessor (43) comprising a cache memory (94), an integrated circuit (42) serves as an interface between the microprocessor (43) and a memory unit (8, 9, 12) constituting the external memory space. The integrated circuit (42) comprises a stack (91) sized for containing a data block from the memory unit (8, 9, 12) such that the block from the memory unit (8, 9, 12) is seen as one or more blocks in the cache memory (94), and a register (93) belonging to the memory space of the microprocessor (43) adapted to contain the coordinates for access to the memory unit (8, 9, 12).

Abstract: Flat-model, 32-bit, real-mode execution may be obtained in an INTEL.TM. X86-compatible processor of a computer to increase address space, while handling interrupts transparently. A protected-mode operating system is not required. A LOADALL instruction available to an operating system may load hidden cache descriptor registers of a processor with the base addresses, segment limits, and other attributes consistent with 32-bit, real-mode operation to provide 32-bit addressing. Interrupts, would normally interfere with the contents of the hidden cache descriptor registers. A new interrupt vector table is provided, with each new vector therein pointing to one of the new interposer routines provided. Upon receipt of an interrupt, a new interrupt vector points to an interposer routine, which saves the state of the hidden cache descriptor registers.

Abstract: An apparatus including address generation units, corresponding reservation stations, and a speculative register file is provided. Decode units provide memory operation information to the corresponding reservation stations while the associated instructions are being decoded. The speculative register file stores speculative register values corresponding to previously decoded instructions. The speculative register values are generated prior to execution of the previously decoded instructions. If the register operands included in the address operands of an instruction are stored in the speculative register file, then the memory operation may be passed through the corresponding reservation station to an address generation unit. The address generation unit generates the data address from the address operands and accesses a data cache while register operands corresponding to the instruction are requested from a register file and reorder buffer.

Abstract: A memory management system is described which divides each virtual page into two or more sectors. Each of these sectors can then be individually loaded into memory in order to reduce bandwidth consumed loading virtual pages into a physical memory. A TLB for this system includes a plurality of TLB entries. Each TLB entry includes a variable physical page number (PPN FIELD) and a variable presence field. Each bit of the presence field indicates whether a corresponding sector is present in physical memory. The TLB entry also includes a page size field, which indicates the size of the corresponding virtual page. This size field also indirectly controls the number of sectors within that page and, thus, the number of presence bits required. As the page size grows the number of bits required to store the physical page number reduces. These unused bits are then consumed by additional presence bits so that all the bits in the TLB entry are used for all page sizes and number of sectors.

Abstract: A microprocessor includes an execution unit for processing a stream of instructions wherein one or more of the instructions reference the eight logical x86 general purpose registers as source and destination registers for operands for the instructions. The microprocessor further includes a register file with a plurality of physical registers in excess of the eight x86 general purpose registers. The physical registers in the register file are mapped to the logical x86 general purpose registers such that one of the physical registers may contain one or more logical source or destination registers of the x86 general purpose registers for an instruction. The register file drives the entire bits of the physical register which contains the destination register for the instruction onto an internal bus. The bits are stored in a latching circuit in the register file. The execution unit performs the instruction and returns the resulting operand to be stored in the logical destination register.

Abstract: A processor core for providing a linear extension of addressable memory space of a microprocessor with minimal additional hardware and software complexity. A N+x bit pointer register (e.g. program counter) holds an N+x bit instruction address. The N+x bit instruction address provides to an execution unit a pointer to an instruction in the memory to be processed by the execution unit. An encoder encodes the N+x bit address into an N bit encoding of the N+x bit address. The processor core can thereby address 2.sup.x times more memory locations than 2.sup.N. Two other registers each hold a portion of a data address (i.e. a pointer to a datum in memory to be operated on). An address former concatenates the portions of the address in the two registers to form the data address. Therefore, the address is formed from portions of the data address stored in multiple registers without performing any arithmetic on the portions.

Abstract: A computer system includes a number of storage elements encoded with space selection instructions and at least one current-space storage element that together allow a computer to address a larger number of devices than allowed by a limited number of address terminals on the computer. Specifically, the current-space storage element is encoded with a space-selection signal that indicates a "current" address space, i.e. which one of a number of mutually exclusive address spaces is currently accessed. The space-selection signal can be changed by any device using a data bus to store signals indicative of a new address space as the "current" address space in the current-space storage element. The current-space storage element is included in a first device that can be accessed by the computer at any time by driving a signal active on a high address line of an address bus.