Abstract: A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software.

Abstract: An address generation apparatus and an operation apparatus are shown to generate a complex address and to suppress an increase of a mounted area even if a bit width of a counter is widened. An address generation apparatus has at least one counter setting a count value by an operated value, at least one operation section being arranged corresponding to the counter respectively, operating a supplied step value and a count value of the corresponding counter in response to a control signal and supplying the operated count value to the corresponding counter, a selection section selecting either a set value or the operation result of the operation section in response to a control signal and inputting it to the counter, and an address operation section performing an operation in response to a control signal for the count value of the counter and outputting the operation result as an address.

Abstract: An interleaver for use with transform processors provides an address generator allowing for implementation using a reduced memory foot print, and permitting interleaving of an input sequence while minimizing latency.

Abstract: A table value conversion device for use with a memory in which a default table value is stored, a central processing unit for reading a default table value from the memory and outputting an output value, and a functional macro functioning as hardware for processing data and storing a lookup table. The device enables simple and efficient rewriting of values stored in the memory. The device includes a conversion module arranged on an external bus extending between the memory and the central processing unit. The conversion module receives the output value of the central processing unit, performs a correction computation on the received output value to generate a corrected value, and converts a table value of the lookup table in the functional macro based on the corrected value.

Abstract: An input/output request sent from a host is once cued through a channel adapter and is then transferred to a resource manager and is cued, and the cuing is distributed. Even if sequential input/output requests of the host are separated through a distribution processing to a plurality of paths, they are recognized on the device controller side and a countermeasure is taken. In the case in which a path from the host to the device controller is caused to be redundant into an operation system and a standby system, a path confirmation command is issued to the device drivers of a standby system path in order to confirm that the standby system path is normally operated or not. When the issuance of the input/output request is transferred to another path, a command for releasing the reserve of a transfer path is issued from another path.

Abstract: A data storing method for a storage apparatus. The storage apparatus has a memory block, which includes a first terminal and a second terminal. The data storing method includes receiving a data set; selecting a first writing direction or a second writing direction to be a preferred writing direction, wherein when the first writing direction is selected to be the preferred writing direction, the first terminal is a starting point corresponding to the first writing direction, and when the second writing direction is selected to be the preferred writing direction, the second terminal is a starting point corresponding to the second writing direction; and writing the data set into the memory block according to the selected writing direction.

Abstract: Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way prediction scheme lies in its efficiency when dealing with instructions that vary the PC in a non-sequential manner, such as branch instructions including jump instructions. To facilitate caching of non-sequential instructions an additional cache way prediction memory is provided to deal with the non-sequential instructions. Thus during program execution a decision circuit determines whether to use a sequential cache way prediction array or a non sequential cache way prediction array in dependence upon the type of instruction. Advantageously the improved cache way prediction scheme provides an increased cache hit percentage when used with non-sequential instructions.

Abstract: In some embodiments, data may be transferred from a first memory agent to a second memory agent in a first format having a first width, and at least a critical portion of the data maybe transferred from the second memory agent back to the first memory agent in a second format having a second width, where the critical portion is included in a first frame. The critical portion may include a cacheline mapped over a memory device rank. Other embodiments are described and claimed.

Abstract: A system includes a continual process for detecting specific data patterns and changes according to a configuration of re-definable and process generated variables. A coarse sample reference, a fine sample reference, and a data array reference are applied to provide independent control over the number of observable signal elements, the level of change that must be observed before detection can occur, and a memory array reference for data probing. A methodology provides near real-time access to specific information portraying the electrical behavior of raw data patterns from signal detector and/or converter circuits independent of a decompression process.

Abstract: A method of creating a discontiguous address plan for an enterprise is provided which includes determining a hierarchy of routing optimization for an enterprise, determining a number of route advertisement aggregation points at each level of the hierarchy, determining a number of network security policy areas for the enterprise, and determining a number of addresses for each of the network security policy areas. The number of addresses is rounded up to a power of the address scheme base number to produce a plurality of rounded addresses. The method further includes allocating an address range for each of the plurality of rounded addresses so that a starting address of the address range begins on a power of the base number and determining a size of the plurality of address ranges. The size of the plurality of address ranges is rounded up to a power of the base number to produce the size of a repeating policy pattern.

Abstract: The present disclosure relates to an address sub-sampling apparatus and method, and an image sensor employing the same. An address sub-sampling apparatus includes a counting unit that generates a binary address of N bits, N being a natural number larger than 2. The address sub-sampling apparatus also includes an address conversion unit that sub-samples the binary address of N bits to output a sub-sampled address having first, second and third bit groups, wherein the sub-sampled address is arranged in order of the third, the first and the second bit groups from the MSB (Most Significant Bit).

Abstract: The present invention comprises a data access pattern interface that allows software to specify one or more data access patterns such as stream access patterns, pointer-chasing patterns and producer-consumer patterns. Software detects a data access pattern for a memory region and passes the data access pattern information to hardware via proper data access pattern instructions defined in the data access pattern interface. Hardware maintains the data access pattern information properly when the data access pattern instructions are executed. Hardware can then use the data access pattern information to dynamically detect data access patterns for a memory region throughout the program execution, and voluntarily invoke appropriate memory and cache operations such as pre-fetch, pre-send, acquire-ownership and release-ownership.

Abstract: A system and method of improved handling of large pages in a virtual memory system. A data memory management unit (DMMU) detects sequential access of a first sub-page and a second sub-page out of a set of sub-pages that comprise a same large page. Then, the DMMU receives a request for the first sub-page and in response to such a request, the DMMU instructs a pre-fetch engine to pre-fetch at least the second sub-page if the number of detected sequential accesses equals or exceeds a predetermined value.

Abstract: Systems and methods using an excitement protocol enable prediction of which blocks of a resource to prefetch and store in memory. The system maintains a set of excitement values corresponding to the resource being accessed. The system also maintains a threshold. As blocks of the resource are requested, the system updates the set of excitement values. The system compares the excitement level to the threshold to determine whether to prefetch the corresponding resource block.

Abstract: A method for setting an address of a rank in a memory module having a number of memory chips distributed along a byte lane includes setting the first memory chip of the byte lane to have a first rank address, generating a second rank address therein from the first rank address, and driving the second rank address to a second one of the memory chips. Alternatively, the first rank address may be driven to the second memory chip, and then, a second rank address is generated in that second memory chip. Further, the second memory chip is set to have the second rank address in response to the driving the second/first rank address. A power-up sequence after voltage supply, or command signals sent via a serial management bus or the command address bus can be used to initiate the setting of ranks. The rank addresses are re-driven to adjacent memory chips by DQ-lines along a byte lane.

Abstract: Aspects of the present invention are directed at centrally managing the allocation of memory to executable images in a way that inhibits malware from identifying the location of the executable image. Moreover, performance improvements are implemented over traditional systems that enable relative addressed instruction to be resolved at runtime. In this regard, a method is provided that identifies a randomized location to load the executable image into a memory address space. Then, data that may be used to resolve the relative addressed instruction is loaded and maintained in memory. At runtime when pages that store relative addressed instructions are accessed, an arithmetic operation is performed to resolve the relative addressed instruction. As a result, only those relative addressed instructions on pages accessed during program execution are resolved.

Abstract: In some embodiments a processing device is disclosed. The processing device is configured to read data from a memory device. The processing device transmits a read request to the memory device for a data block at a certain address and reads the data block for the certain address from the memory device. The processing device dynamically detects boundaries for the data block read by detecting an alignment pattern in data received from the memory device. Other embodiments are otherwise disclosed herein.

Abstract: A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components. Once the carry-in is computed, a plurality of conditional sums are generated for a logic 0 carry-in and a logic 1 carry-in. Subsequently, a sum is selected from the plurality of conditional sums to form a first portion of an effective address from the logical address components in a first stage and a second portion of the effective address in a second stage. In one embodiment, a fully dynamic high-performance sparse tree adder circuit that generates one in four carries, is used to form an address generation circuit, in accordance with one embodiment. Other embodiments are described and claimed.

Abstract: A method and apparatus for determining a stack distance histogram for running software. The method may include receiving a plurality of memory references each including a corresponding address. The method may also include performing a first hash function and a second hash function on each received address. In addition, the method may include selectively storing an indication representative of each corresponding address in a hash table dependent upon results of the first hash function and the second hash function. A stack distance may then be determined based upon contents of the hash table.

Abstract: A method for determining a stack distance including spatial locality for running software. The method may include receiving a plurality of memory references each including a corresponding address. The method may also include performing a merge function on each address corresponding to each received memory reference to generate a modified version of each corresponding address, and then performing a first hash function on the modified version of each corresponding address. In addition, the method may include performing a filter function on each address corresponding to each received memory reference. The method may further include selectively storing an indication representative of the modified version of each corresponding address in a hash table dependent upon results of the first hash function and the filter function. A stack distance may then be determined based upon contents of the hash table.

Abstract: An address learning method for a network device having a plurality of connection ports, at least one of which is electrically connected to a terminal device. The method includes a fetching process, a hashed-address generating process, a data registering process and an address registering process. The fetching process fetches an address data string from a first memory unit by a programmable logic device (PLD). The hashed-address generating process generates a hashed-address by the programmable logic device. The data registering process writes the address data string into an address data table. The address registering process writes the hashed-address into a hashed-address table. A network device for performing the address data learning method is also disclosed.

Abstract: An address decoder 10 decodes an address signal 20 to generate access signals 22, 24. An OR circuit implements a logical OR of the signals 22, 24 to generate a chip enable signal. An address generation circuit 14 generates an address signal 28 to access the RAM in ascending order from a head address based upon the signal 20. An address inversion circuit 16 inverts and outputs each bit of the signal 28 when the signal 24 is “1” or outputs the address signal without inversion when the signal 24 is “0.” When the chip enable signal is “1,” the RAM performs reading/writing data according to an address signal 30 from the inversion circuit.

Abstract: A combination of circuits for use in a memory device is comprised of a decode circuit responsive to a first portion of address information for identifying a word to be read or written. The decode circuit is further responsive to a second portion of the address information for identifying an order in which one or more portions of the identified word are to be read or written. An address sequencer routes at least one bit of the address information. A sequencer circuit is responsive to the address sequencer for ordering the plurality of data bits within each portion of the identified word.

Abstract: A digital camera containing patient images is connected to an uploader computer and the patient's name or history is entered into the uploader computer. The uploader computer then connects to the Internet, connects to the secure host server, uploads the images to the host server and shuts down the Internet connection. After the physician selects a medical facility and the system verifies the physician's user I.D. and password, the host server constructs an HTML web page which includes a list of patients whose images were previously uploaded by the medical facility and are available for viewing. The physician simply selects the name of a patient and the host server displays the patient information and images on the physician's computer. The system is password-protected at all levels and the operator for each medical facility determines who may have access to the medical facility images.

Abstract: A random number generator, for generating random numbers, includes: a first processing module for generating at least one candidate number array comprising a plurality of candidate numbers respectively corresponding to a plurality of candidate addresses; an address generating module for generating at least one specific address according to at least one generator polynomial, where each specific address is a candidate address within the plurality of candidate addresses; and a second processing module, coupled to the first processing module and the address generating module, within the candidate number array sent from the first processing module, the second processing module selecting the candidate number(s) corresponding to the specific address as random number(s).

Abstract: Devices, systems and methods of reduced-power memory address generation. For example, an apparatus includes: a carry save adder including at least a first set of adders and a second set of adders, wherein the adders of the first set are able to receive a first number of input bits and to produce a first number of outputs, and wherein adders of the second set are able to receive a second number of input bits and to produce the first number of outputs.

Abstract: Various embodiments of the present invention provide for immediate allocation of virtual memory on behalf of processes running within a computer system. One or more bit flags within each translation indicate whether or not a corresponding virtual memory page is immediate. READ access to immediate virtual memory is satisfied by hardware-supplied or software-supplied values. WRITE access to immediate virtual memory raises an exception to allow an operating system to allocate physical memory for storing values written to the immediate virtual memory by the WRITE access.

Abstract: A method for generating addresses for a processor is provided. The addresses are for use by an application that may be executed by the processor. The application comprises a plurality of instructions, and each instruction comprises at least one line. The method includes storing a plurality of predetermined addresses and, for each line of each instruction, generating at least one address for the processor based on the predetermined addresses.

Abstract: Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command signal from a first communication register to retrieve a first set of data from memory according to a look up table of memory addresses. The first memory access generator reads the look up table of memory addresses, which contain a second set of memory commands and reroutes the second set of commands to a bypass register. In turn, the second set of memory commands stored at the bypass register are read by a second memory address generator which retrieves a second set of data from memory according to the second set of memory command signals read out of memory by the first memory address generator.

Abstract: To correctly generate LAs even when out-of-order occurs. In a disk array system according to the present invention, a control unit includes: a host input/output unit that exchanges data and a control signal with a host connected to a disk array system; a disk input/output unit that exchanges data and a control signal with a disk; a cache memory that temporarily stores the data during transfer between the host input/output unit and the disk input/output unit in units of segments that are each formed by a plurality of blocks having a predetermined size; an MPU that controls an operation of the control unit by executing a control program; and a cache controller that controls input/output of the data into/from the cache memory, and the host input/output unit transfers, to the cache controller, transfer information containing the guarantee codes of the first blocks of the segments relating to the data transfer.

Abstract: A memory includes an address bus, address counter, address decoder, comparator, and control circuit. During a data read or write cycle, the address bus receives an external address, the address counter generates an internal address, which the address decoder decodes, and the comparator compares the external address to a value. Based on the relationship between the external address and the value, the comparator enables or disables the data transfer. For example, such a memory can terminate a page-mode read/write cycle by determining when the current external column address is no longer equal to the current internal column address. This allows the system to terminate the cycle after a predetermined number of data transfers by setting the external column address to a value that does not equal the internal column address.

Abstract: A memory controller which can perform a series of data write operation to a flash memory device fast is disclosed. The memory controller according to an embodiment of the present invention is the memory controller for accessing a memory having a plurality of physical blocks based on a host address provided from a host computer. The memory controller has means for dividing the physical blocks into a plurality of groups, means for forming a plurality of virtual blocks by virtually combining a plurality of physical blocks each of which belongs to different groups, the virtual blocks can be divided into at least a first class and a second class, and means for assigning adjacent host addresses into different physical blocks belonging to the same virtual block of the first class and assigning adjacent host addresses into the same physical blocks belonging to the same virtual block of the second class.

Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.

Abstract: The Internet data defining destinations accessible by a router are partitioned into a portion containing the address search information and a portion containing forwarding option data. The address search information is stored in fast memory in a tree search format and the set of possible next destinations are stored as forwarding option data in slower memory at addresses derived algorithmically from the tree search address information. Internet data packets are received and data therein is compared to determine the best match address in the fast memory to the set of possible best next destinations. The multiple accesses necessary to determine the best match address are confined to high speed memory. An algorithm receives option data from an Internet packet and option threshold data from the best match address of the high speed memory and determines which address of the slower memory has the desired forwarding data using one access.

Abstract: The present invention realizes pre-fetch based on a high-accuracy prediction. A plurality of address values are registered in advance in a pre-fetch address queue, based on previous memory accesses. If a request address from the processor unit of a request address register matches this address value, a pre-fetch address obtained by adding a block size to the request address is output to a secondary cache as a pre-fetch request. This pre-fetch address is written back into the pre-fetch address queue.

Abstract: An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.

Abstract: Methods and apparatus provide for: testing a static random access memory (SRAM) to obtain performance data on the SRAM; and using the performance data as at least a basis of a identification number.

Abstract: A method of accessing matrix data of a semiconductor memory having memory banks. The memory banks each having memory cells arranged in X and Y directions, a Y decoder for selecting Y-direction addresses of the memory cells and an X decoder for selecting X-direction addresses of the memory cells, predicated on the memory banks being operable independently. Items of data specified by a specified number of continuous X addresses and having the same Y addresses are successively written into or read from the memory cells arranged in the X direction, which are specified by X addresses corresponding to 1+knth in one of the banks. After all data have been written into or read from the specified memory cells, corresponding data are successively written into or read from the memory cells specified by X addresses corresponding to 2+knth in another one of the banks.

Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.

Abstract: A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active location in the memory array are processed prior to addresses that do not correspond to an active location. Data is read from the memory to a read buffer and ordered in a manner commensurate with the order of received addresses at the address buffer (e.g., thus facilitating access to the memory in an order different from that received at the address buffer while maintaining the order from the read buffer).

Abstract: The present invention provides for the employment of a dynamic debugger for a parallel processing environment. This is achieved by dynamically updating mapping information at run-time in a mapping table, wherein the mapping table is read by the dynamic debugger.

Abstract: A processor includes a trace cache memory coupled to a trace generator. The trace generator may be configured to generate a plurality of traces each including one or more operations that may be decoded from one or more instructions. Each of the operations may be associated with a respective address. The trace cache memory is coupled to the trace generator and includes a plurality of entries each configured to store one of the traces. The trace generator may be further configured to restrict each of the traces to include only operations having respective addresses that fall within one or more predetermined ranges of contiguous addresses.

Abstract: A system for generating addresses for a digital signal processor in which the program instructions include a code for accessing a memory associated with said processor. An address calculation circuit calculates each access address to the memory on the basis of operation codes designated by the address generation code of one of the instructions and of the content of one address register selected from said address registers. Each address generation code defines an operation code to be sent to the calculation circuit. Each of the address registers is further associated with a configuration register designated at the same time as the address register by the address generation code, and each of the configuration registers contains a set of predefined operation codes, each adapted to command a predetermined calculation operation in the calculation circuit.

Abstract: An interface for accessing a bank of registers is described. A controller is coupled to receive address information, read information and write information. The device control register interface includes: a data bus for receiving data, pointer information and operation delineation information; a decoder coupled to receive the read information, the write information, the pointer information and the operation delineation information, where the decoder is configured to provide activation signaling responsive to information received; and the bank of registers coupled to the decoder to receive the activation signaling and coupled to the data bus for receiving the data, where the address information is for the bank or registers and where a single address is used for accessing all registers in the bank of registers.

Abstract: A method and mechanism for managing timers in a multithreaded processing system. A storage device stores a plurality of count values corresponding to a plurality of timers. A read address generator is coupled to convey a read address to the storage device. The read address generator is configured to maintain and increment a first counter. In response to determining the counter does not equal a predetermined value, the mechanism conveys a first read address for use in accessing a count value in the storage device. In response to determining the count equals the predetermined value, the mechanism conveys a second read address for use in accessing a count value in the storage device. The predetermined value is utilized to repeat accesses to a given count value a predetermined number of times.

Abstract: A method of carrying out a data fetch operation for a data-parallel processor such as a SIMD processor is described. The operation is specifically involving the use of a plurality of non-sequential data addresses. The method comprises constructing a linear address vector from the non-sequential addresses, and using the address vector in a block fetch command to a data store.

Abstract: A data processing device has load and store instructions which address memory with the content of a data pointer register. In a normal mode, the same data pointer register is used for all load and store instructions. In this mode the processor is compatible with a older processor design. In a special mode, at least two different registers are used alternately to address memory when memory access instructions are executed. A control register controls whether or not the different registers are updated as part of the memory access instructions. Preferably, the control register provides for more than one different kind of update of the different registers, such as post addressing increment, post addressing decrement etc.

Abstract: The present invention provides improved techniques for managing storage resources, such as disk drives, I/O ports, and the like in a network based storage system according to a user position within the network. Embodiments according to the present invention can provide a relatively high performance storage access environment for the mobile users moving around a wide area. For example, in one applicable environment, there are several data centers in the wide area, and each data center has a local storage system that is connected to the other storage systems through a network. Copies of a user's volume can be made in some of the storage systems. A remote copy function is utilized for making real time copies of the user's volume.

Abstract: A data processing apparatus and method are provided for controlling access to a slave device, the slave device having an address range associated therewith. The apparatus comprises control storage programmable to define a partition identifying a secure region and a non-secure region in the address range, with the data processing apparatus supporting a plurality of modes of operation including a secure mode, and the control storage being programmable only by software executing in the secure mode. A master device is arranged to issue an access request onto a bus, the access request identifying a sequence of addresses within the address range and including a control signal indicating whether the access request is a secure access request or a non-secure access request. The secure region is only accessible by a secure access request.

Abstract: A data interface includes a network interface processor, a transmitter, and a receiver. The network interface processor is operably coupled to transceive parallel data via a network connection. The transmitter is operably coupled to convert outbound parallel data from the network interface processor into serial transmit data. The receiver is operably coupled to convert serial receive data into inbound parallel data, wherein the receiver provides the inbound parallel data to the network interface processor.