Abstract: Memory leak detection can be automated by assigning and recording an increasing sequence number to each memory allocation requested by an action. Call stacks associated with the action are also recorded. Several repetitions of the action can be executed. Allocations that occur in each action and that have similar or matching callstacks are defined as leaks. Allocations that do not have matches can be ignored.

Abstract: A memory control device that transfers data from an external memory to a data processing unit having plural processing mechanisms, includes an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period; a differential address storage unit that stores plural differential addresses therein; a differential address selection unit that selects any one of the plurality of differential addresses in a given order; a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address; and a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit.

Abstract: A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.

Abstract: In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data.

Abstract: Read messages are grouped by a plurality of unique sequence identifications (IDs), where each of the sequence IDs corresponds to a specific read sequence, consisting of all read and read-ahead requests related to a specific storage segment that is being read sequentially by a thread of execution in a client application. The storage system uses the sequence id value in order to identify and filter read-ahead messages that are obsolete when received by the storage system, as the client application has already moved to read a different storage segment. Basically, a message is discarded when its sequence id value is less recent than the most recent value already seen by the storage system. The sequence IDs are used by the storage system to determine corresponding read-ahead data to be loaded into a read-ahead cache.

Abstract: A key transport method for transporting a key from a buffer memory to an encryption/decryption unit is provided. The method includes logically dividing bits of the key into key segments, wherein each of the key segments has a start position and a segment length. The method also includes setting a transmission length belonging to each of key segments based on the start positions and the segment lengths of the key segments; assigning a transmission bit stream belonging to each of the key segments from the bits of the key according to the start positions and the transmission lengths of the key segments; determining a transmission sequence; and sending the start position, the segment length and the transmission bit stream belonging to each of the key segments to the encryption/decryption unit from the buffer memory based on the transmission sequence. Accordingly, the method can transport the key safely.

Abstract: Various methods and systems for securing access to hash-based storage systems are disclosed. One method involves receiving information to be stored in a storage system from a storage system client and then generating a key. The key identifies the information to be stored. The value of the key is dependent upon a secret value, which is associated with the storage system. The key is generated, at least in part, by applying a hash algorithm to the information to be stored. The key can then be returned the key to the storage system client. The storage system client can then use the key to retrieve the stored information.

Abstract: A method for installing linked MIFARE applications (TK1-A, TK1-B, TK1-C) in a MIFARE memory (MM) being configured as a MIFARE Classic card or an emulated MIFARE Classic memory comprises storing the first linked MIFARE application (TK1-A) in a first free sector of the MIFARE memory, storing the second linked MIFARE application (TK1-B) in a second free sector of the MIFARE memory and writing link information (LK) indicating this second sector in a link information memory location of the first sector where first linked MIFARE application (TK1-A) has been stored, and repeating the steps of storing linked MIFARE applications and writing link information (LK) until the last linked MIFARE application (TK1-C) has been stored.

Abstract: A convolutional interleaver uses local memory of a first IC in combination with burst-type memory of a second IC. When a burst of data is read from memory of the second IC, one data value is provided to a data output and the remaining values are temporarily stored in local memory. After the memory of the second IC is initially filled, burst WRITE and burst READ operations provide efficient data transmission between the ICs.

Abstract: The technique introduced here involves using a block address and a corresponding generation number as a “fingerprint” to uniquely identify a sequence of data within a given storage domain. Each block address has an associated generation number which indicates the number of times that data at that block address has been modified. This technique can be employed, for example, to determine whether a given storage server already has the data, and to avoid sending the data to that storage server over a network if it already has the data. It can also be employed to maintain cache coherency among multiple storage nodes.

Abstract: Techniques for efficiently generating addresses for pruned interleavers and pruned de-interleavers are described. In an aspect, a linear address may be mapped to an interleaved address for a pruned interleaver by determining the total number of invalid mappings corresponding to the linear address. The linear address may be summed with the total number of invalid mappings to obtain an intermediate address. The interleaved address for the pruned interleaver may then be determined based on a non-pruned interleaver function of the intermediate address. The pruned interleaver may be a pruned bit-reversal interleaver, a pruned Turbo interleaver composed of a bit-reversal function and a linear congruential sequence function, or some other type of interleaver. The total number of invalid mappings may be determined iteratively, and each iteration may be performed in different manners for different types of pruned interleaver.

Abstract: A device that implements a method for performing integrated caching in a data communication network. The device is configured to receive a packet from a client over the data communication network, wherein the packet includes a request for an object. At the operating system/kernel level of the device, one or more of decryption processing of the packet, authentication and/or authorization of the client, and decompression of the request occurs prior to and integrated with caching operations. The caching operations include determining if the object resides within a cache, serving the request from the cache in response to a determination that the object is stored within the cache, and sending the request to a server in response to a determination that the object is not stored within the cache.

Abstract: A device for storing data includes a sequence generator configured to generate a first number sequence that is a pseudorandom number sequence, a cross-correlation unit configured to produce a second number sequence that is a cross-correlation between the first number sequence and a third number sequence, and a write and read unit configured to write the second number sequence in memory and read the second number sequence from the memory, wherein the cross-correlation unit is further configured to reconstruct the third number sequence by obtaining a cross-correlation between the first number sequence and the second number sequence read from the memory.

Abstract: An input data stream is received for processing at an integrated circuit (IC) through multiple channels. The input data stream is interleaved and the interleaved input data stream is stored in a memory buffer associated with the IC. An addressing scheme is defined for reading and writing data samples from and to the memory buffer within the IC. The addressing scheme includes determining a current increment by analyzing a pattern associated with data samples within the memory buffer and determining the memory address for each data sample within the memory buffer using the current increment. A data sample for a frame is read from a corresponding address within the memory buffer using the addressing scheme and a subsequent data sample from the interleaved input data stream is written into the corresponding address of the memory buffer. The current increment and the addressing scheme are stored in the memory buffer.

Abstract: A system, method, and computer-readable storage medium for mapping block numbers within a region to physical locations within a storage system. Block numbers are mapped within a region according to a fractal-based space-filling curve. If the region is not a 2k by 2k square, then the region is broken up into one or more 2k by 2k squares. Any remaining sub-region is centered within a 2k by 2k square, the 2k by 2k square is numbered using a fractal-based space-filling curve, and then the sub-region is renumbered by assigning numbers based on the order of the original block numbers of the sub-region.

Abstract: An apparatus, system, and method for providing a multi-dimensional data structure and address generation unit configured to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern. The address generation unit may be configured to calculate the real addresses by executing a series of nested loops pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure. The address generation unit may receive as inputs a set of parameters defining characteristics of the nested loops such as a starting offset, number of iterations or step size for loops, data structure dimensions, or loop starting point inheritance. A vector processor may then access the multi-dimensional data structure at the real addresses calculated by the address generation unit. The multi-dimensional data structure may be stored in a buffer in a data memory.

Abstract: An information processing apparatus comprising: a reception unit adapted to receive a packet containing first data to be stored in a storage unit, a first address indicating an address of second data held in the storage unit, and a second address indicating an address at which the first data is to be written in the storage unit; an access unit adapted to read out the second data from the storage unit based on the first address, and write the first data in the storage unit based on the second address; and a transmission unit adapted to replace the first data of the packet received by the reception unit with the second data read out by the access unit, and transmit the packet.

Abstract: A network device assigns unique encoded values, represented by mnemonics, to protocol headers supported by the network device, and defines a plurality of templates, where each template includes a set of the mnemonics. The network device also stores the plurality of templates in a template table, where the template table enables the network device to create one or more protocol headers for packets transmitted by the network device.

Abstract: A baseboard management controller is disclosed. The baseboard management controller adapted to monitor a host comprises a baseboard management control module, a memory controller and a video graphic array (VGA) module. The VGA module comprises a video controller, a decoder, a select circuit and a mapping circuit. The decoder receives a transaction signal from a first local bus and decodes a first address signal contained in the transaction signal. The select circuit selectively transfers data from one of the microprocessor bus, the video controller and the memory controller back to the first local bus according to a control signal. The mapping circuit being connected with the decoder maps the first address signal and a second address signal to a third address signal, updates the first address signal and transfers an updated transaction signal.

Abstract: A device for storing data includes a sequence generator configured to generate a first number sequence that is a pseudorandom number sequence, a cross-correlation unit configured to produce a second number sequence that is a cross-correlation between the first number sequence and a third number sequence, and a write and read unit configured to write the second number sequence in memory and read the second number sequence from the memory, wherein the cross-correlation unit is further configured to reconstruct the third number sequence by obtaining a cross-correlation between the first number sequence and the second number sequence read from the memory.

Abstract: Systems and methods are disclosed for reducing memory usage and increasing the throughput in variable-size Fast Fourier Transform (FFT) architectures. In particular, 3D symmetric virtual memory is disclosed to exploit the structure inherent in variable-size FFT computations. Data samples may be written to and read from the 3D symmetric virtual memory in a specific sequence of coordinates that exploits the structure inherent in variable-size FFT computations. Memory locations in the 3D symmetric virtual memory may be mapped to memory address in a 1D buffer using an address generation circuit.

Abstract: A non-volatile semiconductor memory is disclosed comprising N memory devices each comprising a plurality of blocks, wherein each block comprises a plurality of memory segments accessed through an address. A searched is performed by issuing a read command for each of the N memory devices, wherein an address of each read command is separated by a distance determined in response to the search range of addresses and N, and the search range of addresses is greater than N. Data read from at least one of the memory devices is evaluated to determine whether the search has finished.

Abstract: A method of performing a write operation in a nonvolatile memory device comprises storing write data in a log block used to update a data block, determining whether a write pattern stored in the log block is a sequential write pattern or a random write pattern, and selecting a new data block for storing merged data in the data block and the log block. The new data block is determined to be a single-level cell block or a multi-level cell block according to the determined write pattern.

Abstract: A wireless communications device has two or more multiple port memory units operable to perform encryption/decryption shuffling and processing. Other circuits and methods of manufacture and operation are also disclosed.

Abstract: In response to a memory allocation request received from an application thread, a random number is obtained (e.g., from a random number list previously populated with multiple random numbers). A starting location in at least a portion of a bitmap associated with a region including multiple blocks of the memory is determined based on the random number. A portion of the bitmap is scanned, beginning at the starting location, to identify a location in the bitmap corresponding to an available block of the multiple blocks, and an indication of this available block is returned to the application thread.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing and using a partial-address select-signal generator with address shift.

Abstract: A system and method for storing and retrieving a sparse matrix from memory of a computing device while minimizing the amount of data stored and costly jumps in memory. The computing device may be an FPGA having memory and processing elements. The method comprises storing non-zero data elements of the matrix in a data array and storing their corresponding column address values in a column index array. To read this stored data from memory, each preceding value of the column index array may be compared with each current value of the column index array to determine if the data array value corresponding with the current column index array value belongs on the next row of the matrix. The method may include pre-ordering the matrix with zero-pad placeholders or creating a row increment pointer array which typically stores fewer values than the number of rows in the matrix.

Abstract: In one aspect, methods and systems for variable-block length encoding of data, such as an inverted index for a file are disclosed. These methods and systems provide for relatively fast encoding and decoding, while also providing for compact storage. Other aspects include a nearly 1:1 inverted index comprising a position vector and a data store, wherein values that have a unique location mapping are represented directly in the position vector, while for 1:n values (n>1), the position vector can include a pointer, and potentially some portion of information that would typically be stored in the data area, in order to fully use fixed width portions of the position vector (where a maximum pointer size is smaller than a maximum location identifier size).

Abstract: Read messages are issued by a client for data stored in a storage system. A client agent mediates between the client and the storage system. Each sequence of read requests generated by a single thread of execution in the client to read a specific data segment in the storage is defined as a client read session. Each read request sent from the client agent to the storage system includes a position and a size for reading. The read-ahead cache and a current sequence ID value for each client read session are maintained. For each incoming read request, the storage system determines whether to further process the read request based on a sequence ID value of the read request, and the source from which to obtain data for the read request, and which of the data to load into the read-ahead cache according to data positions of the read request.

Abstract: Some of the embodiments of the present disclosure provide a method for predicting, for a first virtual address, a first descriptor based at least in part on the one or more past descriptors associated with one or more past virtual addresses; and determining, for the first virtual address, a first physical address based at least in part on the predicted first descriptor. Other embodiments are also described and claimed.

Abstract: Read messages are issued by a client for data stored in a storage system of the networked client-server architecture. A client agent mediates between the client and the storage system. Each sequence of read requests generated by a single thread of execution in the client to read a specific data segment in the storage is defined as a client read session. The client agent maintains a read-ahead cache for each client read session and generates read-ahead requests to load data into the read-ahead cache. Each read request and read-ahead request sent from the client agent to the storage system includes positions and a size for reading and a sequence id value. The storage system filters and modifies incoming read request and read-ahead requests based on sequence ID values, positions and sizes of the incoming read request and read-ahead requests.

Abstract: Read messages are issued by a client for data stored in a storage system of the networked client-server architecture. A client agent mediates between the client and the storage system. Each sequence of read requests generated by a single thread of execution in the client to read a specific data segment in the storage is defined as a client read session. Each read request sent from the client agent to the storage system includes positions and size for reading. A read-ahead cache is maintained for each client read session. The read-ahead cache is partitioned into two buffers. Data is loaded into the logical buffers according to the changes of the positions in the read requests of the client read session and loading of new data into the buffers is triggered by the read requests positions exceeding a position threshold in the data covered by the second logical buffer.

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract: Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences such as high-level language software critical loops are converted into read/transform/write (RXW) processes with buffer based flow control between the processes. Having separate read and write processes allows an arbitrary number of sequential reads/writes to occur in any order, subject to buffer size, allowing bursting/sequential transactions that are more efficient than random accesses.

Abstract: Methods, apparatuses, and computer program products for accessing a logic device through a serial interface are provided. Embodiments include receiving, by the serial interface of the logic device, a first data access request indicating a non-linear address mode, wherein the first data access request includes: a non-linear address corresponding to a non-linear index specifying a plurality of non-linear addresses, the non-linear index associating each non-linear address with one of the plurality of registers; a data count indicating an amount of data to be accessed in the first data access request; and a page offset value indicating within a register, a starting page to perform the first data access request. Embodiments also include identifying in the non-linear address mode a location within the logic device based on the non-linear address and the starting page; and performing at the identified location, by the logic device, a serial transaction in accordance with the first data access request.

Abstract: A device identifies array accesses of variables in a program code that includes multiple arrays, and identifies array access patterns for one of the array accesses. The device also determines an order of the array access patterns identified for the array accesses, and calculates, based on the order, distances between the array access patterns. The device further shares address calculations amongst the array accesses associated with array access patterns with one or more of the distances that are equivalent.

Abstract: A system comprises a system interface to receive one or more instruction sets from a microcontroller and to receive digital data to be processed. The system further comprises a controller that is reconfigurable according to the one or more instruction sets received by the system interface. The system further comprises a data path device to perform digital filtering operations on the digital data as directed by the controller according to the reconfiguration of the controller by the one or more instruction sets.

Abstract: A method for providing at least one sequence of values to a plurality of processors is described. In the method, a sequence generator from one or more sequence generators is associated with a memory location. The sequence generator is configured to generate the at least one sequence of values. One or more read accesses of the memory location are enabled by a processor from the plurality of processors. In response to enabling the read access, the sequence generator is executed so that it returns a first value from the sequence of values to the processor. After executing the sequence generator, the sequence generator is advanced so that the next access generates a second value from the sequence of values. The second value is sequentially subsequent to the first value.

Abstract: An apparatus and method in a computer system allows a software application to specify an intended stride access when writing data elements into a memory. A memory control in the computer system writes data in a manner that provides improved access performance when accesses to the data elements are performed using the intended stride. The memory system uses a hashing mechanism that uses the intended stride to store the data elements in such a way that accessing the data elements at the intended stride will ensure that consecutive accesses are not to the same group or bank of memory. Sequential accesses of the data elements also are ensured not to be directed to the same group or bank of memory. The memory can be divided into memory portions; different memory portions of the computer storage can have different intended strides.

Abstract: A data processing system comprises multiple data processing nodes that communicate with one another using the FlexRay protocol. Each respective node works according to a respective schedule based on a repetitive sequence of cycles, each cycle having a sequence of time slots. Each node executes instructions, one per time slot, if any. The instructions are stored in a memory. Each instruction is identified by the relevant cycle number and time slot number in the relevant cycle. Accordingly, the combination of cycle number and slot number identify a memory address. Typical instructions appear more than once in the repetitive sequence of cycles for a node. This temporal pattern of occurrences of the same instruction at a node is used to modify the generation of the memory addresses, so that the same memory address is generated each time the instruction is needed. This makes efficient use of storage space.

Abstract: In accordance with an aspect of the invention, a storage system includes a processor; a memory; a disk control module configured to receive a write command for writing to an unallocated area and to identify an object of the write command to be written as a written object; and an object allocation acquisition module configured to obtain object allocation information specifying one or more virtual volume locations for storing the written object. The disk control module allocates, to each of the one or more virtual volume locations, an area selected from a plurality of logical volumes if the written object is predefined as a randomly accessed object. The disk control module allocates to the one or more virtual volume locations a consecutive area of one logical volume if the written object is predefined as a sequentially accessed object.

Abstract: A controller for the storage apparatus: creates a second logical volume in a storage area provided by one or more storage devices; stores management information of a snapshot of a first logical volume, which is to be provided to a host computer, in the second logical volume; and reads the management information of a necessary snapshot from the second logical volume to a memory when needed, executes processing using the read management information, and returns the management information, which becomes no longer necessary, from the memory to the second logical volume. When reading the management information of the necessary snapshot from the second logical volume to the memory when needed, the controller changes the number of generations and address range of the snapshot of the management information to be read to the memory according to a generation and address of the snapshot whose management information is required.

Abstract: A method of loading data into register files that correspond to respective execution units within a data-parallel processor. After receiving a first set of parameters that specify a subset of data within a first memory, the first set of parameters are compared to a plurality of sets of conditions that correspond to respective patterns of data. The first set of parameters is then converted to a second set of parameters in accordance with one of the sets of conditions satisfied by the first set of parameters. A sequence of memory addresses are generated based on the second set of parameters. Data is retrieved from locations within the first memory specified by the sequence of memory addresses and loaded into register files that correspond to respective execution units within a processor.

Abstract: Exploit nonspecific host intrusion prevention/detection methods, systems and smart filters are described. Portion of network traffic is captured and searched for a network traffic pattern, comprising: searching for a branch instruction transferring control to a first address in the memory; provided the first instruction is found, searching for a subroutine call instruction within a first predetermined interval in the memory starting from the first address and pointing to a second address in the memory; provided the second instruction is found, searching for a third instruction at a third address in the memory, located at a second predetermined interval from the second address; provided the third instruction is a fetch instruction, indicating the presence of the exploit; provided the third instruction is a branch instruction, transferring control to a fourth address in the memory, and provided a fetch instruction is located at the fourth address, indicating the presence of the exploit.

Abstract: Testing a circuit in a post-silicon stage is performed by enabling the different processing entities of the circuit to determine a consistent access permissions schema in a random manner. Based upon the consistent access permissions schema, addresses to be accessed during the testing of the circuit may be determined. The addresses may be determined in a random manner. The consistent permissions schema may be determined based on a template representative of repetitive portions of access permissions schema. The disclosed subject matter may utilize biasing modules to bias the test generation to provide a test having a predetermined characteristic. The disclosed subject matter may utilize a joint random seed or other techniques to provide for consistent random decisions by the different processing entities.

Abstract: A system and method for generating a real address in data memory in response to a read/write request may include generating an access request to at least one of read and write data to the data memory. A connection identifier (ID), received in association with the access request; may include a buffer ID designating a buffer in the data memory in which to access the data, and a port ID designating a pattern in which to access the data in the buffer. The method may further include translating the connection ID into the real address of the data memory, and accessing the data memory at a location corresponding to the real address. Different types of buffers, such as point-to-point, scatter, and gather buffers may be used, and different patterns, such as first-in-first out (FIFO), nested loop, matrix transforms may be used.

Abstract: The present disclosure provides a system and method for wear leveling. In one example, the method includes receiving first data to be stored to a first data storage medium and storing the first data to a first storage location in a nonvolatile data store of a second data storage medium comprising a solid-state memory. The method also includes setting a pointer to enable writing second data that is received to a next storage location in the nonvolatile data store. The next storage location comprises an address of the nonvolatile data store that is sequentially after an address of the first storage location. When the address of the first storage location is a last addressed location of the nonvolatile data store the pointer is set to enable writing the second data to a first addressed location of the nonvolatile data store.

Abstract: A burst address generator includes a burst bit counter for receiving at least one burst bit, and increasing or decreasing the at least one burst bit, a burst bit splitter for receiving the increased or decreased at least one burst bit from the burst bit counter, and dividing the increased or decreased at least one burst bit into an X burst bit and a Y burst bit, and a selector for receiving an X address, a Y address, the X burst bit, and the Y burst bit, and generating an X burst address based on the X address and the X burst bit and a Y burst address based on the Y address and the Y burst bit.

Abstract: One or more embodiments of the invention enable a memory device to load its memory array with desired background data, such as to reduce total test time and costs associated with testing. A background data loading circuit according to one embodiment of the invention includes a buffer, a data loading circuit, and a pattern generating logic. The buffer is coupled to the array of memory cells. The data loading circuit is coupled to load data into the buffer to be transferred to a respective row of the memory cells. The pattern generating logic is coupled to the data loading circuit. The pattern generating logic applies a pattern generating algorithm corresponding to a test mode when the memory devices is in the test mode and generates patterns of data each for a respective row of the memory cells according to the pattern generating algorithm.

Abstract: A method for address generation checking including receiving a starting memory address for a data, an ending memory address for the data, a length value of the data, and an address wrap indicator value that indicates if the data wraps from an end of a memory block to a start of the memory block, determining whether the ending memory address is equal to a sum of the starting memory address added to a difference of the length value to the address wrap indicator value, and transmitting an error signal that indicates an error occurred in a generation of the starting memory address or the ending memory address if the ending memory address is not equal to the sum.