Using Table Patents (Class 711/221)
  • Patent number: 9171030
    Abstract: In a method for populating a lookup table, a plurality of hash tables are provided. Each hash table is accessed by a respective hash function. A plurality of hashed values for a key are generated using the hash functions corresponding to the plurality of hash tables. The plurality of hashed values are used to determine whether the key can be inserted into one or more hash tables of the plurality of hash tables without colliding with keys previously stored at respective locations corresponding to the determined hashed values. When it is determined that the key can be inserted into multiple hash tables, it is then determined which one of the multiple hash tables is populated with the greatest number of keys. The hash table that is populated with the greatest number of keys is selected for insertion of the key, and the key is inserted into the selected hash table.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: October 27, 2015
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventors: Carmi Arad, Gil Levy
  • Patent number: 9143449
    Abstract: Methods and apparatuses for improving performance of database searches are disclosed herein. For example, in some implementations, the methods and apparatuses use a data node structure that prevents the need to duplicate data nodes shared by a plurality of data trees. Additionally, the methods and apparatus facilitate improved database lookup times by implementing an adaptive presence detection system based on the Bloom Filter, performance characteristics of the computing device evaluated at run time and status of the database.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: September 22, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Salvatore Valenza, Leo Caldarola, Roberto Muccifora, Domenico Ficara
  • Patent number: 9037544
    Abstract: In one embodiment, snapshots and/or clones of storage objects are created and managed by a volume layer of a storage input/output (I/O) stack executing on one or more nodes of a cluster. Illustratively, the snapshots and clones may be represented as independent volumes, and embodied as respective read-only copies (snapshots) and read-write copies (clones) of a parent volume. Volume metadata is illustratively organized as one or more multi-level dense tree metadata structures, wherein each level of the dense tree metadata structure (dense tree) includes volume metadata entries for storing the metadata. Each snapshot/clone may be derived from a dense tree of the parent volume (parent dense tree). Portions of the parent dense tree may be shared with the snapshot/clone.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: May 19, 2015
    Assignee: NetApp, Inc.
    Inventors: Ling Zheng, Blake H. Lewis, Kayuri H. Patel
  • Patent number: 9032164
    Abstract: The splitting of storage applications and functions into a control path (CP) component and a data path (DP) component is disclosed. Reads and writes may be handled primarily in the DP. The CP may be responsible for discovery, configuration, and exception handling. The CP can also be enabled for orchestrating complex data management operations such as snapshots and migration. Storage virtualization maps a virtual I/O to one or more physical I/O. A virtual target (vTarget) in the virtual domain is associated with one physical port in the physical domain. Each vTarget may be associated with one or more virtual LUNs (vLUNs). Each vLUN includes one or more vExtents. Each vExtent may point to a region table, and each entry in the region table may contain a pointer to a region representing a portion of a pExtent, and attributes (e.g. read/write, read only, no access) for that region.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: May 12, 2015
    Assignee: Emulex Corporation
    Inventors: Sriram Rupanagunta, Parag Bhide
  • Patent number: 9021210
    Abstract: A mechanism is provided in a cache subsystem for cache prefetching based on non-sequential access. The mechanism determines frequently accessed non-sequential cache records in the cache subsystem. The mechanism collects trailing record statistics for the frequently accessed non-sequential cache records. The mechanism determines a caching strategy. The caching strategy comprises prefetching a set of trailing records responsive to a read of a given frequently accessed non-sequential cache record. The mechanism applies the caching strategy to the cache subsystem.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bruce McNutt, Vernon W. Miller
  • Patent number: 9015133
    Abstract: A technique for resizing a first RCU-protected hash table stored in a memory. A second RCU-protected hash table is allocated in the memory as a resized version of the first hash table having a different number of hash buckets, with the hash buckets being defined but initially having no hash table elements. The second hash table is populated by linking each hash bucket thereof to all hash buckets of the first hash table containing elements that hash to the second hash bucket. The second hash table is then published so that it is available for searching by hash table readers. The first table is freed from memory after waiting for a grace period which guarantees that no readers searching the first hash table will be affected by the freeing.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Paul E. McKenney, Joshua A. Triplett
  • Publication number: 20150106588
    Abstract: A computer processor is provided with execution logic that performs operations that utilize pointers stored in memory. In one aspect, each pointer is associated with a predefined number of event bits. The execution logic processes the event bits of a given pointer in conjunction with processing a predefined pointer-related operation involving the given pointer in order to selectively output an event-of-interest signal. In another aspect, each pointer is represented by an address field and a granularity field. The address field includes a chunk address and an offset. The granularity field represents granularity of the offset of the address field. The execution logic includes an address derivation unit that processes the granularity field of a base address for a given pointer in order to generate a valid address field for the derived pointer.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 16, 2015
    Applicant: Mill Computing, Inc.
    Inventors: Roger Rawson Godard, Arthur David Kahlich
  • Patent number: 9009122
    Abstract: A technique for resizing a first RCU-protected hash table stored in a memory. A second RCU-protected hash table is allocated in the memory as a resized version of the first hash table having a different number of hash buckets, with the hash buckets being defined but initially having no hash table elements. The second hash table is populated by linking each hash bucket thereof to all hash buckets of the first hash table containing elements that hash to the second hash bucket. The second hash table is then published so that it is available for searching by hash table readers. The first table is freed from memory after waiting for a grace period which guarantees that no readers searching the first hash table will be affected by the freeing.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Paul E. McKenney, Joshua A. Triplett
  • Patent number: 8990166
    Abstract: A data size characteristic of contents of a related unit of data to be written to a storage by an input/output module of a data storage application can be determined, and a storage page size consistent with the data size can be selected from a plurality of storage page sizes. The related unit of data can be assigned to a storage page having the selected storage page size, and the storage page can be passed to the input/output module so that the input/output module physically clusters the contents of the related unit of data when the input/output module writes the contents of the related unit of data to the storage. Related methods, systems, and articles of manufacture are also disclosed.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: March 24, 2015
    Assignee: SAP SE
    Inventors: Dirk Thomsen, Axel Schroeder, Ivan Schreter
  • Patent number: 8990504
    Abstract: A cache page management method can include paging out a memory page to an input/output controller, paging the memory page from the input/output controller into a real memory, modifying the memory page in the real memory to an updated memory page and purging the memory page paged to the input/output controller.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tara Astigarraga, Michael E. Browne, Joseph Demczar, Eric C. Wieder
  • Patent number: 8976647
    Abstract: A network component comprising a hash generator configured to generate a first hash value using a first hash function and a packet, and generate a second hash value using a second hash function and the packet, a memory comprising a first hash table related to the first hash function and a second hash table related to the second hash function, the first and second hash tables comprising one or more entries, the one or more entries comprising a signature, a timestamp, and a path identification, a comparator configured to compare the first hash value and the second hash value with the one or more entries, and a forwarding decision module configured to forward the packet on a selected path.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: March 10, 2015
    Assignee: Futurewei Technologies, Inc.
    Inventor: Haoyu Song
  • Patent number: 8966200
    Abstract: Pruning free blocks out of a decremental backup chain. In one example embodiment, a method for pruning free blocks out of a decremental backup in a decremental backup chain includes identifying a decremental backup chain that includes one or more decremental backups of a source storage and a base backup of the source storage, identifying, for pruning, a target decremental backup in the decremental backup chain, retrieving one or more file system block allocation maps (FSBAMs) for points in time represented by the target decremental backup and represented by any of the other decremental backups in the decremental backup chain that depend on the target decremental backup, creating a master block allocation map (MBAM) by combining the one or more FSBAMs, and pruning free blocks, corresponding to block positions that are indicated as being free in the MBAM, out of the target decremental backup.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: February 24, 2015
    Assignee: Storagecraft Technology Corporation
    Inventor: Nathan S. Bushman
  • Patent number: 8959302
    Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: February 17, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Kondoh, Isao Ohara
  • Patent number: 8954648
    Abstract: The invention provides a memory device. In one embodiment, the memory device comprises a flash memory, a memory, and a controller. The flash memory comprises a plurality of blocks for data storage. The memory stores an address mapping table recording relationships between logical addresses and physical addresses of the blocks therein. The controller divides the address mapping table stored in the memory to a plurality of mapping table units, updates relationships between the logical addresses and the physical addresses stored in the mapping table units, determines whether data access performed to the flash memory fulfills the conditions of a first specific requirement, and when the data access fulfills the conditions of the first requirement, the controller selects a target mapping table unit from the mapping table units, and stores the target mapping table unit and a corresponding time stamp as a mapping table unit data to the flash memory.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: February 10, 2015
    Assignee: Via Technologies, Inc.
    Inventors: Liang Chen, Chen Xiu
  • Patent number: 8954694
    Abstract: A data storage device comprises a plurality of non-volatile memory devices configured to store a plurality of physical pages; a controller coupled to the plurality of memory devices that is configured to program data to and read data from the plurality of memory devices. A volatile memory may be coupled to the controller and may be configured to store a firmware table comprising a plurality of firmware table entries. The controller may be configured to maintain a plurality of firmware journals in the non-volatile memory devices. Each of the firmware journals may be associated with a firmware table entry and may comprise firmware table entry information. The controller may be configured to read the plurality of firmware journals upon startup and rebuild the firmware table using the firmware table entry information in each of the read plurality of firmware journals.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: February 10, 2015
    Assignees: Western Digital Technologies, Inc., Skyera, Inc.
    Inventors: Andrew J. Tomlin, Justin Jones, Rodney N. Mullendore
  • Patent number: 8949516
    Abstract: An object of the present invention is to realize a highly reliable long-life information processor capable of high-speed operation and easy to handle. The processor includes a semiconductor device comprising a nonvolatile memory device including a plurality of overwritable memory cells, and a control circuit device for controlling access to the nonvolatile memory device. The control circuit device sets assignments of second addresses to the nonvolatile memory device independently of first addresses externally supplied, such that the physical disposition of part of the memory cells used for writing of first data to be written externally supplied is one of the first to (N+1)th of every (N+1) memory cells (N: a natural number) at least in one direction.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: February 3, 2015
    Assignee: Hitachi, Ltd.
    Inventor: Seiji Miura
  • Patent number: 8949537
    Abstract: A processor transmits, to a communication control module, at least one write request packet with which at least one data block element configuring a data block is respectively associated, and updates a first counter to a value corresponding to the number of the transmitted write request packets. The communication control module writes a data block element associated with the write request packet to a cache memory, updates a third counter to a value corresponding to the number of the transmitted data block elements, and reflects the third counter to a second counter. The processor determines that the data block is written to the cache memory when the second counter reaches the first counter after all write request packets are transmitted.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: February 3, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Moritoki, Shohei Asakawa, Takeshi Yamauchi, Suguru Shimotaya
  • Patent number: 8949574
    Abstract: A method is comprised of inputting a comparand word to a plurality of hash circuits, each hash circuit being responsive to a different portion of the comparand word. The hash circuits output a hash signal which is used to enable or precharge portions of a CAM. The comparand word is also input to the CAM. The CAM compares the comparand word in the precharged portions of the CAM and outputs information responsive to the comparing step. When used to process Internet addresses, the information output may be port information or an index from which port information may be located. A circuit is also disclosed as is a method of initializing the circuit.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Keith R. Slavin
  • Patent number: 8938469
    Abstract: An example hashing unit includes a plurality of hardware-based hash tables, wherein each of the hash tables comprises a plurality of buckets, and wherein the plurality of hash tables comprise a set of zero or more active hash tables and a set of one or more inactive hash tables. An example hashing unit controller is configured to receive a key value to be stored in the hashing unit, determine that one of the inactive hash tables should be activated, and, based on the determination, activate the one of the set of inactive hash tables as a recently activated hash table, determine one of the buckets of the recently activated hash table to which a hash function associated with the recently activated hash table maps the received key value, and store the key value in the determined one of the buckets of the recently activated hash table.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: January 20, 2015
    Assignee: Juniper Networks, Inc.
    Inventors: John Keen, Jean-Marc Frailong, Deepak Goel
  • Patent number: 8914601
    Abstract: In a multi-processor (e.g., multi-core) computer system, several processors can simultaneously access data without corruption thereof by: designating to each processor a portion of a hash table containing the data; by allowing each processor to access only those data elements belonging to the portion of the hash table designated to that processor; and by sending, via a network, other data elements to the processors that are designated the portions of the hash table to which the other data elements belong. The network avoids memory contention at each processor without requiring a memory-based lock. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 16, 2014
    Assignee: Reservoir Labs, Inc.
    Inventors: Richard A. Lethin, Jordi Ros-Giralt, Peter Szilagyi
  • Patent number: 8914570
    Abstract: In a method for storing data in a flash memory array, the flash memory array includes a plurality of physical pages. The method includes receiving a request to perform a data access operation through a communication bus. The request includes data and a logical page address. The method further includes allocating one or more physical pages of the flash memory array to perform the data access operation. The method further includes, based on a historical usage data of the flash memory array, selectively encoding the data contained in the logical page into the one or more physical pages.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ganesh Balakrishnan, Anil Krishna
  • Patent number: 8914609
    Abstract: A computing device includes an interface, memory, and a processing module. The memory stores a directory and inode tables. The directory stores a file identifier and a corresponding inumber for each file that is stored in storage units. An inode table stores an inumber, metadata, and a DSN address for each file stored in a corresponding storage unit. The processing module is operable to monitor, for each of the inode tables, utilization of the memory. The processing module is further operable to monitor, for each of the storage units, utilization of memory of the storage units. The processing module is further operable to process, for the inode table and/or the corresponding storage unit, per inode table memory utilization data and per storage unit memory utilization data to adjust memory utilization of the inode table and/or memory utilization of the corresponding storage unit.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: December 16, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Jason K. Resch, Gary W. Grube, S. Christopher Gladwin
  • Patent number: 8904123
    Abstract: A virtual logical unit that stores learning metadata is allocated in a first storage server having a first plurality of clusters, wherein the learning metadata indicates a type of storage device in which selected data of the first plurality of clusters of the first storage server are stored. A copy services command is received to copy the selected data from the first storage server to a second storage server having a second plurality of clusters. The virtual logical unit that stores the learning metadata is copied, from the first storage server to the second storage server, via the copy services command. Selected logical units corresponding to the selected data are copied from the first storage server to the second storage server, and the learning metadata is used to place the selected data in the type of storage device indicated by the learning metadata.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joshua J. Crawford, Benjamin J. Donie, Andreas B. Koster
  • Patent number: 8898424
    Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: November 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Martin L. Culley, Troy D. Larsen
  • Patent number: 8880784
    Abstract: Disclosed is a method for managing logical block write requests for a flash drive. The method includes receiving a logical block write request from a file system; assigning a category to the logical block; and generating at least three writes from the logical block write request, a first write writes the logical block to an Erasure Unit (EU) according to the category assigned to each logical block, a second write inserts a Block Mapping Table (BMT) update entry to a BMT update log, and a third write commits the BMT update entry to an on-disk BMT, wherein the first and second writes are performed synchronously and the third write is performed asynchronously and in a batched fashion.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: November 4, 2014
    Assignee: Rether Networks Inc.
    Inventors: Tzi-cker Chiueh, Maohua Lu, Pi-Yuan Cheng, Goutham Meruva
  • Patent number: 8880829
    Abstract: Systems, methods, and apparatus with improved techniques for copying data from a source memory location to a destination memory location are disclosed. An exemplary method includes receiving a source address that indicates the source memory location, a destination address that indicates the destination memory location, and receiving a size indicator that indicates the size of the data. When the size is less than a threshold size, a particular pointer in a jump table is accessed, based upon the size that points to particular load and store instructions. The jump table includes a plurality of pointers that point to a corresponding one of a plurality of load and store instructions. The particular load-store instructions are then executed with a processor of the computing device to copy the data from the source memory location to the destination memory location. Several other efficiency-improvement aspects are also disclosed that may be used in connection with these steps to further improve copy efficiencies.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: November 4, 2014
    Assignee: Qualcomm Innovation Center, Inc.
    Inventors: Gregory A. Reid, Terence J. Lohman, Brent L. Degraaf
  • Patent number: 8868822
    Abstract: A data-processing method in a flash memory with a plurality of sectors, the method includes arranging first data which is not updated in a first sector at a leading portion of a second sector and adding a first identifier of the first data to the second sector by a memory control circuit when transferring data in the first sector to the second sector, the plurality of sectors including the first sector and the second sector.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: October 21, 2014
    Assignee: Spansion LLC
    Inventor: Hiroyuki Komori
  • Patent number: 8868865
    Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: October 21, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Kondoh, Isao Ohara
  • Patent number: 8868847
    Abstract: Systems, methods, and devices for reducing snoop traffic in a central processing unit are provided. In accordance with one embodiment, an electronic device includes a central processing unit having a plurality of cores. A cache memory management system may be associated with each core that includes a cache memory device configured to store a plurality of cache lines, a page status table configured to track pages of memory stored in the cache memory device and to indicate a status of each of the tracked pages of memory, and a cache controller configured to determine, upon a cache miss, whether to broadcast a snoop request based at least in part on the status of one of the tracked pages in the page status table.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: October 21, 2014
    Assignee: Apple Inc.
    Inventor: Jeffry Gonion
  • Patent number: 8862860
    Abstract: Methods and apparatus may operate to receive allocation requests from a processor configured to manage memory comprising a non-volatile memory device configurable as a plurality of blocks comprising a plurality of sectors, assign partial page blocks from the plurality of blocks for memory storage, fill some of the sectors by storing data bits associated with the allocation request in the at least one of the plurality of sectors, determine that the sectors are full, assigning a full page block from the plurality of blocks, and transfer the data bits associated with the allocation request from the partial page blocks to the full page block. Other apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: October 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Viet Ly, Michael Murray
  • Patent number: 8856425
    Abstract: A method for performing meta block management is provided. The method is applied to a controller of a Flash memory having multiple channels, where the Flash memory includes a plurality of blocks respectively corresponding to the channels. The method includes: utilizing a meta block mapping table to store block grouping relationships respectively corresponding to a plurality of meta blocks, where blocks in each meta block respectively correspond to the channels; and when it is detected that a specific block corresponding to a specific channel within a meta block does not have remaining space for programming, according to the meta block mapping table, utilizing at least one blank block corresponding to the specific channel within at least one other meta block as extension of the specific block, for use of further programming. An associated memory device and a controller thereof are also provided.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: October 7, 2014
    Assignee: Silicon Motion Inc.
    Inventor: Yang-Chih Shen
  • Patent number: 8850159
    Abstract: Methods and systems for latency optimized ATS usage are disclosed. Aspects of one method may include communicating a memory access request using an untranslated address and also an address translation request using the same untranslated address, where the translation request may be sent without waiting for a result of the memory access request. The memory access request and the address translation request may be made in either order. A translation agent may be used to translate the untranslated address, and the translated address may be communicated to the device that made the memory access request. The translated address may also be used to make the memory access. Accordingly, by communicating the translated address without having to wait for completion of the memory access, or vice versa, the requesting device may reduce latency for memory accesses when using untranslated addresses.
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: September 30, 2014
    Assignee: Broadcom Corporation
    Inventors: Jacob Carmona, Eliezer Aloni, Yuval Eliyahu, Rafi Shalom
  • Patent number: 8838915
    Abstract: The present invention may provide a computer system including a plurality of tiles divided into multiple virtual domains. Each tile may include a router to communicate with others of said tiles, a private cache to store data, and a spill table to record pointers for data evicted from the private cache to a remote host, wherein the remote host and the respective tile are provided in the same virtual domain. The spill tables may allow for faster retrieval of previously evicted data because the home registry does not need to be referenced if requested data is listed in the spill table. Therefore, embodiments of the present invention may provide a distance-aware cache collaboration architecture without incurring extraneous overhead expenses.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: September 16, 2014
    Assignee: Intel Corporation
    Inventors: Ahmad Samih, Ren Wang, Christian Maciocco, Tsung-Yuan C. Tai
  • Patent number: 8838922
    Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: September 16, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Kondoh, Isao Ohara
  • Patent number: 8806174
    Abstract: A system and method are disclosed for storing data in a hash table. The method includes receiving data, determining a location identifier for the data wherein the location identifier identifies a location in the hash table for storing the data and the location identifier is derived from the data, compressing the data by extracting the location identifier; and storing the compressed data in the identified location of the hash table.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: August 12, 2014
    Assignee: STEC, Inc.
    Inventors: Mohammad Reza Sadri, Saied Kazemi, Siddharth Choudhuri
  • Patent number: 8788791
    Abstract: A comparand word is input to a plurality of hash circuits with each hash circuit responding to a different portion of the comparand word. The hash circuit outputs a hash signal which enables or pre-charges portions of a content addressable memory (CAM). The comparand word is also input to the CAM. The CAM compares the comparand word in the pre-charged portions of the CAM and outputs information responsive to the comparison. When Internet addresses are processed, the output information may be port information or an index for locating.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Keith R. Slavin
  • Patent number: 8788784
    Abstract: A method and device for storing and reading/writing a composite document are disclosed. The method includes: an initial storing area is pre-allocated for an inner controlling stream of the composite document and the initial storing area is continuous sectors or sector clusters; the inner controlling stream is stored in the initial storing area. The patches of a user data stream and the inner controlling stream in the composite document are reduced using the method or device. Correspondingly, pre-allocating storing area makes the probability of continuously storing the user data stream and the inner controlling stream in the composite document increased. The I/O can be optimized by introducing a strategy of reading cache and writing in a batch size, which can improve the efficiency of reading and writing.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: July 22, 2014
    Assignee: Tencent Technology (Shenzhen) Company Limited
    Inventors: Libo Deng, Yi Chen
  • Patent number: 8782344
    Abstract: A cache layer leverages a logical address space and storage metadata of a storage layer (e.g., storage layer) to cache data of a backing store. The cache layer maintains access metadata to track data characteristics of logical identifiers in the logical address space, including accesses pertaining to data that is not in the cache. The access metadata may be separate and distinct from the storage metadata maintained by the storage layer. The cache layer determines whether to admit data into the cache using the access metadata. Data may be admitted into the cache when the data satisfies cache admission criteria, which may include an access threshold and/or a sequentiality metric. Time-ordered history of the access metadata is used to identify important/useful blocks in the logical address space of the backing store that would be beneficial to cache.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: July 15, 2014
    Assignee: Fusion-io, Inc.
    Inventors: Nisha Talagala, Swaminathan Sundararaman, Amar Mudrankit
  • Patent number: 8775772
    Abstract: Methods and apparatus for enhanced READ and WRITE operations in a FLASH-based solid state storage system that includes a logical to physical translation table where the logical to physical translation table can include entries associating a logical block address with one or more data identifiers, where each data identifier is associated with a data string.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: James A. Fuxa, Lance W. Shelton, Justin C. Haggard
  • Patent number: 8756400
    Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: June 17, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Martin L. Culley, Troy D. Larsen
  • Patent number: 8750119
    Abstract: Some embodiments provide a controller for managing a plurality of managed switching elements that forward data through a network. The controller comprising a first set of tables for storing input logical control plane data, and a second set of tables for storing output logical forwarding plane data. It also includes a table mapping engine for mapping the input logical control plane data in the first set of tables to output logical forwarding plane data in the second set of tables by performing a set of database join operations on the input logical control plane data in the first set of tables. The logical forwarding plane data is subsequently translated into physical forwarding behaviors that direct the forwarding of data by the managed switching elements.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: June 10, 2014
    Assignee: Nicira, Inc.
    Inventors: W. Andrew Lambeth, Teemu Koponen, Pankaj Thakkar, Alexander Yip, Martin Casado
  • Patent number: 8750144
    Abstract: Aspects of the invention provide for updating TCAMs while minimizing TCAM entry updates to add/delete ACL rules. For example, one aspect provides a method for minimizing updates in a router forwarding table, such as a TCAM, including a plurality of rules indexed by priority. This method comprises providing a proposed rule to be added to the router forwarding table, identifying a range of candidate entries in the router forwarding table for the proposed rule, determining a minimum set of rules to relocate, and creating an empty entry in the range of candidate entries based upon the minimum set of rules to relocate. The method may further comprise reallocating the minimum set of rules by, for example, shifting the minimum set of rules in sequence based on priority, and adding the proposed rule to the empty entry in the range of candidate entries.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: June 10, 2014
    Assignee: Google Inc.
    Inventors: Junlan Zhou, Zhengrong Ji
  • Patent number: 8736631
    Abstract: The display color of, for example, a button image responsive to a command input into a facility operation display device is controlled by a palette value having a smaller number of bits than an RGB value. When the display color of the button image is changed, the palette value of a drawing object associated with the button image is changed to an RGB value. This eliminates the necessity of incorporating, for example, a high-performance CPU as a central arithmetic unit. In addition, it is not necessary to pre-store images corresponding to several kinds of display colors specified by RGB values, to thereby eliminates the necessity of incorporating, for example, a high-capacity storage medium in the facility operation display device. Accordingly, the device cost can be reduced.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: May 27, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuya Mukai, Masanori Nakata, Yoshiaki Koizumi, Makoto Katsukura, Noriyuki Kushiro
  • Patent number: 8723870
    Abstract: Systems, servers, methods, media, and programs for storing a list of options associated with object-types, such as a chart-type, selected during an on-line session. When a new object-type is selected, some of the options in the first object-type are copied from the options list associated with the first object-type to the options list associated with the second (new) object-type. The list of options to be transferred is determined by a set rules associated with a transferable array and a set of rules associated with a quarantine set. The transferrable array includes rules for options available for transfer, and quarantine list includes rules for options and type pairs that are not available for transfer.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: May 13, 2014
    Assignee: Google Inc.
    Inventors: Daniel Libicki, Hillel Maoz
  • Patent number: 8719546
    Abstract: Embodiments of techniques and systems for using substitute virtualized-memory page tables are described. In embodiments, a virtual machine monitor (VMM) may determine that a virtualized memory access to be performed by an instruction executing on a guest software virtual machine is not allowed in accordance with a current virtualized-memory page table (VMPT). The VMM may select a substitute VMPT that permits the virtualized memory access, In scenarios where a data access length for the instruction is known, the substitute VMPT may include full execute, read, and write permissions for the entire guest software address space. In scenarios where a data access length for the instruction is not known, the substitute VMPT may include less than full execute, read, and write permissions for the entire guest software address space, and may be modified to allow the requested virtualized memory access. Other embodiments may be described and claimed.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: May 6, 2014
    Assignee: Intel Corporation
    Inventors: Baohong Liu, Manohar R. Castelino, Kuo-Lang Tseng, Ritu Sood, Madhukar Tallam
  • Patent number: 8694752
    Abstract: A method begins by a processing module determining an imbalance between inode utilization and data storage utilization. When the imbalance compares unfavorably to an imbalance threshold, the method continues with the processing module determining whether utilization of another inode memory and utilization of another corresponding data storage memory are not imbalanced. When the utilization of the other inode memory and the utilization of the other corresponding data storage memory are not imbalanced, determining whether the inode utilization is out of balance with respect to the data storage utilization. When the inode utilization is out of balance, the method continues with the processing module transferring data objects from a data storage memory to the other corresponding data storage memory and transferring mapping information of data objects from a inode memory to the other inode memory.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: April 8, 2014
    Assignee: Cleversafe, Inc.
    Inventors: S. Christopher Gladwin, Jason K. Resch
  • Patent number: 8694750
    Abstract: Embodiments of the present invention are directed to a method and system for allowing data structures to be moved between storage locations of varying performance and cost without changing the application firmware. In one embodiment, rather than application firmware directly accessing memory, the application firmware requests a data structure by parameters, to which the implementation returns a pointer. The parameters can be, for example, the logical block address of a data sector, and the data structure can be mapping and associated information of that logical block address (LBA) to a location in the flash device.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: April 8, 2014
    Assignee: NVIDIA Corporation
    Inventors: Dmitry Vyshetsky, Paul Gyugyi
  • Patent number: 8688949
    Abstract: A method begins by a processing module determining an imbalance between inode memory utilization and data storage memory utilization. When the imbalance compares unfavorably to an imbalance threshold, the method continues with the processing module determining whether the inode memory utilization is out of balance with respect to the data storage memory utilization or whether the data storage memory utilization is out of balance with respect to the inode memory utilization. When the inode memory utilization is out of balance with respect to the data storage memory utilization, the method continues with the processing module transferring a set of data objects from a data object section to a data block section and transferring object mapping information of the set of data objects into block mapping information for the set of data objects.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: April 1, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Jason K. Resch, Gary W. Grube, S. Christopher Gladwin
  • Patent number: 8683173
    Abstract: The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation. Subsequently, in response to detecting the formatting operation, the method includes inspecting format information on the memory unit, calculating a logical address offset, and applying the offset to a host logical address.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Mehdi Asnaashari, William E. Benson
  • Patent number: RE45097
    Abstract: An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: August 26, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Sundar Iyer, Nick McKeown