Abstract: A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references used by routines in the code. In a suitably equipped processing system, the reference tables can be passed to a memory management processor which can open the appropriate memory pages to expedite the retrieval of data referenced in the execution pipeline. The disclosed method and system create such reference tables at the beginning of each routine so that the table can be passed to the memory management processor in a suitably equipped processor. Resulting object code also allows processors lacking a suitable memory management processor to skip the reference table, preserving upward compatibility.

Abstract: A controller can process an instruction directed to the controller itself to access data in the memory of the controller dynamically at runtime, where the data can be indirectly accessed by referencing a tag name, associated with the data and a memory space in memory, which can be included in a string tag associated with the instruction. Multiple tags, each tag associated with a respective item of data, can be located or referenced dynamically at runtime to access the respective items of data where one tag can be associated with a first structure, array, and/or scope and a disparate tag can be associated with a disparate structure, array, and/or scope, via an instruction.

Abstract: Several deterrence mechanisms suitable for content distribution networks (CDN) are provided. These include a hash-based request routing scheme and a site allocation scheme. The hash-based request routing scheme provides a way to distinguish legitimate requests from bogus requests. Using this mechanism, an attacker is required to generate O(n2)amount of traffic to victimize a CDN-hosted site when the site content is served from n CDN caches. Without these modifications, the attacker must generate only O(n) traffic to bring down the site. The site allocation scheme provides sufficient isolation among CDN-hosted Web sites to prevent an attack on one Web site from making other sites unavailable. Using an allocation strategy based on binary codes, it can be guaranteed that a successful attack on any individual Web site that disables its assigned servers, does not also bring down other Web sites hosted by the CDN.

Abstract: Storage network arrangements effecting a method including: acquiring information on the real volumes, and port information on the physical devices in which the real volumes reside; creating virtual volumes being linked to the real volumes, based on the information on the real volumes; forming one or more virtual volume groups by combining the virtual volumes, based on the port information, in such a way that the virtual volumes and the virtual volume groups in which the virtual volumes reside have a virtual-volume-to-virtual-volume-group configuration which is identical to a real-volume-to-physical-device configuration of the real volumes and the physical devices in which the real volumes reside; and establishing the created virtual volume groups in the upper storage apparatus.

Abstract: A system and method of using an n-way cache are disclosed. In an embodiment, a method includes determining a first way of a first instruction stored in a cache and storing the first way in a list of ways. The method also includes determining a second way of a second instruction stored in the cache and storing the second way in the list of ways. In an embodiment, the first way may be used to access a first cache line containing the first instruction and the second way may be used to access a second cache line containing the second instruction.

Abstract: A method of automatically adjusting parameters of a display device is provided. The method includes: measuring a current distance between a user and the display device; determining a particular distance range which the current distance falls in; determining corresponding parameter values of the particular distance range according to a parameter management table which lists a series of distance ranges and corresponding parameter values of the display device; transmitting the parameter values to the display device; adjusting parameters of the display device according to the parameter values.

Abstract: A method, system, apparatus, and computer-readable medium are provided for improving storage in a disk array are provided. According to aspects of the invention, a redundant disk array is combined with a mechanism for thin provisioning of the array. Thin provisioning refers to a process of allocating physical capacity to logical volumes on an as-needed basis. Data structures containing a mapping between the logical location of stored data and its actual location on a physical device are maintained. Through the use of the thin provisioning mechanism, physical storage space can be allocated sequentially, regardless of the order of logical writes. In this manner, the data stored on the array grows in a linear manner. The data structures maintained by the thin provisioning mechanism can be used to identify the portions of a device or an array that have been previously written.

Abstract: An electronic device has a reception unit that can receive satellite signals transmitted from positioning information satellites and acquire positioning information and time information, a time difference data storage means in which a data table and a memory address table are stored, and a time difference data acquisition means that acquires time difference data corresponding to positioning information acquired by the reception unit from the time difference data storage means. The data table is compiled by dividing geographical information to which time difference data is assigned into segments of a constant size, setting only one time difference in each segment, grouping the segments into blocks each containing a specific number of segments, and storing the time difference data of each segment as block data by block unit while storing the block data only once for blocks containing the same time difference data array and storing the block data for mutually different time difference data arrays once each.

Abstract: A method of utilizing NAND type memory is disclosed herein. Operating system type instructions executable by a processor can be stored in a NAND based memory. The instructions can have logical addresses that can be utilized by the processor to fetch the operating system instructions. The method can store address conversions in the NAND based memory, where the address conversions can relate logical addresses to a physical address. At least one validity flag can be assigned to the address conversions. The processor can perform a direct read of the operating system instructions from the NAND based memory in response to a first setting of a validity flag and the processor can perform an indirect read of the operating system instructions by fetching an address conversion from the NAND based memory in response to a second setting of the at least one validity flag.

Abstract: In PCI-Express and alike network systems, back-up copies of recently sent packets are kept in a replay buffer for resending if the original packet is not well received by an intended destination device. A method for locating the back-up copy in the retry buffer comprises applying a less significant portion of the sequence number of a to-be-retrieved back-up copy to an index table to obtain a start address or other locater indicating where in the retry buffer the to-be-retrieved back-up copy resides. A method for skipping replay of late nullified packets includes deleting from the index table, references to late nullified packets.

Abstract: Embodiments of the present disclosure provide methods, apparatuses and systems including a storage configured to store and output multiple address strides of varying sizes to enable access and precharge circuitry to access and precharge a first and a second group of memory cells based at least in part on the multiple address strides during operation of the host apparatus/system, the first and second group of memory cells being different groups of memory cells.

Abstract: A system and method for performing vector arithmetic is disclosed. The method includes loading two operand vectors, each composed of a number of vector elements, into two storage locations. A selected arithmetic operation is performed on the operand vectors to produce a result vector having the number of vector elements. Each vector element of the result vector is associated with an arithmetic logic cell that has a first input that can receive any vector element from the first vector and a second input that can receive any vector element from the second vector. Accordingly each vector element of the result vector is a function of any two individual vector elements of the operand vectors. By applying the operand vector elements to the appropriate arithmetic logic cells, and by selecting the appropriate arithmetic operation, complex vector operations can be performed efficiently.

Abstract: A method for classifying a data packet containing a header is provided. The method may comprise parsing the header of a data packet into header elements. Rules in secondary lookup tables generated from a primary lookup table may be accessed. The respective header elements of the data packet may be compared to the respective fields of each of the secondary lookup tables, and rule results for each of the secondary lookup tables in a combinable format may be generated. In another embodiment, a method for generating secondary lookup tables from a primary lookup table is provided. The method may comprise accessing a primary lookup table defining packet classification rules and generating multiple secondary lookup tables from the primary lookup table. For each secondary lookup table, a selection of classification rules and a selection of fields of the multiple fields based on a rule set identifying predefined entries may be extracted.

Abstract: A computer system has secondary data that is derived from primary data, such as entries in a TLB being derived from entries in a page table. When an actor changes the primary data, a producer indicates the change in a set data structure, such as a data array, in memory that is shared by the producer and a consumer. There may be multiple producers and multiple consumers and each producer/consumer pair has a separate channel. At coherency events, at which incoherencies between the primary data and the secondary data should be removed, consumers read the channels to determine the changes, and update the secondary data accordingly. The system may be a multiprocessor virtual computer system, the actor may be a guest operating system, and the producers and consumers may be subsystems within a virtual machine monitor, wherein each subsystem exports a separate virtual central processing unit.

Abstract: Provided are a method for Ternary Contents Address Memory (TCAM) table management and a computer-readable recording medium for recording a program that implements the method. The method includes the steps of: a) dividing a memory area of TCAM into fixed-size blocks depending on priority to configure a lookup table; b) assigning a priority to each routing entry being inputted to the lookup table based on prefix length; c) storing the routing entry having been assigned with the priority in a lookup table block of a corresponding priority; and d) when a modification occurs in the lookup table, modifying the lookup table to maintain an arranged state for a longest prefix match.

Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing engine and a memory system such that write data is buffered and information based upon reads and writes is recorded. Memory read data is returned speculatively since the packet processing engine is processing packets in parallel and not necessarily in sequence. Information is maintained allowing the detection of a speculative read that was incorrect (i.e. a memory conflict). When a memory conflict is detected, a restart signal is generated and the information for the associated packet identifier or sequence number is flushed.

Abstract: There is provided a process management system which, when a crash occurs in execution of a processing process, can immediately restart a processing process while holding data used in occurrence of the crash as much as possible. When a determination unit determines that a detected crash is not a crash caused by data used in a processing process, a processing unit reexecutes the processing process in which the crash occurs. When the determination unit determines that the detected crash is a crash caused by the data used in the processing process, an initialization unit initializes the data used in the processing process.

Abstract: The invention relates to a memory index management system. The said system comprises an indexed storage memory, a memory zone containing the index and a microprocessor. The index is built in the form of a hierarchical tree structure and comprises at least two nodes. A node contains an identifier associated with a pointer that references either a node of the index or a memory zone in the storage memory. The content of a node is distributed over a first and a second memory zone that are separate in the memory zone. The first space has a first specific pointer that points to the second space and the second space has a second specific pointer whose value has a blank state.

Abstract: The present invention provides an improved way to calculate a replacement way within a processor cache that is effective with different combinations of hardware address translation cache miss handling, software address translation cache miss handling, and hint lock bits. For some embodiments, LRU bits used to select an entry for replacement are updated only if software address translation cache miss handling is disabled. Further, for some embodiments, LRU bits may be modified to change the way a binary tree structure is traversed to avoid selecting a hint locked entry for replacement.

Abstract: A multi-level lookup table includes a plurality of search levels with each search level including a plurality of subtrees, each subtree representing a plurality of nodes. A search of the multi-level lookup table for an entry corresponding to a search key results in a value stored in an entry associated with the node in a subtree. A default value is associated with the root of the subtree. Multiple entries for the subtree can store the default value. To minimize route update time, the default value associated with the subtree is stored in a single location. Instead of storing the default value in multiple entries, each entry stores a use default indicator to indicate that the default value stored in the single location is to be used. To further reduce the number of locations to modify to update the default route, the single location can store an inherit indicator to indicate that the default value for the subtree is inherited from another subtree.

Abstract: A data storage apparatus is provided. The data storage apparatus includes: a storage unit managed using a logical block address; a memory; a storage control unit for storing in the storage unit a free area control table transmitted from the host apparatus in which information on a free area in the storage unit is stored; an expanding unit for reading the free area control table in the storage unit and expanding it in the memory; a recording unit for recording data transmitted from the host apparatus into a free area in the storage unit on the basis of the free area control table in the memory; an updating unit for updating the free area control table in the memory after the data recording unit has completed a recording operation; and a transmission unit for transmitting to the host apparatus updated information included in the free area control table which has been updated by the updating unit.

Abstract: [Problems] To provide a highly efficient pseudo-random number generation device which can be used in a small-scale computer and a mobile terminal. [Means for Solving Problems] A memory table having n elements is prepared. A unique value is set for each of the n elements. By changing the contents of the respective elements in the memory table so as to change the memory table state. The change is extracted as a random number. Thus, it is possible to obtain a random number table of a cycle of power n at the maximum.

Abstract: A method, system, apparatus, and computer-readable medium are provided for improving storage in a disk array are provided. According to aspects of the invention, a redundant disk array is combined with a mechanism for thin provisioning of the array. Thin provisioning refers to a process of allocating physical capacity to logical volumes on an as-needed basis. Data structures containing a mapping between the logical location of stored data and its actual location on a physical device are maintained. Through the use of the thin provisioning mechanism, physical storage space can be allocated sequentially, regardless of the order of logical writes. In this manner, the data stored on the array grows in a linear manner. The data structures maintained by the thin provisioning mechanism can be used to identify the portions of a device or an array that have been previously written.

Abstract: Flash memory is accessed via mapping tables comprising a master mapping table and at least one secondary mapping table. The master mapping table contains indexes to the secondary mapping tables. The secondary mapping tables contain indexes to locations in the flash memory. The mapping tables are maintained in the flash memory. Upon initialization subsequent a safe power shutdown, the master mapping table is cached and secondary mapping tables are cached as needed. Upon initialization subsequent an unsafe power shutdown, the mapping tables are constructed in accordance with a multiple-phase process. In an example embodiment, the multiple-phase process comprises locating all the secondary mapping tables stored in the flash memory, determining which secondary mapping tables are valid, determining which secondary mapping tables are invalid, determining which sectors of the flash memory are free, and constructing the master mapping table and the secondary mapping tables from this information.

Abstract: A method, system and program product for equitable sharing of a CAM (Content Addressable Memory) table among multiple users of a switch. The method includes reserving buffers in the table to be shared, the remaining buffers being allocated to each user. The method further includes establishing whether or not an address contained in a packet from a user is listed in a buffer in the table, if the address is listed, updating a time-to-live value for the buffer for forwarding the packet and, if the address is not listed, determining whether or not the user has exceeded its allocated buffers and whether or not the reserved buffers have been exhausted, such that, if the user has exceeded its allocated buffers and the reserved buffers have been exhausted, the address is not added to the table and the user is precluded from using any additional buffers in the network switch.

Abstract: A method of searching a data page in a table space of a database for inserting a data record to a first table, wherein the table space comprises space map pages and sets of data pages, wherein each space map page comprises information about the available storage space of one set of data pages, wherein each space map page and the corresponding set of data pages is further assigned to a table range for each table to which at least one data page in the set of data pages belongs to, wherein the database further comprises a clustering index for the first table in the database management system, wherein the database management system comprises a space usage information database, and wherein the space usage information database holds space usage information for each table range.

Abstract: A mass storage controller includes a packet filter module for receiving a packet containing an updated sector of a remote file allocation table from a host device. The packet filter module is further operable for scanning the updated sector contents to determine their state. The updated sector is written to a local file allocation table of a local device when the state of the updated sector contents match a first state. An original sector of the local file allocation table corresponding to the updated sector is retained when the state of the updated sector contents match a second state.

Abstract: A method or device handles memory management faults in a device having a digital signal processor (“DSP”) and a microprocessor. The DSP includes a memory management unit (“DSP MMU”) to manage memory access by the DSP, and the DSP and the microprocessor access shared physical memory. Upon the DSP executing an instruction attempting to access a virtual address wherein the virtual address is invalid, a page fault interrupt is generated by the DSP MMU. A microprocessor interrupt handler in the microprocessor is activated in direct response to the page fault interrupt. Thereafter in the microprocessor, a translation lookaside buffer (“TLB”) entry is created in the DSP MMU, which includes a valid mapping between the virtual address and a page of physical memory. After creating the TLB entry, the microprocessor indicates to the DSP that the access by the DSP of the virtual address is completed.

Abstract: A “LUN Table” enables Logical Unit Number (LUN) mapping/masking within an IOV adapter included in a Serial Attached Small Computer System Interface (“SAS” or “Serial Attached SCSI”). A plurality of System Images (“SI”) share block storage through the SAS. The IOV adapter includes one or more Virtual Functions (VF), a Physical Function (PF), and a LUN Table within the PF. The VF allows each SI to communicate I/0 requests with a storage device through the PF. The LUN Table maps the I/0 requests to unique locations within the storage device. Each SI is isolated from all other SIs. Interference between each SI is avoided. A VIOS or a LUN mapping/masking SAN are not required. I/0 latency, processor overhead and storage cost are improved over prior LUN mapping/masking solutions.

Abstract: Systems, methods and media for selectively closing pages in a memory in anticipation of a context switch are disclosed. In one embodiment, a table is provided to keep track of open pages for different processes. The table comprises rows corresponding to banks of memory and columns corresponding to cores of a multi-core processing system. When a context switch signal is received, the system unsets a bit in a column corresponding to the core from which the process is to be context-switched out. If no other process is using a page opened by the process the page is closed.

Abstract: A restrictive multi-level-cell (MLC) flash memory prohibits regressive page-writes. When a regressive page-write is requested, an empty block having a low wear-level count is found, and data from the regressive page-write and data from pages stored in the old block are written to the empty block in page order. The old block is erased and recycled. A two-level look-up table is stored in volatile random-access memory (RAM). A logical page address from a host is divided by a modulo divider to generate a quotient and a remainder. The quotient is a logical block address that indexes a first-level look-up table to find a mapping entry with a physical block address that selects a row in a second-level look-up table. The remainder locates a column in the row in the second-level look-up table. If any page-valid bits above the column pointed to by the remainder are set, the write is regressive.

Abstract: A mobile electronic device with NOR and/or NAND flash memory may be updated using an update agent able to perform fault tolerant updates. The efficiency of an update of the memory of the device may be significantly improved by employing memory management information provided by a generator used to produce update information for updating the memory. Erasures and writes to blocks of flash memory may be reduced by mapping a logical block layout to a physical block layout that helps avoid moves of memory blocks to be updated. Fault tolerance of the update process is maintained.

Abstract: Mapping tables are for stipulating information for primarily identifying computers, information for identifying a group of the computers and a logical unit number permitting access from the host computer inside storage subsystem, in accordance with arbitrary operation method by a user, and for giving them to host computer. The invention uses management table inside the storage subsystem and allocates logical units inside the storage subsystem to a host computer group arbitrarily grouped by a user in accordance with the desired form of operation of the user, can decide access approval/rejection to the logical unit inside the storage subsystem in the group unit and at the same time, can provide the security function capable of setting interface of connection in the group unit under single port of storage subsystem without changing existing processing, limitation and other functions of computer.

Abstract: A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the appropriate memory pages to expedite the retrieval of information from memory referenced by instructions in the execution pipeline. A suitable compiler parses the source code and collects references to branch addresses, calls to other routines, or data references, and creates reference tables listing the addresses for these references at the beginning of each routine. These tables are received by the memory management processor as the instructions of the routine are beginning to be loaded into the execution pipeline, so that the memory management processor can begin opening memory pages where the referenced information is stored. Opening the memory pages where the referenced information is located before the instructions reach the instruction processor helps lessen memory latency delays which can greatly impede processing performance.

Abstract: In this invention, when execution of an special function executable only by a second storage control apparatus connected to a first storage control apparatus is requested by a higher-level apparatus, the special function is caused to be executed by a second storage control apparatus, and appropriate load balancing is achieved. An executing apparatus judgment section, upon receiving an execution request from a host, uses a function management section and a state detection section to decide which storage control apparatus should execute the function. An execution instruction section issues an instruction to execute the function to the function execution section of the storage control apparatus determined to be the executing apparatus. By this means, even in the case of an special function executable only by a storage control apparatus, the function can be caused to be executed.

Abstract: Techniques are provided for re-mapping and interleaving transport packets of multiple transport streams for processing by a single transport demultiplexor. At least one PID re-map table is employed having re-map values indexed by n possible PID values of transport packets associated with at one transport stream of the multiple transport streams. The n possible PID values is less than or equal to the number of PID values which can be handled by the single transport demultiplexor, and is less than all possible PID values of transport packets within the multiple transport streams. The PID values within at least one transport stream are compared with the n possible PID values of the PID re-map table, and when a match is found, the table is indexed using the matching entry and a re-map value is generated therefrom. The re-map value replaces the original PID value within the transport packet.

Abstract: Improved systems and methods for implementing data-driven protocols are provided. In one embodiment, improved implementations of multicast routing protocols are provided. Separation between multicast forwarding and control elements are provided by use of a powerful yet simple application program interface (API) for inter-module communication. The API is multicast-routing-protocol-independent and can be used to express the forwarding state of any existing multicast protocol. Efficient platform-specific implementations are facilitated.

Abstract: A state machine may be coupled to a memory management unit configuration table (MMUCT) stored in a memory to index an entry from the MMUCT. A parameter associated with the entry may be used to control operations associated with a memory management unit (MMU). The MMU may be used to control access to a set of page tables stored in the memory. Other embodiments may be described and claimed.

Abstract: An object of the present invention is to integrally manage disk storage apparatuses through virtualization. Some physical storage apparatuses 14 connected to a host computer 10 via a communication network 12 are virtualized with a virtual switch 18, a control unit 20, and a virtual device 22. The physical storage apparatus specifies a command when receiving the command from the host computer 10, and accesses, if the command access has been made to its own physical storage apparatus, a real disk via the virtual control unit 20 and virtual device 22, and executes I/O processing. If the command access is not made to its own physical storage apparatus, the physical storage apparatus 14 directs the command to the transmission target via the virtual switch 18. The physical storage apparatuses 14 are integrally managed according to the command in the above described manner.

Abstract: An improved system and method for removing a storage server in a distributed column chunk data store is provided. A distributed column chunk data store may be provided by multiple storage servers operably coupled to a network. A storage server provided may include a database engine for partitioning a data table into the column chunks for distributing across multiple storage servers, a storage shared memory for storing the column chunks during processing of semantic operations performed on the column chunks, and a storage services manager for striping column chunks of a partitioned data table across multiple storage servers. Any data table may be flexibly partitioned into column chunks using one or more columns with various partitioning methods. Storage servers may then be removed and column chunks may be redistributed among the remaining storage servers in the column chunk data store.

Abstract: Disclosed is a vector indexed memory unit and method of operation. In one embodiment a plurality of values are stored in segments of a vector index register. Individual ones of the values are provided to an associated operator (e.g., adder or bit replacement). Individual ones of the operators operates on its associated vector index value and a base value to generate a memory address. These memory addresses are then concurrently accessed in one or more memory units. If the data in the memory units are organized as data tables, the apparatus allows for multiple concurrent table lookups. In an alternate embodiment, in addition to the above described operators generating multiple memory addresses, an adder is provided to add the base value to the value represented by the concatenation of the bits in the vector index register to generate a single memory address.

Abstract: A method for relocating system management interface code in an information handling system which includes extracting a relocation table from the system management interface code, inserting a relocation identifier in each entry of the system management interface code having an address, searching the system management code for the relocation identifier during execution of the information handling system, and inserting an address based upon a relocation address for each entry in the system management interface code having a relocation identifier.

Abstract: A Hard Disk Drive (HDD) is provided two FATs and two cluster sizes, a regular cluster and a “Supercluster”. In one example, each Supercluster is the size of four regular clusters. A second Supercluster FAT is added (FAT2) which works in a similar manner to the original FAT (hereinafter FAT1), but instead points to the next Supercluster in the chain. Since there are far fewer Superclusters than clusters, the Supercluster FAT (FAT2) can be stored in a cache memory. When data is streamed to and from the hard drive, it can be streamed to Superclusters and no seeks on the HDD to a FAT are required, as the FAT2 is cached in memory. Access time to and from the hard drive is decreased. The original cluster configuration is still supported. During lulls in system operation, the FAT2 data may be written to the drive and moreover, FAT1 data created and “flushed” to the hard drive.

Abstract: A method for providing BGP route updates in an MPLS network is disclosed. The route update is performed at a router having a forwarding information table containing BGP routes and an internal label, and an adjacency table containing BGP/VPN labels and said internal label. The internal label corresponds to at least one IGP route and has an adjacency associated therewith. The method includes updating the adjacency associated with the internal label following an IGP route change.

Abstract: A method and system for improving the performance of a cache. The cache may include an array of tag entries where each tag entry includes an additional bit (“reused bit”) used to indicate whether its associated cache line has been reused, i.e., has been requested or referenced by the processor. By tracking whether a cache line has been reused, data (cache line) that may not be reused may be replaced with the new incoming cache line prior to replacing data (cache line) that may be reused. By replacing data in the cache memory that might not be reused prior to replacing data that might be reused, the cache hit may be improved thereby improving performance.

Abstract: Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command signal from a first communication register to retrieve a first set of data from memory according to a look up table of memory addresses. The first memory access generator reads the look up table of memory addresses, which contain a second set of memory commands and reroutes the second set of commands to a bypass register. In turn, the second set of memory commands stored at the bypass register are read by a second memory address generator which retrieves a second set of data from memory according to the second set of memory command signals read out of memory by the first memory address generator.

Abstract: An improved system and method for recovery from failure of a storage server in a distributed column chunk data store is provided. A distributed column chunk data store may be provided by multiple storage servers operably coupled to a network. A storage server provided may include a database engine for partitioning a data table into the column chunks for distributing across multiple storage servers, a storage shared memory for storing the column chunks during processing of semantic operations performed on the column chunks, and a storage services manager for striping column chunks of a partitioned data table across multiple storage servers. Any data table may be flexibly partitioned into column chunks using one or more columns with various partitioning methods. Storage servers may then fail and column chunks may be recreated from parity column chunks and redistributed among the remaining storage servers in the column chunk data store.

Abstract: A method of migrating data from an old storage subsystem to a new storage subsystem in a data processing system which comprises host computers and storage subsystems. There is provided a route-changing phase before the data is migrated from the old storage subsystem to the new storage subsystem. In the route-changing phase, each host computer can access both the old and new storage subsystems and the new storage subsystem writes data into the old storage subsystem in response to a write request from the host computer and reads data from the old storage subsystem and sends the data to the host computer in response to a read request from the host computer.

Abstract: A run level address mapping table and related method provides for storing address mapping data, which maps logical addresses to physical addresses in a flash memory using a flash translation layer. A first value is stored in the address mapping table, indicating an initial location for a run within a memory block, the run having at least two consecutive physical addresses. A second value is stored in the address mapping table, indicating a total size for the run.

Abstract: Using location-independent names to identify content, a service for mapping endpoint requests to requested content. Content requested by an endpoint of the network is mapped to a dynamic “swarm” of server, peer, or other endpoints capable of supporting the content download. Content names are mapped to a dynamically generated content swarm, presenting a current set of hosts, which can provide the requested content. Optionally, varying degrees of explicit visibility into routing paths and the performance tradeoffs between those routing paths is supported. Based on a set of class of service parameters for a given request for content, a host can initiate route selection based on class of service parameters, predicated on routing metrics maintained by the network by cooperating endpoints and/or network routers.